ASM-GaN: Industry Standard GaN HEMT Compact Model for Power-Electronics and RF Applications

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1 ASM-GaN: Industry Standard GaN HEMT Compact Model for Power-Electronics and RF Applications Dr. Yogesh S. Chauhan Associate Professor, Dept. of EE, IIT Kanpur, India *Editor of IEEE Trans. on Electron Device *TPC member of IEDM 2018, ESSDERC Homepage

2 Outline Overview of Compact Modeling GaN HEMT ASM-GaN-HEMT Model Model Validation 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 2

3 My Group and Nanolab Current members 30 Postdoc 5 Ph.D. 16 Seven PhD graduated Device Characterization Lab - Keysight B1500 IV/CV Parameter Analyzer - Keysight B1505 High Power IV/CV Analyzer - Maury s Pulsed IV/RF for GaN HEMTs - Keysight PNA-X 43.5GHz - Load-Pull system 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 3

4 Compact Modeling Industrial Research Bulk MOSFET Modeling (DC to RF) BSIM4 and BSIM-BULK (BSIM6) Partially Depleted SOI MOSFET Modeling (DC to RF) BSIM-SOI Multigate MOSFET Modeling FinFET & Nanowire Transistor BSIM-CMG Fully Depleted SOI (FDSOI) Transistor BSIM-IMG High Voltage LDMOS Modeling BSIM-HV GaN HEMT Modeling ASM-HEMT DC, CV and RF Characterization All models are validated on measured data 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 4

5 Joint Development & Collaboration 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 5

6 Analyzing Electronic System Source: Xing Zhou, NTU 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 6

7 SPICE and Device Models Ron Rohrer Special Issue on 40 th Anniversary of SPICE 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 7

8 Device Model Good SPICE model should be Accurate Produce trustworthy simulations Simple Simulation time is minimum Easy parameter extraction Balance between accuracy and simplicity depends on end application Creating a model that is both accurate and simple is by no means a simple task. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 8

9 Model Types Look Up Table Physical model generally does not have parameters but does not fit with data accurately. Empirical models are mathematical models written to reflect measured characteristics Angelov model for HEMT Compact SPICE models are the combination of physical and empirical methods. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 9

10 What is a Compact Model? 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 10

11 Compact MOSFET Model Compact Model Cgd=f2(Vgd, Vgs) Drain Gate Cgs=f3(Vgd, Vgs) Source Jds = f1(vds,vgs) TCAD Model 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 11

12 Compact model complexity I = V/R is a compact model for a resistor I = V/((q o +TCR*(T-25))*(L-dL)/(W-dW)) Add: Geometric Scaling Temperature Scaling 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 12

13 Compact model complexity I = V/R is a compact model for a resistor Jth TR Rth I = V/((q o +TCR*(VTR+T-25))*(L-dL)/(W-dW) Jth = V*I Rth=Rth/(L*W) Add: Geometric Scaling Temperature Scaling Self Heating 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 13

14 Effective Dimensions L1 L Weff W Drawn dimensions Poly after etch Contact after etch Current Flow Leff L1 accounts for etch bias Leff accounts for etch bias and spreading resistance 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 14

15 PDK and Compact Model 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 15

16 Enablers of a silicon chip design 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 16 Source: David HARAME at. al., IBM J. RES. & DEV. MARCH/MAY 2003

Goal of a PDK The output of Enablement Technology

! Circuit Designers Offer a circuit design environment

device physics Model impact of layout choices on device

simulation from schematic Accurate modeling of layout

17 Goal of a PDK The output of Enablement Technology Innovation Enablement PDK Key to Happy Designers!! Circuit Designers Offer a circuit design environment that enables full exploitation of technology Capture all device physics Model impact of layout choices on device mean and variance Include typical layout effects for simulation from schematic Accurate modeling of layout effects for simulation from layout 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 17

Balance between accuracy and simplicity depends on end application Excellent Convergence Simulation

18 Compact Modeling or SPICE Modeling Medium of information exchange Good model should be Accurate: Trustworthy simulations. Simple: Parameter extraction is easy. Balance between accuracy and simplicity depends on end application Excellent Convergence Simulation Time ~µsec Accuracy requirements ~ 1% RMS error after fitting Example: BSIM-BULK, BSIM- CMG, BSIM-IMG 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 18

19 Industry Standard Compact Models Standardization Body Compact Model Coalition CMC Members EDA Vendors, Foundries, IDMs, Fabless, Research Institutions/Consortia 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 19

physicality Model Process Variation Kit Integration Kit Test Release to

20 Compact Model Build Test site Specification Test site Layout Hardware build Measure data Fit to measured data Center model Test for convergence, physicality Model Process Variation Kit Integration Kit Test Release to customers 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 20 Curtesy: Josef Watts, IBM/GF

21 Challenges in Compact Modeling Materials (Si, Ge, III-V) Physics (Quantum Mechanics, Transport) Maths/ Computer Sc. (Compiler, Function speed, implementation, algorithms, smoothing, integration, PDE) SPICE Model Electronics (Circuit considerations Digital/Analog/RF/noise) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 21

22 Compact Model is Art Based on Science Output Conductance Current Saturation Quantization Gate Current GIDL Current Impact Ionization Current Noise models Mobility and Transport S/D Resistance Gate Resistance Short Channel Effects Core Overlap Capacitances Fringe Capacitances Inversion Layer Thickness Non-Quasi-Static Effects Substrate RC Network Parasitic Diode, BJT Self Heating Temperature Effects Proximity Effects Random Variations Y. S. Chauhan et.al., BSIM6: Analog and RF Compact Model for Bulk MOSFET, IEEE TED, /12/2018 Yogesh S. Chauhan, IIT Kanpur 22

BSIM Family of Compact Device Models 1990 1995 2000 2005 2010 BSIM1,2

Silicon on Insulator MOSFET BSIM-CMG BSIM-IMG Multi-Gate MOSFET BSIM:

23 BSIM Family of Compact Device Models BSIM1,2 BSIM3 BSIM4 Conventional MOSFET BSIMSOI BSIM5 BSIM-BULK (BSIM6) Silicon on Insulator MOSFET BSIM-CMG BSIM-IMG Multi-Gate MOSFET BSIM: Berkeley Short-channel IGFET Model 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 23

FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard Authors Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan,

24 FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard Authors Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan, Samsung Sourabh Khandelwal, UCB Ai Niknejad, UCB Chenming Hu, UCB Chapters 1. FinFET- from Device Concept to Standard Compact Model 2. Analog/RF behavior of FinFET 3. Core Model for FinFETs 4. Channel Current and Real Device Effects 5. Leakage Currents 6. Charge, Capacitance and Non-Quasi-Static Effect 7. Parasitic Resistances and Capacitances 8. Noise 9. Junction Diode Current and Capacitance 10. Benchmark tests for Compact Models 11. BSIM-CMG Model Parameter Extraction 12. Temperature Effects 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 24

25 Some Snapshots from recent work 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 25

26 Quantum Mechanical Effects Predictive model for confinement induced V th shift due to band splitting present in the model Effective Width model that accounts for reduction in width for a triple / quadruple / surround gate structure BOX FinFET/Nanosheet Transistor Width reduction due to structural confinement of inversion charge. (Dotted lines represent the effective width perimeter) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 26 S. Venugopalan et. al., IEEE TED, 2013

27 Modeling of III-V Channel DG-FETs Conduction band nonparabolicity 2-D density of states Quantum capacitance in low DOS materials Contribution of multiple subbands C. Yadav et. al., Compact Modeling of Charge, Capacitance, and Drain Current in III-V Channel Double Gate FETs, IEEE TNANO, /12/2018 Yogesh S. Chauhan, IIT Kanpur 27

28 Modeling of Quasi-ballistic Nanowire FETs 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 28

Channel Halo Implanted MOSFETs: Analysis

29 Modeling of Long Channel Halo Implanted MOSFETs Part of BSIM-BULK (BSIM6) Model H. Agarwal et. al., "Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling", IEEE TED, Feb /12/2018 Yogesh S. Chauhan, IIT Kanpur 29

Modeling of TMD transistor 2D density of

Dichalcogenide based Thin body Transistors

30 Modeling of TMD transistor 2D density of state Fermi Dirac statistics Trapping effects C. Yadav et. al. Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation, IEEE TED, March /12/2018 Yogesh S. Chauhan, IIT Kanpur 30

31 News (March 14, 2018) Our ASM-GaN-HEMT Model is industry standard SPICE Model for GaN HEMTs Download /12/2018 Yogesh S. Chauhan, IIT Kanpur 31

32 Media Coverage (April 11, 2018) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 32

33 GaN Attractions & Avenues Size Comparison Size comparison of Si power MOSFET with GaN HEMT from EPC for same performance [1] GaAs Industry players for power applications as of 2012 GaN Size comparison of RF HEMTs based on GaAs and GaN technologies from Qorvo Source: S. Levin, Tech. Rep., Power Petrov Group, [2013] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 33

34 RF Market 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 34

35 Power Transistor Market Source: Electronics Weekly 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 35

36 GaN Properties Device characteristics: High Breakdown Voltage (VV BBBB ) Low ON Resistance (RR OOOO ) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 36

GaN HEMT Some interesting features of III-nitride system:

High breakdown voltage Excellent thermal conductivity High

operate in high frequency, high power as well as high

37 GaN HEMT Some interesting features of III-nitride system: Wide bandgap High 2-DEG charge density High electron mobility High breakdown voltage Excellent thermal conductivity High power density per mm of gate periphery GaN HEMTs are able to operate in high frequency, high power as well as high temperature device applications 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 37

38 High Power Switching applications Small terminal capacitances Less reverse recovery charge Power loss is low [X. Huang, et al., IEEE TPEL, 29 (5), 2453 (2014)] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 38

39 GaN HEMT Structure Ti/Al/Ti/Au Source 2DEG Pt/Au Gate G AlGaN AlGaN Spacer Layer (UID) GaN Ti/Al/Ti/Au Drain Graded AlGaN to GaN Substrate 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 39

materials create piezoelectric and spontaneous polarization effects

40 AlGaN/GaN Hetero-structure The AlGaN/GaN hetero-structure is used to take advantage of the two dimensional electron gas (2-DEG) AlGaN/GaN materials create piezoelectric and spontaneous polarization effects using an un-doped hetero-interface 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 40

41 Field Plates Distribution of EE EE cccccccccccccccc Field Plated Structure CC gggg and CC dddd 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 41 [H Huang, et al., IEEE TPEL, 29 (5), 2164 (2014)] [W. Saito et al., IEEE TED, 50 (12), 2528 (2003)]

42 Modeling GaN! Modeling Strategy Existing Models 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 42

Challenging to use for multiple device dimensions [I. Angelov et al.

43 Modeling Continued Angelov model Angelov Model Deficiencies Emperical model with ~ 90 parameters Fails to capture non-linear behaviour and harmonic accuracy in power circuits Challenging to use for multiple device dimensions [I. Angelov et al., IEEE T-MTT, 44 (10), 1664 (1996)] [I. Angelov et al., IEEE T-MTT, 40 (12), 2258 (1992)] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 43

44 Status of Compact Model GaN HEMT Table-Based Compact Model GaN-HEMT Empirical Physics Based Five years of rigorous evaluation Threshold- Voltage Based Surface- Potential Based Advanced SPICE Model for GaN HEMT device CMC candidate models for industry standardization (Two models selected as industry standard) ASM-GaN model: Our Model (Y. S. Chauhan, IITK & S. Khandelwal, MQ) MIT MVSG model: MIT, Prof. D. Antoniadis 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 44

45 Advantages of SP-Based Model Better Model Scalability Device Insight Better Statistical Behavior Accurate Charges and Capacitances Better Temperature Scalability Less number of parameters Easier parameter extraction Uses a single expression for all regions Inherent Model Symmetry 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 45

46 ASM-HEMT Model Overview Analytical Solution of Schrӧdiger s & Poisson s 2-DEG Charge Fermi-level (Ef), Surface-potential (SP) SP-Based I d I g & ChargeModel Real Device effects included Accurate I-V and C-V Physical parameters DIBL, Rs, VS,... Noise Model, Trapping Effects Model, Self-Heating DC, AC, Transient Harmonic Simulations, Noise etc. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 46

Core Model & Parameters Real Device Effects Incorporated into the Model Core Model Parameters Parameter Description Extracted Value VV OOOOOO Cutoff Voltage 2.

47 Core Model & Parameters Real Device Effects Incorporated into the Model Core Model Parameters Parameter Description Extracted Value VV OOOOOO Cutoff Voltage 2.86 VV NN FFFFFFFFFFFF Subthreshold Slope Factor CC DDDDDDDD SS Degradation Factor VV 1 ηη 0 DIBL Parameter UU 0 Low Field Mobility mmmm 2 /VVVV NN SS0FFFFFFDD AR 2DEG Density 1.9ee + 17 /mm 2 VV SSSSSSSSSSSSSS AR saturation velocity 157.6ee + 3 cccc/ss RR TTTT0 Thermal Resistance 22 Ω Core drain current expression Self-Heating Effect Access Resistance Model 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 47

48 Model Parameter Extraction Parameter Extraction in ICCAP Software Set L, W, NF, Tbar Device Dimensions Obtain LAMBDA, Improve VSAT, ETA from IDVD Obtain VOFF, NF, CDSCD, ETA from log-idvg, LINEAR And Saturation Temperature Parameters Obtain U0, UA, UB and RDS from IDVG-LIN Capacitance Modeling Obtain VSAT, Improve ETA From LINEAR IDVG Model Implemented in Verilog-A Simulations performed in: ADS, Spectre, HSPICE 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 48

49 DC-Parameter Extraction II dd VV gg (Extract VV OOOOOO, NN FFFFFFFFFFFF, CC DDDDDDDD ) II dd VV gg (Extract UU 0 ) II dd VV dd (Extract NN SSSSSSSSSSS ) [1] S. A. Ahsan et al., MOS-AK Workshop, Shanghai, [2016] II 07/12/2018 dd VV dd (Extract VV SSSSSSSSSSSSSS ) Yogesh S. Chauhan, IIT Kanpur II dd VV dd (Extract RR TTTTT ) 49

50 Nonlinear source/drain access region resistance model Fig.: Nonlinear variation of source/ drain access resistances with Ids extracted from TCAD simulation and comparison with model. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 50

R d/s Model Validation with Measurement Effect of high

in g m -V g : self-heating governs the first slope

51 R d/s Model Validation with Measurement Effect of high access region resistance at high V g Different slopes in g m -V g : self-heating governs the first slope while velocity saturation in access region affects second slope. Fig.: (a) Ids-Vds, (b) g ds and (c) reverse Ids-Vds fitting with experimental data. The non-linear R s/d model shows correct behavior for the higher Vg curves in the Id - Vd plot. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 51

Modeling of Temperature dependence 2-DEG

52 Modeling of Temperature dependence 2-DEG charge density in the drain or source side access region: R d/s increases significantly with increase in temperature. Saturation Velocity: Electron Mobility: 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 52

53 Modeling of Field-Plates in HEMTs Affects capacitance and breakdown behavior. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 53

54 VV DDDDDD Current Collapse VV GGGGGG Source: Stephen Sque - ESSDERC tutorial Sept /12/2018 Yogesh S. Chauhan, IIT Kanpur 54

55 Trap Model Pulsed-IV Scheme used to simulate the P-IV Characteristics in IC-CAP Pulsed IV chacteristics for multiple quiescent conditions Pulse Width 200 ns, Duty-cycle 0.02 % 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 55

56 DC I-V Results from Toshiba Power GaN Transistor 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 56

57 Room Temperature Id-Vd Plots Id-Vd Forward Reverse g ds -Vd g ds`-vd g ds -Vd g ds`-vd 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 57

58 Room Temperature Id-Vg Plots Linear Scale Id (A) g m (ma/v) g m (ma/v 2 ) Id (A) Log Scale 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 58

59 / / / / Other temperatures deg C Rev T=150 C -0 Rev T=-20 C Id (A) id (m/s) [E-3] id (m/s) [E+0] vd [E+0] vd [E+0] vd [E+0] id (m/s) [LOG] id (m/s) [LOG] vd [E+0] vd [E+0] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 59

60 Temperature Scaling Vd = 0.1, 0.5, 1 and 10V Id (ma) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 60

Cascadable Transformation Compatibility with simulation

61 RF Measurements S-Parameters Easy for high frequencies (hard to do open/short for Z/Y) Calculate other quantities Cascadable Transformation Compatibility with simulation tools VNA Architecture 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 61

RF Model & Extraction (i) Model Core surface potential based PDK Access region resistances included in core Bus-inductances in extrinsics gg GMF LL xxxx gg ii dd ii ss ii dddd PDK LL xxxx DMF CC

62 RF Model & Extraction (i) Model Core surface potential based PDK Access region resistances included in core Bus-inductances in extrinsics gg GMF LL xxxx gg ii dd ii ss ii dddd PDK LL xxxx DMF CC GGGGGG dd Device Layout Overlap LL xxxx gg ii RR gg CC gggg,ii RR dd dd ii Extrinsic Manifolds SMF CC GGGGGG CC gggg,ii CC dddd,ii CC DDDDDD gg mm gg dddd ss RR ss ASM-GaN-HEMT 07/12/2018 Yogesh S. Chauhan, IIT Kanpur ss ii 63 Pad-level Small Signal Equivalent Circuit Model

RF Parameter Extraction (ii) Extract CC GGDDOO

Chauhan, IIT Kanpur 66 [1] Q. Fan et al., Proc.

63 RF Parameter Extraction (ii) Extract CC GGDDOO gg mm dispersion handled by trap model CC GGDDOO CC GGGGGG CC DDDDDD 510 ffff 165 ffff 182 ffff Extract CC GGDDOO 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 66 [1] Q. Fan et al., Proc. IEEE, 98 (7), [2010] gg dddd dispersion handled by trap model

RF Parameter Extraction (iii) SS 11 & SS 22

to interaction of inductances with intrinsic

64 RF Parameter Extraction (iii) SS 11 & SS 22 (5V) SS 12 & SS 21 (5V) Resonant peaks due to interaction of inductances with intrinsic capacitances LL xxxx LL xxxx LL xxxx 10.1 pppp 6.08 pppp 8.25 pppp SS 11 & SS 22 (20V) SS 12 & SS 21 (20V) 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 67 [1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]

65 Power Amplifier Design Goals PP dddd PP dddddddd GGGGGGGG = PP oooooo PP iiii PPPPPP = PP oooooo PP iiii PP dddd DDDDDDDDDD PPffffGGccGGeeGGccEE = PP oooooo PP dddd 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 68

66 Load Pull Technique Helps us: Determine Optimum load impedance for maximum Pout and PAE performance Matching networks Understand tradeoffs! [M. S. Hashmi et. al, IEEE Instrum. Meas. Mag., 16 (2), Feb., (2013)] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 69

67 Large-Signal Model Validation ADS Schematic for simulation of load-pull contours 22 dbm 10 GHz Pout & PAE load pull contours for 10 ma/mm Pout & PAE load pull contours for 100 ma/mm 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 70 [1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]

68 Validation Real & Imag Loads Pout & PAE against load resistance (real load) Pout & PAE against load reactance (imaginary load) Fairly accurate in predicting the maxima for Pout & PAE [1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep. [2017] 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 71

69 Validation Drive-up (HB) Time domain waveforms of drain voltage & current. Load line contours spanning the IV plane Frequency 10 ma/mm 100 ma/mm ff jjjj jjjj.35 MMaaaa. PPPPPP ff jjjj jjjj.44 Harmonic balance drive-up characteristics showing Pout, PAE & Gain ff jjj jjjj.83 ff jjjj jjjj.83 MMaaaa. PP OOOOOO ff jjjj jjjj.72 07/12/2018 Yogesh S. Chauhan, IIT Kanpur ff jjjj jjjj [1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]

70 Statistical Simulation using Model The need for a statistical simulations Variation in device performance Obtain a production-level yield-oriented optimized circuit design P out PAE Model Element Description WW Width LL Length LL SSSS,DDDD TT BBBBBB Parameter List Access region length AlGaN Barrier Thickness Sensitivity Analysis for Output power & PAE across key parameters VV OOOOOO UU 0 NN FFFFFFFFFFFF ηη 0 NN SS0FFFFFFDD/DD VV SSSSSSSSSSSSSS/DD RR TTTT0 RR TTTTTTTT CC GGGG0 CC GGGG0 CC DDDD0 Cutoff Voltage Low Field Mobility Subthreshold Slope Factor DIBL Parameter AR 2DEG Density AR saturation velocity Thermal Resistance Trap Resistance Gate-Source Overlap Cap. Gate-Drain Overlap Cap. Drain-Source Overlap Cap. 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 73 RC Circuit used for Trap Modeling

Monte Carlo Simulation Monte Carlo Controller Number of trials = 250

TTTTTTTT Mean & standard deviation values used for Monte Carlo

Distribution of parameter values to carry out statistical simulation

71 Monte Carlo Simulation Monte Carlo Controller Number of trials = 250 Parameters included in simulation VV OOOOOO, CC GGDDOO, CC GGGGGG & RR TTTTTTTT Mean & standard deviation values used for Monte Carlo Simulation VV OOOOOO RR TTTTTTTT Parameter μμ σσ % VV OOOOOO 2.86 VV 1 RR TTTTTTTT 2.4 Ω 2 CC GGGG0 610 ffff 2 CC GGGG0 225 ffff 2 CC GGGGG CC GGDD0 Distribution of parameter values to carry out statistical simulation using Monte Carlo 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 74 [1] S. A. Ahsan et al., Proc. IEEE Int. Conf. Emerging Electronics (ICEE), Mumbai, Dec. [2016]

72 Statistical Simulation Results Measured Model Measured Model 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 75 Pout, Gain & PAE & Idd for 250 trials of MC & measured data for a batch of 10 devices

73 Summary Physics: Physics-based fully analytical model for the GaN HEMTs Accuracy: Excellent agreement with the measured W and L Flexibility: Model is implemented in the Verilog-A code Will be soon available in major commercial simulators For industry: ASM-GaN has been selected as industry standard model at Si2-CMC 07/12/2018 Yogesh S. Chauhan, IIT Kanpur 76

74 Related Journal Publications 1. S. A. Ahsan, A. Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "A New Small-signal Parameter Extraction Technique for large gateperiphery GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 10, Oct S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Multi-bias RF Large-Signal GaN HEMT Modeling and Parameter Extraction Flow", IEEE Journal of the Electron Devices Society, Vol. 5, Issue 5, Sept S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Pole-Zero Approach to Analyze and Model the Kink in Gain-Frequency Plot of GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 3, Mar S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Cross-Coupling and Substrate Capacitance in GaN HEMTs for Power-Electronic Applications", IEEE Transactions on Electron Devices (Special Issue), Vol. 64, Issue 3, Mar A. Dasgupta and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise in HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 26, Issue 6, June S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron Devices, Vol. 63, Issue 2, Feb A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, June S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Compact Modeling of Flicker Noise in HEMTs", IEEE Journal of Electron Devices Society, Vol. 2, Issue 6, Nov S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface- Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct /12/2018 Yogesh S. Chauhan, IIT Kanpur 77

75 Related Conference Publications 1. S. Khandelwal, S. Ghosh, S. A. Ahsan and Y. S. Chauhan, "Dependence of GaN HEMT AM/AM and AM/PM Non-Linearity on AlGaN Barrier Layer Thickness", IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, Malaysia, Nov S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Surface-potential-based Gate-periphery-scalable Small-signal Model for GaN HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), Miami, USA, Oct S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Statistical Simulation for GaN HEMT Large Signal RF performance using a Physics-based Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference (IMaRC), Delhi, India, Dec S. A. Ahsan, S. Ghosh, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for Gallium Nitride High Electron Mobility Transistors", International Conference of Young Researchers on Advanced Materials (ICYRAM), Bangalore, India, Dec S. Ghosh, S. A. Ahsan, S. Khandelwal and Y. S. Chauhan, "Modeling of Source/Drain Access Resistances and their Temperature Dependence in GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Modeling of Kink-Effect in RF Behaviour of GaN HEMTs using ASM-HEMT Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug R. Nune, A. Anurag, S. Anand and Y. S. Chauhan, "Comparative Analysis of Power Density in Si MOSFET and GaN HEMT based Flyback Converters", IEEE International Conference on Compatibility and Power Electronics, Bydgoszcz, Poland, June S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. Agnihotri, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Gate Field Plate on DC, C-V, and Transient Characteristics of Gallium Nitride HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, T. A. Fjeldly and C. Hu, "Surface-Potential-Based RF Large Signal Model for Gallium Nitride HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), New Orleans, USA, Oct S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June (Invited) 20. A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State 07/12/2018 Circuits (EDSSC), Singapore, June Yogesh S. Chauhan, IIT Kanpur S. Ghosh, K. Sharma, S. Khandelwal, S. Agnihotri, T. A. Fjeldly, F. M. Yigletu, B. Iniguez, and Y. S. Chauhan, "Modeling of Temperature Effects in a Surface-Potential Based ASM-HEMT model", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec

76 Acknowledgements Nanolab Past Students: S. Aamir Ahsan (NYU) Chandan Yadav (Bordeaux) Avirup Dasgupta (UCB) Funding Sources: Collaborators: UCB, MQ, IITK DST, SERB, CSIR, ISRO DST-Nanomission SRC-USA, IBM, UCB Device Characterization Lab DC IV, CV, Pulsed and RF Characterization Publications: Books 1* 1 Journal 20* Conference /12/2018 Yogesh S. Chauhan, IIT Kanpur 79

ASM GaN HEMT: Advanced SPICE Model for GaN HEMTs

ASM GaN HEMT: Advanced SPICE Model for GaN HEMTs Sourabh Khandelwal, T. A. Fjeldly, B. Iniguez, Y. S. Chauhan, S. Ghosh, A. Dasgupta MOS-AK 2014 Sourabh Khandelwal MOS-AK 2014 1 Outline ASM-HEMT Model