Test Station for the LHCb Muon Front-End Boards (November 2005)

Transcription

1 005 IEEE Nuclear Sciece Symposium Coferece Record N Test Statio for the LHCb Muo Frot-Ed Boards (November 005) L.Alessadrelli, V.Bocci, G.Chiodi, F.Iacoageli, R.Nobrega, D.Pici, W.Rialdi INFN - Sezioe di Roma - Italy Abstract - The INFN LHCb group i Rome has developed ad implemeted hardware ad software of a fixture to test LHCb Muo Frot-Ed (FE) circuitry for MWPC ad GEM chambers. Frot-Ed boards are made up of two Amplifyig, Shapig ad Discrimiatig (ASD) ASICs ad a read-out ad cotrol ASIC, all of which accessible via a IC based data trasfer protocol. The resultig testig statio allows bech tests of frot-ed readout circuitry usig the same facilities which will be available for their supervisio, as well as a 16-chael charge ijector, a custom read-out board, ad a Wi API C++ program (to cotrol ad aalyze data) developed especially for this purpose. The outcome is a user friedly system which will be widely utilized i the course of chambers ad readout electroics tests, ad durig the istallatio phase of the experimet. The mai relevat aspects of quality assurace are: data trasfer, board coectivity, sesitivity, offset ad oise. A Time to Digital covertig compoet has also bee implemeted i order to evaluate the output sigals timig respose of the Device Uder Test (DUT). A brief summary of prelimiary results obtaied durig its developmet ad implemetatio is also featured. Idex Terms - Frot-ed, charge ijectio, quality cotrol, coverter, automatio, readout, calibratio. I. INTRODUCTION HCB Muo chambers ad their read-out electroics have etered productio phase this year. All subsystems ad Lparts should be thoroughly tested at differet locatios before becomig part of the LHCb apparatus; some of the istitutes which will use ad test those chambers ad circuits are: CERN (Geeva), LNF (Frascati, Italy) ad INFN (Cagliari, Italy). Test equipmet [1] thought for this purpose aims at achievig the highest test coverage at the lowest cost, ad should be easy to replicate, to trasport ad operate. Moreover, data acquisitio should be simple ad reliable; it ca be performed via a USB coectio or with fial supervisory ad cotrol equipmet of the Muo LHCb System, already i use at several istitutes. For a fuctioal test of fully-fitted FEBs which will evetually be part of the LHCb Muo System [], as may as 7 differet procedures have bee evaluated for both their digital ad aalog characteristics. The parameters to be cosidered are: o-board compoet coectivity, circuit oise, sesitivity, offset ad timig. A. Frot-Ed Uder Test The LHCb Muo FE Board is called CARDIAC [3] (CARioca DIAlog Circuit); it is composed of ASD chips (CARIOCA) ad a third chip (DIALOG) with features for diagostics, timig adjustmet ad logic. Two versios of CARDIAC have bee desiged, i order to be able to operate also with Triple-GEM chambers. Muo Chambers CARIOCA 8 chaels LVDS DIALOG 16 chaels CARIOCA 8 chaels Fig. 1. CARDIAC schematic diagram 8 chaels Cotrol System Readout System CARIOCA [4] (Cer Ad RIO Curret-mode Amplifier) is a IBM 0.5μm CMOS ASIC developed for data readout of the LHCb Muo Detector. Such a ASIC holds 8 idetical curret-mode ASDB (Amplifier, Shaper Discrimiator, Baselie restorer) chaels with idividual threshold iputs. CARIOCA has bee developed to process MWPC cathode ad aode sigals (positive ad egative polarities) ad to accept sigals from Triple-GEM detectors as well. CARIOCA has a peakig time of about 10s, durig which the pulse iput charge accumulated is coverted ito a voltage sigal. Therefore the test statio ijectio pulse should be completed before CARIOCAs peakig time. DIALOG [5] is a ASIC developed with the same IBM process as CARIOCA, ad its mai task is to geerate logical chaels from physical chaels received from ADS s, carryig out a adjustmet i time ad width of physical chaels, ad performig calibratio of all ASD s lies. DIALOG performs calibratio usig a DAC with icremets small eough to permit accurate eough oise measuremets eve with a equivalet iput capacitace of 0pF. II. TESTS A. Digital Digital tests are based o read ad write routies to evaluate bit-by-bit respose ad o auto-ijectio procedures i order to test the FEB facilities themselves ad their iteral couters /05/$ IEEE 701 Authorized licesed use limited to: CERN. Dowloaded o Jauary 13, 010 at 18:16 from IEEE Xplore. Restrictios apply.

2 B. Aalog 1) Coectivity Board coectivity is tested by meas of ijectio of a charge pulse, havig previously adjusted the threshold to a certai value. I this way the etire path from FEB iputs to their outputs is put uder test. Such a procedure allows easy ad quick idetificatio of failures i assembled boards ad therefore it should be executed at the begiig of the aalog part of each testig sequece. ) Equivalet Noise Charge Due to the presece of oise, for each charge ijectio the amplifier has a certai statistic distributio. The probability desity fuctio describig the amplifier respose i the presece of Gaussia oise ca be expressed by the formula: 1 V V i Ne (1) f ( V ) give a discrimiator threshold Vth, the probability that a iput charge Qi (which is equivalet to Vi) results i a discrimiator hit is give by: P V th Ne 1 V V i dv () efficiecy 1,0 0,8 0,6 0,4 0, Fig.. S- curve example 0, The plot show i Figure is obtaied applyig the Leveberg-Marquardt algorithm to experimetal data ad thereafter performig a width computatio of a s-curve, accordig to equatio 4. 3) Sesitivity Measuremets of CARIOCA sesitivity ca be made by meas of a threshold sca with differet ijected charges i the rage betwee approximately ad 15fC. I this way several s-curves are produced ad a Volts per Coulomb sesitivity is obtaied. Vth Such a equatio ca be represeted i terms of the error fuctio: P 1 It ca be demostrated that: 1 V th V erf i (3) 5% 75% Vth Vth (4) 1.35 Takig ito accout the above cosideratios it ca be cocluded that a efficiecy of 50% gives the ijected charge equivalet threshold (true threshold). I actual practice, the efficiecy curve is obtaied varyig the threshold while a fixed charge is ijected. Acquired data ca the be fitted ad a oise rms figure is obtaied i Volts. This value ca be subsequetly coverted ito Coulombs oce chael sesitivity is kow. 1000mV 900mV 800mV Fig. 3. Sample sesitivity plot 4) Bias Bias ca be determied i two ways: extrapolatig the sesitivity curve ad by meas of a oise aalysis (without ijectio). The latter allows bias idetificatio by measurig a maximum oise rate durig a threshold sca procedure. The CARIOCA discrimiator makes use of a Differetial Threshold Voltage (DTV) circuit (8 replicas i total). It ca provide a differetial threshold (VrefA - VrefB) from a sigle polarity referece voltage (Vref). 70 Authorized licesed use limited to: CERN. Dowloaded o Jauary 13, 010 at 18:16 from IEEE Xplore. Restrictios apply.

3 A. System Overview III. SYSTEM The mai buildig blocks of test equipmet are a charge ijector, a read-out ad coutig device, a Time to Digital Coverter (TDC-GPX from ACAM) custom circuit, either a CANbus iterface or a USB adaptor ad a itegrated C++ program. Fig. 4. Differetial Threshold Voltage (DTV) Assumig DTV usage for the CARIOCA discrimiator oe ca expect a mirrored oise rate behavior accordig to threshold variatios as show i Figure 5. This oise measuremet procedure has bee implemeted to provide ad accumulate data for further aalysis Iverse Polarity Zero-Threshold Normal Polarity Frot Ed Electroics Board uder test Cotrol Board Ijector Board USB C++ Cotrol Program Noise Rate (100ms gate) Threshold (DIALOG register) Noise rate for 0pF Noise rate for 100pF Fig. 5. CARIOCA threshold sca ad oise rate usig DIALOG chip. The curret Test Statio uses such a measuremet to determie FE circuit bias. 5) Pulse Width ad Time Walk A TDC with 81ps of resolutio has bee implemeted i the Cotrol Board circuitry. This system circuitry receives the strobe sigal from the ijectio logic ad all the FE output chaels. Such a scheme permits measuremet of width ad time-walk of idividual output sigals. Ijectio INPUT INPUT OUTPUT Time-walk start Fig. 6. TDC timig measuremet diagram stop stop TDC OUTPUT Time Width Fig. 7. FEB Test Statio Schematic diagram B. Electroics The Ijectio Board (IB) cotais 16 chaels ad its circuitry permits a fie tuig of ijected charge (i the rage of a few fc) ad of ASD threshold values, sice CARIOCA has 8 idividual threshold iputs. It ca also mask out ay chose group of chaels, adjust the ijectio rate ad fially iject either positive or egative charge as required. A Cotrol Board receives differetial sigals from the CARDIAC uder test ad processes data by meas of 8 couters (all sychroized with IB sigals); all the logic fuctios, as well as the TDC fuctioality, are implemeted o a ACTEL ProAsicPlus FPGA. Data trasfer with a host computer takes place via either a CANbus adaptor or a USB iterface. Sigals from FEBs are collected by the TDC ad features such as time-walk ad pulse width are measured by compariso. TDC techical mai specificatios are: a resolutio of 81ps, capability to work with either risig or fallig edges, 5.5s pulse pair resolutio with a multi-hit feature. All FPGA iteral registers are accessed by a IC iterface, allowig fie tuig of the ijected charge as well as a selectio of chaels to iject ad of course supervisio of the FEB ASICS through the same mechaism. Prior to testig each device, the etire system has to be calibrated, as it is meat to be used for automated testig: for this purpose a auto-calibratio procedure has also bee implemeted, performig calibratio of ijectio lies usig a kow good (KG) FEB. System iputs are bias ad sesitivity characteristics of sigle chaels of a KG FEB, which the costitute the coversio values applied to each ijectio lie. 703 Authorized licesed use limited to: CERN. Dowloaded o Jauary 13, 010 at 18:16 from IEEE Xplore. Restrictios apply.

4 C. Software A C++ based WiAPI program has bee developed to cotrol ad to process data, carryig out tests, data aalysis ad archivig. Prelimiary testig stages are: access to FEB registers ad a auto-ijectio procedure. Oce a basic degree of fuctioality is certai, the software tool ca proceed further to help ivestigate, as show i Figure 8, several aspects of the device uder test: Coectivity, Noise, Sesitivity ad Offset. agai usig calibratio data gaied i the first ru 145 more times. Such a method is good to appraise the itrisic statio error (calibrated sesitivity: 15mV/fC ad offset 800mV). bars = stadard deviatio Set Parameters Registers Access PROCEED TO NEXT DEVICE Auto Ijectio Coectivity Bias w/o ijectio Noise Sesitivity Bias Time-Walk Pulse Width Data Data Archivig Data Archivig Archivig Results Results & Results Fig. 8. A flow chart-like view of the testig process Fially a proper data acquisitio based o the TDC is performed, to measure time-walk ad pulse width. Test results of every device are stored i order to allow further aalysis, keepig a track of each device i a results database, which will be utilized i due course by the ECS for moitorig purposes. Fig. 9. User Iterface of the Test Suite To shorte test duratio the suite rus i parallel, o four chaels at a time. IV. RESULTS A iitial ru of tests was performed, with the aim of assessig system robustess, basic operatio ad a selfcalibratio procedure. Usig a FEB, the apparatus was successfully calibrated ad the the same board was checked Fig. 10. Sesitivity ad Offset histograms 704 Authorized licesed use limited to: CERN. Dowloaded o Jauary 13, 010 at 18:16 from IEEE Xplore. Restrictios apply.

5 Testig of 50 FEB for Triple-GEM detector, i the LHCb Muo Collaboratio, has already bee performed ad results are preseted here. 10% of the total amout has bee foud defective due to short-circuit, commuicatio failures or chip coectivity. The remaiig 90% (70 FE chaels) has bee completed tested as show by the followig histograms. V. CONCLUSIONS A self cotaied test apparatus ad a testig methodology for LHCb Muo Frot-Ed electroics have bee developed. Results obtaied so far have proved to be very accurate ad useful i determiig faults of FEBs so that more replicas of the fixture are beig itegrated ad will be used for systematic productio tests of a proportio of FEBs ACKNOWLEDGMENTS The authors are deeply idebted to, ad would like to thak for their cotiuous ad ivaluable help ad support Silvao Di Marco, Atoio Rossi, Daiele Ruggeri. REFERENCES [1] R. Nobrega, "FEET - Sistema de Caracterizaçao e Teste.da Eletroica de Aquisiçao de Sial de Detectores de.muos MWPC do LHCb", Master Thesis, CBPF, October 003 [] LHCb Techical Proposal, CERN/LHCC "Status of the LHCb Detector Reoptimizatio", CERN/LHCC [3] W. Boiveto, "Desig ad performace of the frot-ed electroics of the LHCb Muo Detector", LECC, Heidelberg, Germay [4] D. Moraes, W. Boiveto, N. Pelloux, W. Riegler, The CARIOCA Frot Ed Chip for the LHCb muo chambers, LHCb ; Geeva : CERN [5] S. Cadeddu, V. De Leo, C. Deplao ad A. Lai, DIALOG, a ASIC for timig of the LHCb muo detector, Nuclear Istrumets ad Methods i Physics Research A 518 (004), 486 Fig. 11. A summary of the most recet test results 705 Authorized licesed use limited to: CERN. Dowloaded o Jauary 13, 010 at 18:16 from IEEE Xplore. Restrictios apply.