Green Product. S amhop Microelectronics Corp. July Ver 1.2 D1/D 2 S 2 G 2 ID 10 IDM P D. W Operating Junction and Storage Temperature R ange

Transcription

1 Green Product S amhop Microelectronics Corp. July.. 6 Ver. Dual N-C hannel E nhancement Mode F ield E ffect T ransistor P R ODUC T S UMMAR Y V DS S ID R DS (ON) ( mω ) VGS = 4.V V A VGS =.V FEATURES S uper high dense cell design for low R DS (ON). R ugged and reliable. S urface Mount Package. ESD Protected. TSSOP D D D/D S S G D/D S S G G G (TOP VIE W) S S ABS OLUTE MAXIMUM R ATINGS (T A= C unles s otherwis e noted) Parameter Symbol Limit Unit Drain-S ource Voltage V DS V Gate-Source Voltage V GS V a Drain C urrent-c T J= C b -P ulsed ID IDM 4 A A Drain-S ource Diode Forward Current a IS.7 A Maximum P ower Dissipation a P D. W Operating Junction and Storage Temperature R ange T J, TSTG - to C THE R MAL CHAR ACTE R IS TICS a Thermal Resistance, Junction-to-Ambient R JA 8 C /W

2 ELECTRICAL CHARACTERISTICS (TA = C unless otherwise noted) C Parameter Symbol Condition Min Typ Max Unit OFF CHARACTERISTICS Drain-S ource B reakdown Voltage BVDS S V GS = V, ID = ua V Zero Gate Voltage Drain Current IDS S V DS = 6V, VGS = V ua Gate-Body Leakage IGSS V GS = V,VDS = V ua ON CHAR ACTE R IS TICS b Gate Threshold Voltage V GS(th) V DS = V GS, ID = ua..8. V Drain-S ource On-S tate R esistance c R DS (ON) Forward Transconductance gfs V DS = V, ID = A c DYNAMIC CHARACTERISTICS Input C apacitance Output C apacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate C harge Gate-Source Charge Gate-Drain Charge C IS S C OSS C RSS td(on) tr td(off) tf Q g Q gs Q gd V GS = 4V, ID = A. V DS =8V, V GS = V f =.MH Z V DD = V, ID = A, V GEN = 4V, R L = ohm R GEN = ohm V DS =V, ID = A, V GS =4V m ohm V GS =.V, ID = A. 8 m ohm S PF PF PF ns ns ns ns nc nc nc

3 E LE CTR ICAL CHAR ACTE R IS TICS (T A= C unles s otherwis e noted) C Parameter Symbol C ondition Min Typ Max Unit DR AIN-S OUR CE DIODE CHAR ACTE R IS TICS Diode Forward Voltage V SD V GS = V, Is =.7A.7. V Notes a.surface Mounted on FR4 Board, t sec. b.pulse Test:Pulse Width s, Duty Cycle %. c.guaranteed by design, not subject to production testing. b VGS=4V - C ID, Drain C urrent (A) V GS=.V V GS=.V ID, Drain C urrent (A) 9 6 C C VDS, Drain-to-S ource Voltage (V) Figure. Output Characteristics VGS, Gate-to-Source Voltage (V) Figure. Transfer Characteristics 4. R DS (on) (m Ω) V GS=.V V GS=4V R DS (ON), On-R esistance Normalized V G S =4V ID=A V GS=.V ID=A ID, Drain C urrent (A) Figure. On-R esistance vs. Drain Current and Gate Voltage 7 Tj( C) Tj, Junction Temperature ( C) F igure 4. On-R es is tance Variation with Drain Current and Temperature

4 V th, Normalized G ate-s ource T hreshold Voltage V DS=V GS ID=uA BVDS S, Normalized Drain-S ource B reakdown Voltage. ID=uA T j, J unction T emperature ( C ) Tj, Junction Temperature ( C) F igure. G ate T hreshold Variation with T emperature Figure 6. Breakdown Voltage Variation with T emperature R DS (on) (m Ω) 7 C C C ID=A Is, S ource-drain current (A).. C 7 C C V GS, Gate-Source Voltage (V) F igure 7. On-R es is tance vs. G ate-s ource Voltage V SD, B ody Diode F orward Voltage (V) F igure 8. B ody Diode F orward Voltage Variation with S ource C urrent 4

5 6 C, C apacitance (pf ) Coss Ciss V GS, G ate to S ource Voltage (V) 4 V DS=V ID=A Crss V DS, Drain-to S ource Voltage (V) Figure 9. Capacitance Qg, Total Gate Charge (nc) F igure. G ate C harge 6 S witching T ime (ns ) 6 TD(off) Tr Tf TD (on) VDS =V,ID=A VGS= 4 V ID, Drain C urrent (A) ms ms. V GS=V Single Pulse T A= C.. DC s Rg,GateResistance(Ω ) F igure.s witching characteris tics V DS, Drain-S ource Voltage (V) F igure. Maximum S afe Operating Area

6 V DD VGS R GEN V IN G D R L V OUT td(on) V OUT ton toff tr td(off) 9% 9% % INVE R TE D % tf S VIN % 9% % % PULSE WIDTH F igure. S witching T es t C ircuit F igure 4. S witching Waveforms r(t),normalized E ffective Transient Thermal Impedance.. Duty Cycle=... P DM. t t.. R thj A (t)=r (t) * R thja. R thja=s ee Datasheet. T JM-TA = P DM* R thja (t) S ingle Pulse 4. Duty Cycle, D=t/t S quare Wave Pulse Duration (sec) F igure. Normalized T hermal T ransient Impedance C urve 6

7 PACKAGE OUTLINE DIMENSIONS TSSOP Notes:. This drawing is for general information only. Refer to JEDEC Drawing MO-,Variation AA,for proper dimensions, tolerances,datums,etc.. Dimension D does not include mold Flash,protrusions or gate burrs. Mold Flash,protrusions and gate burrs shall not exceed. mm (.6 in) per side.. Dimension E does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed.mm (. in) per side. 4. Dimension b does not include Dambar protrusion.allowable Dambar protrusion shall be.8 mm total in excess of the b dimension at maximum material condition.dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is.7 mm.. Dimension D and E to be determined at Datum Plane H. 7

8 TSSOP-8 Tape and Reel Data TSSOP-8 Carrier Tape UNIT : PACKAGE A B K D D E E E P P P T TSSOP TSSOP-8 Reel UNIT : TAPE SIZE REEL SIZE M N W W H K S G R V