STU/D15L01. N-Channel Logic Level Enhancement Mode Field Effect Transistor
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1 Green Product STU/D5L SamHop Microelectronics C orp. N-Channel Logic Level Enhancement Mode Field Effect Transistor PRODUCT SUMMRY VDSS ID RDS(ON) (mω) Max VGS=V V 5 VGS=4.5V FETURES Super high dense cell design for low RDS(ON). Rugged and reliable. TO-252 and TO-25 Package. Halogen free. G S STU SERIES TO - 252(D- PK ) G D S STD SERIES TO - 25( I - PK ) BSOLUTE MXIMUM RTINGS (T =25 C unless otherwise noted) Symbol V DS V GS I D I DM E S P D T J, T STG Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous -Pulsed c a c Single Pulse valanche Energy d Maximum Power Dissipation Operating Junction and Storage Temperature Range a T C =25 C T C =7 C T C =25 C T C =7 C Limit Units V ±2 V mj 5 W 32 W -55 to 5 C THERML CHRCTERISTICS R JC a Thermal Resistance, Junction-to-Case 3.6 C/W R J a Thermal Resistance, Junction-to-mbient 5 C/W Details are subject to change without notice.
2 STU/D5L ELECTRICL CHRCTERISTICS (T=25 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHRCTERISTICS BVDSS Drain-Source Breakdown Voltage VGS=V, ID=25u V IDSS Zero Gate Voltage Drain Current VDS=8V, VGS=V u IGSS Gate-Body Leakage Current VGS= ±2V, VDS=V ± n ON CHRCTERISTICS VGS(th) RDS(ON) g FS Gate Threshold Voltage Drain-Source On-State Resistance Forward Transconductance VDS=VGS, ID=25u VGS=V, ID=6 VGS=4.5V, ID=5 VDS=V, ID= V 45 m ohm 5 95 m ohm 5 S b DYNMIC CHRCTERISTICS CISS Input Capacitance 48 pf VDS=25V,VGS=V COSS Output Capacitance 47 pf f=.mhz CRSS Reverse Transfer Capacitance 29 pf SWITCHING CHRCTERISTICS td(on) Turn-On Delay Time tr Rise Time td(off) tf Fall Time Qg Qgs Qgd Turn-Off Delay Time Total Gate Charge Gate-Source Charge Gate-Drain Charge b VDD=5V ID= VGS=V RGEN= 6 ohm VDS=5V,ID=6,VGS=V VDS=5V,ID=6, VGS=V ns ns ns ns nc nc nc DRIN-SOURCE DIODE CHRCTERISTICS ND MXIMUM RTINGS VSD Diode Forward Voltage VGS=V,IS= V Notes a.surface Mounted on FR4 Board of inch 2, oz. b.guaranteed by design, not subject to production testing. c.drain current limited by maximum junction temperature. d.starting TJ=25 C,L=.5mH,VDD = 5V.(See Figure3) 2
3 STU/D5L 5 VGS=V ID, Drain Current() VGS=8V VGS=7V VGS=6V VGS=5V ID, Drain Current() C Tj=25 C -55 C VDS, Drain-to-Source Voltage(V) Figure. Output Characteristics VGS, Gate-to-Source Voltage(V) Figure 2. Transfer Characteristics RDS(on)(m Ω) V GS=V RDS(on), On-Resistance Normalized V GS=V ID= Tj( C ) ID, Drain Current() Tj, Junction Temperature( C ) Figure 3. On-Resistance vs. Drain Current and Gate Voltage Figure 4. On-Resistance Variation with Drain Current and Temperature Vth, Normalized Gate-Source Threshold Voltage V DS=V GS ID=25u 25 5 BVDSS, Normalized Drain-Source Breakdown Voltage ID=25u Tj, Junction Temperature( C ) Tj, Junction Temperature( C ) Figure 5. Gate Threshold Variation with Temperature Figure 6. Breakdown Voltage Variation with Temperature 3
4 STU/D5L RDS(on)(m Ω) C ID=6 25 C 25 C Is, Source-drain current() C 25 C 25 C VGS, Gate-to-Source Voltage(V) Figure 7. On-Resistance vs. Gate-Source Voltage VSD, Body Diode Forward Voltage(V) Figure 8. Body Diode Forward Voltage Variation with Source Current C, Capacitance(pF) 9 75 Ciss Coss 5 Crss VGS, Gate to Source Voltage(V) VDS=5V ID= VDS, Drain-to-Source Voltage(V) Qg, Total Gate Charge(nC) Figure 9. Capacitance Figure. Gate Charge 3 8 Switching Time(ns) TD(on) VDS=5V,ID= VGS=V Rg, Gate Resistance(Ω) Tr Tf TD(off ) ID, Drain Current() R DS (ON) Limit VGS=V Single Pulse T=25 C.. VDS, Drain-Source Voltage(V) DC ms ms us Figure. switching characteristics Figure 2. Maximum Safe Operating rea 4
5 STU/D5L tp V(BR )DSS V DS L R G 2V tp D.U.T IS. + - V DD IS Unclamped Inductive Test Circuit Figure 3a. Unclamped Inductive Waveforms Figure 3b. 2 D=.5 Normalized Transient Thermal Resistance R J (t)=r (t) * R J 2. R J=S ee Datas heet SINGLE PULSE 3. T JM-T =PDM* R J (t) 4. Duty Cycle, D=t/t P DM t t2 Square Wave Pulse Duration(sec) Figure 4. Normalized Thermal Transient Impedance Curve 5
6 STU/D5L TO-252 E b3 E L3 D D H 2 3 L4 b e b2 L2 c L L c2 DETIL "" SYMBOLS b b2 b3 c c2 D D e E E H L L L2 L3 L4 MILLIMETERS MIN MX BSC REF.58 BSC DETIL "" 6
7 STU/D5L PCKGE OUTLINE DIMENSIONS TO-25 E b3 c2 D E D H 2 3 b2 L4 L5 b L e b4 c SYMBOL MILLIMETERS MIN MX E L L4.698 REF L D H b b b b e BSC c.4.6 c2 D E
8 STU/D5L TO-25 Tube TO-25 Tube/TO-252 Tape and Reel Data ~ " " TO-252 Carrier Tape P T D P2 E B E2 K D P FEED DIRECTION UNIT: PCKGE TO-252 (6 B K D D E E E2 P P P2 T TO-252 Reel T M N E S G K V R H W UNIT: TPE SIZE 6 REEL SIZE 33 M N W T H K S G R V
9 STU/D5L TOP MRKING DEFINITION TO-252 SamHop Logo STU5L XXXXXX Product No. SMC internal code No. (,B,C...Z) Wafer Lot No. Production Date (,2 ~ 9,,B...) Production Month (,2 ~ 9,,B,C) Production Year (29 = 9, 2 =...) 9
10 STU/D5L TOP MRKING DEFINITION TO-25 SamHop Logo STD5L XXXXXX Product No. SMC internal code No. (,B,C...Z) Wafer Lot No. Production Date (,2 ~ 9,,B...) Production Month (,2 ~ 9,,B,C) Production Year (29 = 9, 2 =...)
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DESCRIPTION The SPN80T06 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. This high density process is especially
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DESCRIPTION The SPN166T06 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. This high density process is especially
More informationSymbol Parameter TSB20N60S TSP20N60S TSF20N60S Unit 20* 20* I D -Continuous (TC = 100 ) 12*
TSP20N60S,TSF20N60S, TSB20N60S 600V N-Channel MOSFET Description SJ-FET is new generation of high voltage MOSFET family that is utilizing an advanced charge balance mechanism for outstanding low on-resistance
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PD-90712C POWER MOSFET THRU-HOLE (TO-254) IRFM360 400V, N-CHNNEL HEXFET MOSFET TECHNOLOGY Product Summary Part Number RDS(on) ID IRFM360 0.20 Ω 23 HEXFET MOSFET technology is the key to International Rectifier
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DESCRIPTION The SPN8206 is the logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize
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DESCRIPTION The SPN166T04 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. This high density process is especially
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DESCRIPTION The SPN9971 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. The SPN9971 has been designed specifically to
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DESCRIPTION The SPN6338 is the Dual N-Channel enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored
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V P-Channel Enhancement-Mode MOSFET VDS= -V RDS(ON), Vgs@-.5V, Ids@-.A = mω RDS(ON), Vgs@-.5V, Ids@-.A = 15 mω Features Advanced trench process technology High Density Cell Design For Ultra Low On-Resistance
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PD - 9472 HEXFET POWER MOSFET SURFACE MOUNT (SMD-.5) IRL7NJ382 2V, N-CHANNEL Product Summary Part Number BVDSS RDS(on) ID IRL7NJ382 2V.85 22A* Seventh Generation HEXFET power MOSFETs from International
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DESCRIPTION The SPN6435 is the Dual N-Channel enhancement mode field effect transistors are produced using high cell density DMOS technology. These products have been designed to minimize on-state resistance
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DESCRIPTION The SPN7002 is the N-Channel enhancement mode field effect transistors are produced using high cell density DMOS technology. These products have been designed to minimize on-state resistance
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DESCRIPTION APPLICATIONS The SPN70T10 is the N-Channel logic enhancement DC/DC Converter mode power field effect transistor which is produced Load Switch using high cell density DMOS trench technology.
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