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1 N-Channel Enhancement Mode Power MOSFET Description The uses advanced trench technology and design to provide excellent DS(ON) with low gate charge. It can be used in a wide variety of applications. General Features V DS = 100V,I D =30A DS(ON) < V GS =10V (Typ:24 mω) Schematic diagram Special process technology for high ESD capability High density cell design for ultra low dson Fully characterized avalanche voltage and current Good stability and uniformity with high E AS Excellent package for good heat dissipation Application Power switching application Hard switched and high frequency circuits Uninterruptible power supply Marking and pin assignment TO-220-3L top view Package Marking and Ordering Information Device Marking Device Device Package eel Size Tape width Quantity TO-220-3L Absolute Maximum atings (T C =25 unless otherwise noted) Symbol Parameter Limit Unit VDS Drain-Source Voltage 100 V VGS Gate-Source Voltage ±20 V I D Drain Current-Continuous 30 A I D (100 ) Drain Current-Continuous(TC=100 ) 21 A I DM Pulsed Drain Current 70 A P D Maximum Power Dissipation 75 W Derating factor 0.5 W/ E AS Single pulse avalanche energy (Note 5) 256 mj T J,T STG Operating Junction and Storage Temperature ange -55 To Page 1/ 6
2 Thermal Characteristic θjc Thermal esistance, Junction-to-Case (Note 2) 2.0 /W Electrical Characteristics (T C =25 unless otherwise noted) Off Characteristics Symbol Parameter Condition Min Typ Max Unit BV DSS Drain-Source Breakdown Voltage V GS =0V I D =250μA V I DSS Zero Gate Voltage Drain Current V DS =100V,V GS =0V μa I GSS Gate-Body Leakage Current V GS =±20V,V DS =0V - - ±100 na (Note 3) On Characteristics V GS(th) Gate Threshold Voltage V DS =V GS,I D =250μA V DS(ON) Drain-Source On-State esistance V GS =10V, I D =15A mω g FS Forward Transconductance V DS =5V,I D =10A S Dynamic Characteristics (Note4) C lss Input Capacitance PF V DS =25V,V GS =0V, C oss Output Capacitance PF F=1.0MHz everse Transfer Capacitance PF C rss (Note 4) Switching Characteristics t d(on) Turn-on Delay Time ns t r Turn-on ise Time V DD =50V, L =5Ω ns t d(off) Turn-Off Delay Time V GS =10V, GEN =3Ω ns Turn-Off Fall Time ns t f Q g Total Gate Charge V DS =50V,I D =18A, nc Q gs Gate-Source Charge V GS =10V nc Gate-Drain Charge nc Q gd Drain-Source Diode Characteristics V SD Diode Forward Voltage (Note 3) V GS =0V,I S =20A V I S Diode Forward Current (Note 2) A t rr everse ecovery Time TJ = 25 C, IF = 18A ns Qrr everse ecovery Charge di/dt = 100A/μs (Note3) nc t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: 1. epetitive ating: Pulse width limited by maximum junction temperature. 2. Surface Mounted on F4 Board, t 10 sec. 3. Pulse Test: Pulse Width 300μs, Duty Cycle 2%. 4. Guaranteed by design, not subject to production 5. EAS Condition : Tj=25,V DD =50V,V G =10V,L=0.5mH,g=25Ω, I AS =32A Page 2/ 6
3 Test Circuit 1) E AS Test Circuit 2) Gate Charge Test Circuit 3) Switch Time Test Circuit Page 3/ 6
4 Typical Electrical and Thermal Characteristics (Curves) dson On-esistance(mΩ) ID- Drain Current (A) ID- Drain Current (A) Vds Drain-Source Voltage (V) Figure 1 Output Characteristics Vgs Gate-Source Voltage (V) Figure 2 Transfer Characteristics Normalized On-esistance Vgs Gate-Source Voltage (V) Is- everse Drain Current (A) T J -Junction Temperature( ) Figure 4 dson-junctiontemperature Qg Gate Charge (nc) Figure 5 Gate Charge I D - Drain Current (A) Figure 3 dson- Drain Current Vsd Source-Drain Voltage (V) Figure 6 Source- Drain Diode Forward Page 4/ 6
5 Vds Drain-Source Voltage (V) Figure 7 Capacitance vs Vds T J -Junction Temperature ( ) Figure 9 Power De-rating ID- Drain Current (A) C Capacitance (pf) Vds Drain-Source Voltage (V) Figure 8 Safe Operation Area T J -Junction Temperature( ) Figure 10ID Current- Junction Temperature r(t),normalized Effective Transient Thermal Impedance ID Current (A) Power Dissipation (W) Square Wave Pluse Duration(sec) Figure 11 Normalized Maximum Transient Thermal Impedance Page 5/ 6
6 TO-220-3L Package Information Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A A b b c c D E E e TYP TYP. e F H h L L V EF EF. Φ Page 6/ 6
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General Description These N-Channel enhancement mode power field effect transistors are using trench DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,
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Main Product Characteristics V DSS R DS(on) I D 650V 0.32Ω (typ.) 11A TO-220F Marking and Pin S c h e m a ti c Dia g r a m Assignment Features and Benefits High dv/dt and avalanche capabilities 100% avalanche
More informationDevice Marking Device Device Package Reel Size Tape width Quantity. HM4622A HM4622A SOP-8 Ø330mm 12mm 2500 units
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RoHS Compliant Product A suffix of -C specifies halogen & lead-free DESCRIPTION The is the highest performance trench N-ch and P-ch MOSFETs with extreme high cell density, which provide excellent R DSON
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