Wafer Level System Integration. Oswin Ehrmann

Transcription

1 Wafer Level System Integration Oswin Ehrmann Fraunhofer Institut for Reliability and Microintegration IZM D Berlin Germany Gustav-Meyer-Allee 25 Outline Introduction Wafer Bumping and Flip Chip Bonding for ATLAS Future Options and Requirements: Bump size and Pitch Lead Free Bumping Thin Silicon Integration of Passives 3D Integration

2

3 Fraunhofer in profile 59 institutes employees (full-time equivalence 1000 million Euro bugdet Fraunhofer Institut for Reliability and Microintegration IZM Fraunhofer Institut Zuverlässigkeit und Mikrointegration 250 Scientists and Engineers (+100 Students)/ Cleanroom 800 m 2 Applied Research and Development of Advanced Packaging Solutions for Microelectronics Branch Labs and Centers in Chemnitz, Teltow, Paderborn, Oberpfaffenhofen and Munich Worldwide Technology Transfer and Consulting Services

4 Front End Back End Electronic Packaging Front End Wafer

5 Packaging Roadmap 2000 till TB-BGA LC-TB-BGA stacked modules MC-BGA VSI stacked CSP FC-MCM chip in polymer S-CSP Polytronic ULC-CSP Flex-Sys WLP thin silicon COF/FCOB CSP PGA BGA QFP SQFP MCM COB FC CCC VSO 1997 SO SOJ TFP VTFP V-PAK stacked chips DIP Chip on Board Si-Chip Substrat Si-Chip Substrat

6

7 Si-Chip Flip Chip Bump Si-Chip Si-Chip Substrat Si-Chip Substrat

8 ECD Bumping at IZM Gold SnAg AuSn Cu - CuSn PbSn Processflow PbSn-Bumping using Electroplating Sputter Etching and Sputtering of the Plating Base / UBM Spin Coating and Printing of Photoresist Electroplating of Cu and PbSn Resist Stripping and wet Etching of the Plating Base Reflow

9 Sputter Etching Sputtering of Plating Base / UMB Photolithographie

10 Electroplating Construction Scheme of the Electrolytic Cell of a Rack Plater A: Anode G B: Spray Tubes C C: Shielding D: Wafer E: Overflow A B D E F: Immersion Heater G: Level Switch F

11 Electroplating Equipment Semitool Equinox ATLAS Detektor Large Hadron Collider (CERN) Length: 50 m Diameter: 25 m Weight: 7000 t

12 ATLAS Pixel Detector Module Thin-Film-Multichipmodul Size 22 x 64 mm² Silicon Sensor 16 Readout ICs (KGD) IO-Bumps pitch 50 µm, electroplated SnPb Fundamental Construction of Bumps on ATLAS Detector Chips 25 µm electroplated PbSn63 5 µm electroplated Cu as solderable base 300 nm sputtered Cu as plating base 200 nm sputtered Ti:W as adhesion layer and diffusion barrier Al chip pad with overlapped passivation 12 µm 20 µm 26 µm 20 µm as plated after reflow

13 4 High Density ECD Bumping & Flip Chip IBM 0.25 µm rad tolerant design Bumps / chip size / pitch : 30 µm / 50 µm 98 Readout Chipwafer ATLAS FE-I3 CMOS IC 200 mm Si-Wafer, CMOS 0.25µ Technology 288 tested Chips per Wafer Chip Size: 7,4 x 11 mm² EIectroplated I/O Bumps: ~ Bumps per Wafer, Ø 25µm Plating Base: UBM: Solder: Ti:W/Cu Cu Sn60Pb40

14 Bumped FE-I Chip IBM 0.25 µm rad tolerant design Chip with 9 column pairs Defect Classes Small Bump Large Bump Particle Bump Position Missing Bump

15 IC Technology Roadmap: Chip Interconnect Pitch Chip Interconnect Pitch [µm] ATLAS Year area array peripheral Source: ITRS ATLAS Si-Sensor Substrate Wafer 520 Processed Sensor Wafer: 100 mm Silicon Wafer Double side processed Thickness 250 µm 3 sensor tiles with pixel cells 50 x 400(600) µm² Electroplated Sensor Pixel Contacts : Pixelmetallization Al Plating Base Ti:W/Cu Pad 5 µm Cu + 1µm Ni + Au

16 Bare Module Flip Chip Assembly readout chips, sensor tiles: test, inspection, classification flux deposition pick and place: FC150 of SüssMicrotech, Pick & Place Accuracy 3µm reflow: at 250 C, reductive atmosphere inspection and measurements: x-ray inspection, electric module test rework: single die exchange of misplaced die, to many bridged bumps, die that failed electrical test Assembly of ATLAS Pixel Detector Modules 16 ROC Flip-Chip Bonded to the Sensor electroplated SnPb IO-Bumps, Ø 25 µm, pitch 50 µm Assembly of 1139 ATLAS Modules Assembled Chips: ~ chips Module Yield incl. rework: 97 % Chip Rework Rate: 0.7 % Chip Yield after Bumping: processed Readout Chips 98% der Module mit <10 Bumpdefekten Class 1: perfect chips Class 2: accepted defects (< 4 defective bumps, small particle,...) Calss 3: rejected chips (> 4 defective bumps, scratches, residues, plating defects,...)

17 ATLAS Pixel Detector at LHC at CERN Bare Module 22 x 64 mm² PIXEL Detector Ø 0.9m ATLAS Detector Ø 25m Inner Detector Ø 2m ATLAS Pixel Detector at LHC at CERN

18 ATLAS Pixel Detector at LHC at CERN

19 Detector Placquettes for CMS 1 x 1 2 x 3 1 x 3

20 Future Requirements: Bump size and Pitch Solder Bumping PbSn37/63 Diameter: 10 µm Pitch: 20 µm Future Requirements: Lead Free Solder for Melting FC Interconnects Point SnBi 42/ C PbSn 37/ C SnZn 91/9 199 C SnAg 96.5/ C SnCu 99.3/ C AuSn 80/ C PbSn 95/5 314 C

21 Lead Free Bumping SnAg Meeting the requirements of future environmentally friendly lead-free flip chip interconnects basing on the EU-directive ROHS 2000 Bump dimensions Size: µm Pitch: down to 50 µm Ag composition: 3.0 ~ 4.0 at.% Melting point: 221 C Lead Free Bumping SnAg

22 GaAs X-ray Pixel Detector Frontend Readout Chip MEDIPIX 256x256 IOs Pixel cell size 55 x 55 µm² Chip size 14 x 14 mm² SnAg Bumps Ø25 µm, more than bumps/wafer GaAs Sensor Chip GaAs Detector 256x256 pixels Pixel size 55 x 55 µm² Chip size 16 x 16 mm² Electroplated Cu-Pad, height 5 µm project partners: MPD, Fine Tech, FhG-IZFP, FhG-IZM funded by: EFRE and the Free State of Saxony GaAs Hybrid Pixeldetector: X-Ray Test Pixeldetector assembled on MEDIPIX board and tested at FhG-IZFP x-ray images of a spring and a screw using the 202x202 pixel detector prototyp (photography by FhG-IZFP) project partners: MPD, Fine Tech, FhG-IZFP, FhG-IZM funded by: EFRE and the Free State of Saxony

23 AuSn Bumping for RF- Devices - AuSn Bumps on GaAs typ size diameter: 40 µm Hight: µm ζ-phase ep. Au sp. Au Ti:W(N) Chip Pad Pass. AuSn Electroplated Bumps 50 µm pitch full array 30 µm AuSn20 x-ray pixel detector

24 Cu Pillar Bumps (Height: 80 µm, Diameter: 60 µm) Process Flow - Stencil Printing Al bond pad Ni UBM Solder paste Cleaned solder bump Reflowed solder bump Source:

25 Electroless Ni + Solder Printing Solder Bumping by Stencil Printing 150 µm pitch 500 µm pitch Waferbumping by C4NP

26 Waferbumping by C4NP

27 Waferbumping by C4NP Waferbumping by C4NP Bumping of thinned wafers Bumping of wafers with vias (stacking) Solder with 3 or more components Fine Pitch Bumping

28 Elastic Contact Structures ELASTec Source: Infineon ClawConnect made of StressedMetall : J-shaped planar microspring Source: NanoNexus, Xerox Co., PARC Source: Georgia Tech Nano - structured Bump surface

29 Future Requirements: Integration of Passive Components Build up for the realization of all three passive types Thin Film Build Up for the Realization of Passives Future Requirements: Integration of Passive Components thinfilm resistors thinfilm inductors R = 1kΩ R = 5kΩ

30 Future Requirements: Thin Silicon Thinning of bumped wafers: 180 µm

31 Future Requirements: Thin Silicon Silicon becommes flexible when thickness is reduced down to less than 30µm bending radius 1mm / 1µm thickness fully flexible and ultra thin systems available best opportunities to proceed with FC and CSP technologies basis for 3D chip integration Dicing by Thinning Rounded chip corners Dry Etching of about 30µm deep groves Backside Grinding - Etching - CMP nearly ideal chip edges (rounded corners are possible) shorter process times for singulation into individual chips narrow cuts save silicon area for small chips non rectangular dies are possible non-rectangular dies

32 Wafer Level 3D Integration Technologies Stacking Technologies: Die-Stacking Pyramid Stack Same Size Stack with Spacer

33 Stacking Technologies: Die-Stacking Chip-in-Polymer Die-Stack Through Silicon Via Die-Stack Stacking Technologies: Wafer-Stacking Yield!!!

34 Through Silicon Vias: Basic Questions Pre Front End Process Post Front End Process New Front End Process Restrictions in Process Parameters Design Restrictions Through Silicon Vias: Basic Questions Wafer Front Side Processing - Wafer Back Side Processing

35 Wafer-Level-Packaging for Optical Applications Tapered Vias & Streets controlled sidewall angle for sribe line controlled sidewall angle for via holes Ball Grid Array on the backside with Silicon Via Contacts

36 Wafer-Level-Packaging for Optical Applications Through Silicon Vias TSV Formation and Metallization Deep Via High Aspect Ratio Etching (h >20 µm 80 µm) Side Wall Insulation Via Filling by Cu-CVD/ Via Filling by Cu-Electroplating Via Filling by W - CVD

37 Through Silicon Vias: Si Etching Si Trench Etch 2.5 x 20 µm² How Deep is the Via? Through Silicon Vias: Via Filling W- Fill of High Aspect Ratio Trench ICV-Dimensions: 3 µm x 10 µm x 50 µm 300 nm SACVD TEOS 20 nm TiN CVD 900 nm W CVD und W Backetch 800 nm M1 (AlSiCu, structured) 850 nm PN/POX (Passiviation)

38 Through Silicon Vias: Via Filling Deep Inter-Chip Vias AR 20:1 W-Fill and Etch Back 23,4 µm W (via-fill) SACVD Oxide Through Silicon Vias: Via Filling Copper CVD

39

40 Process flow Fabrication of inter-chip vias with standard wafer process sequence Simultaneous formation of electrical and mechanical connection Fabrication of Tungsten or Copper filled InterChip Vias on Top Substrate Via Opening and Metallization Thinning (20µm) Opening of Plugs Electroplating CMOS Top Wafer prior to Thinning 10x2,5 µm ICVs TEOS M2-AlSiCu SACVD planarized ILD TEOS Therm. Oxide O3/TEOS Spacer MOCVD-TiN/W ICVs 10 x 2,5 µm, 20 µm deep, AR 8:1 Distance between W-filled ICVs and Transistors: ~ 4 µm to Source/Drain Area ~ 11 µm to Gate Area

41 Process flow Simultaneous formation of electrical and mechanical connection Alignment and Soldering to the Bottom Wafer

42 Process flow Alignment and Soldering of additional Top Chips - Thin SLID layers with large area contacts - Modular concept - Suitable for chip-to-wafer stacking Integration densities up to 10 5 cm -2 Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM) Dept. High Density Interconnect & Wafer Level Packaging Gustav-Meyer-Allee 25, Berlin Tel.: +49 (0) , Fax: -123 Forschungsschwerpunkt Technologien der Mikroperipherik, TIB Sekr. 4/2-1 Gustav-Meyer-Allee 25, Berlin Tel.: +49 (0) , Fax: