Electronic Packaging Technologies from Bump Bonding to 3D Integration

Transcription

1 Electronic Packaging Technologies from Bump Bonding to 3D Integration Fraunhofer Institute for Reliability and Microintegration (IZM) Gustav-Meyer-Allee Berlin Germany Dipl.-Ing. Thomas Fritzsch Contact: 1

2 Electronic Packaging Wikipedia.de Telephone - Johann Philipp Reis 1861 Packaging has four major functions: Mechanical Connection Electrical Connection (Signal and Power distribution) Heat dissipation Protection (mechanical, chemical, electromagnetic) Goal: Provide reliable interconnects and reliable systems for a specific application and under various conditions (temperature, moisture, vibration, radiation, dust) Driving forces: Miniaturisation Functionallity Reliability Cost Smartphone 2013 David Hodson/ Packaging Level: Packaging at component level Packaging at sub-assembly level Packaging at system level 2

3 Electronic Packaging Component-/ Wafer Level Bumping and Interconnects Redistribution Layer Hermetic Caping / Sealing Flip Chip Bonding 3D Chip Stacking System - / Product Level Wire and Connector Assembly Sub-Assembly Integration Housing PCB-/ Sub-Assembly Level Wire Bonding Soldering Encapsulation / Molding Flip Chip / SMD Assembly Reliability Temperature Cycle Test Humidity Storage Vibration / Drop Test Power Cyling 3

4 Outline Fraunhofer IZM The Electronic Packaging Institute Wafer Level Packaging Micro Bumping Technology Bump Bonding and Interconnection Technologies for Hybrid Pixel Radiation Detectors 3D Integration Technologies and Applications 4

5 Overview Fraunhofer Gesellschaft 69 institutes 24,500 employees app. 2.1 billion turnover More than 70% contract research Information Technology Light & Surfaces Life Sciences Microelectronics Production Defense & Security Materials & Components 5

6 Fraunhofer Institute For Reliability and Microintegration - IZM Figures Mio. turnover 85 % contract research 367 employees (235 full time, 132 students, PhD, trainee) Locations Berlin Dresden University Cooperation Long-term contract with Technical University of Berlin Research Center Microperipheric Technologies Approx. 90 additional staff Joint use of equipment, facilities and infrastructure Director Prof. K.-D. Lang Material characterization Process evaluation Reliability testing Failure analysis Sample production Training courses 6

7 Fraunhofer IZM Bringing Microelectronics into Application ASIC, components Design Wafer Level Packaging Printed Circuit Board Level Packaging Product Level Final Product 7

8 Outline Fraunhofer IZM The Electronic Packaging Institute Wafer Level Packaging Micro Bumping Technology Bump Bonding and Interconnection Technologies for Hybrid Pixel Radiation Detectors 3D Integration Technologies and Applications 8

9 Wafer Fabrication and Wafer Level Packaging (WLP) Frontend - Wafer Fabrication Backend - Wafer Level Packaging Adaption of ASICs to further assembly steps ZDNet Additional contact layers (bumps, RDL, ) ASIC cross section ASIC fabrication on silicon wafer in submicron technology (180 22nm) Wafer size 150, 200, 300, (450) mm Top pad metal aluminium (AlSi, AlSiCu,Cu) developed for wire bonding Functionally tested ASIC (KGD) Structure size nm Structure size µm Micro-Bumping 25µm size Thin Film Multilayer Redistribution (RDL) 4 20µm width 9

10 Wafer Level Packaging at Fraunhofer IZM Fraunhofer IZM - Berlin Fraunhofer IZM ASSID Dresden ~ 800 m² cleanroom Wafer size: 100, 150, 200, (300)mm 900 m² cleanroom Wafer size: 200, 300mm PVD Sputtering DRIE Si Etch CVD (Oxid / Barrier / Seed) Polymer/ Resist application Lithography Electrochemical deposition and Wet Etch CMP Wafer Bonding and Debonding Chip Bonding D2D, D2W Thinning / Grinding Dicing Automatic Optical Wafer Inspection Metrology 10

11 Wafer Level Packaging: Micro Bumping Process SSEC Sputter Etching and Sputtering of the Plating Base / UBM Spin Coating and Printing of Photoresist Electroplating of Cu of and UBM PbSn and Bump Resist Stripping and wet Etching of the Plating Base 11

12 Physical Vapour Deposition (PVD) Sputtering of Plating Base Seed Layer Resist Lithography Plating Etching Inspection Dicing Metal deposition: TiW, Ti, Cu, Au, Pt, NiCr, Al, AlSi, (barrier + seed layer) Layer thickness: nm Goals: minimum layer stress Diffusion barrier between contact pad and plating base Plating base layer with low resistivity 12

13 Resist Patterning by Mask Lithography Seed Layer Resist Lithography Plating Etching Inspection Dicing Resist deposition by spin-coating, spraycoating or dry film lamination Resist thickness 5µm 100µm UV mask exposure & resist development Goals: Accurate wafer-mask alignment Edge steepness/resist stability Residue free via 13

14 Electrochemical Deposition - Electroplating Seed Layer Resist Lithography Plating Etching Inspection Dicing Metal deposition: Cu, Au, Ni, Sn, SnAg, In, Au/Ag Layer thickness: 2 100µm Goals: Minimum layer stress Homogenious layer thickness Defect free deposition G Rack Plater C A: Anode B: Spray Tubes A B D E C: Shielding D: Wafer E: Overflow F F: Immersion Heater G: Level Switch 14

15 Wet Etching Process Seed Layer Resist Lithography Plating Etching Inspection Dicing Removal of resist layer by solvent solution Removal of seed- and barrier layer by wet etching Residueless removal of resist and plating base Differential etch of TiW, Ti, Cu, Au, Cr Tools: Manual and automated wet etch processes available Manual single wafer load and automated wafer handling process (C2C) SSEC 15

16 Wafer Inspection Surface, 2D/3D Metrology Seed Layer Resist Lithography Plating Etching Inspection Dicing Only electrically good tested chips without bump defects are used for further assembly Rudolph Technologies Surface & bump inspection deformed bump merged bump missing bump 2D bump metrology by image processing 3D bump metrology by laser triangulation 16 16

17 Wafer Dicing Seed Layer Resist Lithography Plating Etching Inspection Dicing Dicing Process: Mounting on dicing tape Dicing (saw, laser) Detaping and sorting Dicing Technologies: Saw Dicing Laser Dicing: Full-Cut Stealth Dicing Dicing by Grinding Plasma Dicing Source Microworld Source DISCO Source DISCO 17

18 Flip Chip Assembly Chip 2 Chip Chip 2 Wafer Chip with function A i.e. ASIC Chip with function B i.e. sensor, MEMS Flip Chip Assembly with Bonding Tools: High Accuracy Chip Pick and Place Process Interconnection by temperature and pressure: reflow soldering, thermo-compression bonding, thermosonic bonding 18

19 High Accuracy Flip Chip Assembly Bonder Tools SET FC150 Panasonic FCB3 set-na.com panasonicfa.com Semi automatic flip chip bonder Accuracy ± 3 Sigma Bonding force up to 500N C2C bonding Substrate size up to 50 x 50 mm² Capable for Adhesive-, TC- and Thermode Bonding Full automatic flip chip bonder Accuracy ± 3 Sigma Bonding force up to 490N C2C, C2W bonding Substrate size up to 12 wafer size Capable for Adhesive-, TC- and TS Bonding 19

20 X-ray Inspection Process: X-ray scanning of module Alignment between sensor and ROC Missing / Bridged Bumps Particles / residues No open bump connections detectable! source: Xray source Device Under Test Misaligned chip particles Missing bumps/ Bridged bumps Xray detector screen 20

21 Outline Fraunhofer IZM The Electronic Packaging Institute Wafer Level Packaging Micro Bumping Technology Bump Bonding and Interconnection Technologies for Hybrid Pixel Radiation Detectors 3D Integration Technologies and Applications 21

22 Hybrid Pixel Detectors Setup: Back Side Electrode Pixel Sensor Chip Readout Chip Flip Chip Interconnection Sensor Pixel Communication, Data processing particle / photon Function: Sensor chip Readout chip 22

23 Hybrid Pixel Detectors Requirements Readout Chip Radiation hardness High readout speed Low noise electronic Low power consumption Short connections to the sensor Sensor Radiation hardness High detection efficiency Fast signal response High spectral and spatial resolution Large detector array Advantages: Separate development and optimization of sensor and readout chip Variable use of different semiconductor sensor materials 23

24 Packaging of Hybrid Pixel Detectors Flip Chip Bump Bonding Step 1: UBM deposition on sensor wafer Step 2: solder bump deposition on readout chip wafer Step 3: Flip Chip Assembly of readout chip to sensor chip 24

25 Fine Pitch Interconnects Deposition by Electroplating Interconnection Materials and Structures SnAg3.5 Indium/InSn Cu-Sn Pillar Cu Pillar Au Au-Sn Ni-Au/Cu-Ni-Au Cu 25

26 SnAg Solder Bumping on 200mm Readout Chip (ROC) Wafer ATLAS FE-I4 TIMEPIX / MEDIPIX Bump size: 25µm Bump Pitch: 50µm (x, y1), 450µm (y2) Chip Size: ~20 x 20 cm² Bump matrix: 80 x 336 (26880 per chip) Number of bumps: >1.6 Mio. (200mm) Application: Research Bump size: 25 30µm Bump Pitch: 55µm (x, y) Chip Size: ~14 x 16 cm² Bump matrix: 256x257 (65792 per chip) Number of bumps: >7 Mio. (200mm) Application: Research, Industry 26

27 Hybrid Pixel Detectors for Particel Tracking and Xray Imaging Particle Tracking: CERN X-ray Imaging for Synchrotrons CERN Courtesy of MEDIPIX Collaboration Röntgenbeugung CERN Hybrid pixel detector modules are the main building blocks of the inner tracking detector Hybrid pixel detector modules are used for x-ray imaging in photon-counting pixel detectors for synchrotrons and FEL 27

28 CERN ATLAS IBL Pixel Tracking Detector Upgrade ATLAS FE-I4B Modules for ATLAS Insertable B-Layer (IBL) ATLAS FE-I4B double chip modul ATLAS IBL insertion (courtesy of Heinz Pernegger/CERN) ATLAS Pixel Tracking Detector (InSpire/CERN) SnAg Bumping on 200mm Readout chip wafer, min. pitch 50µm Assembly of 168 double and 112 single chip modules for ATLAS IBL Readout Chip size 2x2 cm², module size 4x2 cm² 150µm thin chip ROC assembly 28

29 Silicon Pixel Detector Modules for the CMS Detector - Upgrade at LHC - CERN Upgrade Phase for the new 4 barrel layer CMS Silicon Pixel Detector Fraunhofer IZM processed 316 modules for the 3rd layer (incl. spares) SnAg Bumping of 26x 200mm Readout Chip wafers (6448 ROCs total) Cu-UBM deposition on 130x 100mm sensor wafers Flip Chip Assembly of 16 Readout Chips per module (5056 ROCs total) Total module count: assembly of 316 modules Innermost part: silicon pixel tracking detector New 3rd layer with modules fabricated at IZM CMS detector at LHC / CERN ( CMS/CERN) 29

30 The European X-Ray Free-Electron Laser (XFEL) at DESY Hamburg European XFEL, the largest and most powerful X-ray laser in the world, was officially inaugurated on September 1 st, 2017 The European XFEL produces extremely bright and ultrashort light pulses. The facility will generate up to pulses per second 200 times more than other X-ray lasers. With the help of specialized instruments, these X-rays enable completely new insights into the atomic details and extremely fast processes of the nanoworld. Scientists will use these X-ray flashes to map the threedimensional structure of biomolecules and other biological particles, ( single snapshots of particles produced with the X-ray laser can be sewn together to create molecular movies to study the progress of biochemical and chemical reactions [ 30

31 Pixel-Detector Modules for European X-Ray Free-Electron Laser (XFEL) X-ray Diffractometry: The European X-Ray Free Electron Laser (XFEL) will provide ultra-short, highly coherent X-ray pulses which will revolutionize scientific experiments in a variety of disciplines spanning physics, chemistry, materials science, and biology European XFEL will provide very short x-ray pulses in a high repetition frequency with pulses per second Detection of molecule diffraction pattern with radiation hard X-ray cameras Very fast and high dynamic range readout ASICs necessary because most experiments using particle injection mechanisms Adaptive Gain Integrating Pixel Detector (AGIPD) Modules assembled at Fraunhofer IZM for European XFEL 31

32 Pixel-Detector Modules for European X-Ray Free-Electron Laser (XFEL) Adaptive Gain Integrating Pixel Detector (AGIPD) Modules assembled at Fraunhofer IZM for European XFEL 16-Chip Module with AGIPD Readout ASICS, module size 11x3 cm² 200 x 200 µm² pixel size, pixels per modules 1MPix X-ray camera consist of 16 modules positioned around the beam line center Fabrication of AGIPD modules in cooperation with DESY Functional-Test of AGIPD Detector-Three Module Camera XFEL SPB-beamline with AGIPD Detector (SPB Single particles, Clusters and Biomolecules) A.Allahgholi - CFEL A.Allahgholi - CFEL 32

33 Detectors with high-z Sensors for Hard X-rays GaAs Sensor with Pixel metallization CdTe Sensor with Pixel metallization D. Pennicard. Germanium pixel detector, Materials: Cadmium Telluride Gallium Arsenide Germanium Requirements: Bump Material adapted to GaAs and CdTe pad metallization Maximum process and bonding temperature below 120 C 150 C (CdTe, Ge) Low bonding pressure Indium based solder bumps 33

34 Indium and Indium/Tin for Low Temperature Flip-Chip Interconnections Development of a wafer-level electroplating bumping technique for low-melting Indium solder Indium bump Indium-tin bump T M (Indium) = 156 C; T M (In52Sn48) = 117 C for thermally sensitive bonding processes Electrochemical deposition of Indium or Indium/Tin Flip chip bonding process In to In or In to Au pad surface, bonding temperature below 100 C process also available for InSn-bumps Pulltest: Indium bump on Au-pad UBM In bump with good adhesion on sensor UBM, separation within ductile Indium bump Pulltest: Indium-tin bump on Au-pad UBM Bump UBM pulled from silicon wafer stronger adhesion of InSn-bump to sensor UBM connection 34

35 Germanium X-ray detector using Indium bumping 2015: Ge Sensor HEXA Module 35

36 Germanium X-ray detector using Indium bumping spot of cosmic radiation with Ge HEXA Detector M. Sarajilic, Medipix Meeting, Maastricht

37 Alternative Bonding Techniques for 3D Integration Higher Bonding and Application Temperature Pillar bump bonding Transient Liquid Phase (TLP) Bonding Cu CuSn Metal-Metal Direct Bonding Cu, (Au, Ni) Cu, (Au, Ni) Cu 3 Sn Intermetallics ECD Cu-pillar with solder cap Short reflow process Use of underfiller for higher reliability Use of different solder types for chip stacking ECD Cu and Cu-Sn pads High melting Cu 3 Sn IMC Ts = 700 C Bonding parameters: C, 10 50MPa High planarity necessary ECD Cu pads (Au, Ni) Planarized surfaces, preconditioning Bonding parameters: 300 C 400 C, >100MPa, t= min h, vacuum 37

38 R&D: Nano-Porous Gold Bumps for Chip Interconnections Development electro-plating baths for Ag/Au alloy deposition Prozess flow similar to conventional Au Bumping Skeleton formation due to simple dealloying by wet etching of Ag Average pore sizes adjustable from 20 nm up to 500 nm TC-Bonding with reduced bonding parameters possible, typ. 10 Mpa / 200 C / 300s Sponge-like Au is fully compressible and able to compensate topography and inhomogeneities on chip and substrate 38

39 Outline Fraunhofer IZM The Electronic Packaging Institute Wafer Level Packaging Micro Bumping Technology Bump Bonding and Interconnection Technologies for Hybrid Pixel Radiation Detectors 3D Integration Technologies and Applications 39

40 2.5D/3D Integration Technology TSV Through Silicon Via LETI Filled TSV (2 20µm Ø) for high density through via interconnects Interposer applications High IO ASICs Linered TSV (>20µm Ø) for moderate density through via interconnects Low IO ASIC and sensors 40

41 Basic Technologies for TSV Formation 6. Frontside- /Backside RDL Cu-Electroplating or Al-Sputtering 1. TSV silicon etching DRIE BOSCH Process 5. Si-Thinning / TSV- Reveal Backside DISCO 2. TSV-Insulation TEOS, PE-CVD, SA-CVD, 3. Barrier-/Seed-Layer Ti (TiW, TiN, Ta(N)) / Cu HI-PVD 4. Via filling ECD Cu bottom up filling 41

42 Application: Silicon Interposer for High Bandwidth Module Fabrication of silicon interposers with Cu TSVs and high density RDL at 200 mm Size: 20 x 21,7 mm 2, Thickness: 100 m 42,459 TSVs per Device Cu-TSV density ~10,000/cm² Back: PCB-side (as seen in a mirror) Front: HD-side Interposer IC1 IC2 More than 200 modules delivered by IZM 42

43 3D Packaging of Hybrid Pixel Detectors Larger detector size with minimum dead area between sensors replace wire bond interconnections by TSV and backside connects Four side stitchable module matrix arrangement possible X-Y-Sensor-Matrix sensor ROC with TSVs and backside RDL IO flex interconnection 4x4 sensor matrix and schematical cross section of a 3D pixel detector module 43

44 MEDIPIX3 TSV Development RDL lines and pad metallisation Cu-filled TSV (x-ray left, cross cut right) TSV process from wafer backside UBM on MEDIPIX wafer Bumping of sensor wafer Module hybridization 2nd level assembly of LTCC/PCB substrate 44

45 MEDIPIX3 TSV Module Test on Evaluation Board PCB with TSV module MEDIPIX TSV Module Test Standard PCB technology Size: 64mm x 67mm Terminating resistors and decoupling capacitor on the board Samtec connector 28 pin pairs Bump bonding (BGA) between Mpx3 chip and PCB Imaging with Medipix3RX TSV module: PCB sample imaged with X-ray tube, Mo target, 51 kv and 31 ma, 100 s exposure, flat-field corrected, presented on linear scale where black color is zero counts and white is the maximum (left) Background radiation after 30 min exposure time, white pixels have zero counts and black have one count (right). Milija Sarajli, David Pennicard, Sergej Smoljanin, Thomas Fritzsch, Kai Zoschke, Heinz Graafsma: Progress on TSV technology for Medipix3RX chip ; IWORID 2017, Cracow, July

46 TSV Process for Ultra Fast Xray Pixel Matrix Chip UFXC32k Readout Chip developed by AGH Krakow, Poland Prepared for TSV frontside option Process at IZM: TSV ROC TSV-frontside process Completely-filled Cu-TSV Frontside and backside RDL Fronside Solder Bumps/Pillars Backside solderable Pad Cross section of ROC-Sensor Module, with Cu filled TSV Metallization Hybridization to sensor 2nd level assembly to LTCC ROC backside after TSV and backside RDL process 46

47 TSV Process for Ultra Fast Xray Pixel Matrix Chip The tests of a detector module: measurement of a total power consumption ( MHz) functionality verification of digital blocks in UFXC32k ICs (registers and counters readout), measurements of the effective offset spread from pixel to pixel before and after trimming, test with the charge injection circuit to verify the in-pixel analog front-end operation, test with X-ray radiation of different energy, measurement of example radiograms. Kai Zoschke et al. Fabrication of 3D Hybrid Pixel Detector Modules Based on TSV Processing and Advanced Flip Chip Assembly of Thin Read Out Chips, ECTC 2017, Lake Buena Vista, Florida, May 30 to June 2,

48 Summary Wafer Level Packaging A Micro Integration Technology Adaption of IOs to further chip assembly steps and integration into electronical systems Bumping, RDL, TSV processes, Chip assembly Bump Bonding and Interconnection Technologies SnAg, In solder bump deposition and bump bonding Used for Hybrid Pixel Detector Modules for Particle tracking in High Energy Physics and X-ray imaging for synchrotrons and FEL 3D Integration Technologies and Applications 2.5D and 3D integration technology using TSVs Interposer and active die stacking 3D packaging on R&D level for hybrid pixel detectors available 48

49 Thank You For Your Attention Fraunhofer Institute for Reliability and Microintegration (IZM) Gustav-Meyer-Allee Berlin, Germany Contact: 49