Drucktechnik für das moderne Packaging - Teil 2
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1 Drucktechnik für das moderne Packaging - Teil 2 Dipl.-Ing. Technical University of Berlin (TUB) Gustav-Meyer-Allee 25, Berlin, Germany coskina@izm.fhg.de Fraunhofer Institute for Reliability and Microintegration (IZM) Gustav-Meyer-Allee 25, Berlin, Germany
2 Die 2012: Printing of 40x40 mm² FC 40m m Aco ustom icroscopicalim ageofunderfiled FlipChip,InitialState
3 Stencil Printing: Determination of Process Yield Initial State of Wafer Prior Stencil Printing Reflowed Solder Paste 4 Wafer 500 µm Pitch Pads per Wafer Wet Solder Paste Deposits Created by Stencil Printing (SnPbAg2) average bump height = 207 µm standard deviation = 5 µm failure rate = 10 ppm
4 Flip Chip Technologies soldering UBMs: TiWCu, CrNi, NiAu solders: PbSn, SnAg, AuSn, In substrates: ceramics, FR4, flex adhesive joining bumps: Au, Ni/Au adhesives: isotropic, anisotropic substrates: glass, flex, FR4 thermo-compression bumps: Au substrate: silicon, ceramics
5 Flip Chip Using Adhesives -Methods- Isotropic Conductive Anisotropic Conductive Non-Conductive 1. IC 2. Syringe IC Gold Bump IC Mech. Gold Bump ICA Bondpad ACA NCA Substrate Temperature Underfiller Temperature Substrate Load + Temperature Bondpad Substrate Bondpad Load + Temperature
6 Combination of Flip Chip and SMD
7 Si Chip Flip Chip Using Adhesives -ACA on Flex- cross section of assembly using ACA paste Si Chip Conductor Lines Ni Bump Conducting Particle
8 Problemstellung PBGA CSP mit Zwischenträger CSP mit Umverdrahtung Die Miniaturisierung von neuen Produkten wird bei koplanarem Aufbau durch die Silizium Fläche des IC s bestimmt. Eine weitere Erhöhung der Funktionsdichte kann nur noch durch eine volumetrische Integration erzielt werden. Flip Chip
9 Packaging Roadmap > 2000
10 3D MCM: Stapel Konzept Sensorintegration µc, Memory Kommunikation
11 Smart Products Flexible smart cards Electronic labels Intelligence in paper Throw away electronics Electronic watermark Self supervising documents
12 Flip Chip on Flex Using Anisotropic Conductive Adhesives - Application: Transponder Tag (Airline Bag Tag) - Substrate: Polyester Coil: Aluminum Anisotropic Conductive Adhesive (ACA) Chip Coil Transponder IC on Polyester Flex Courtesy of Texas Instruments Deutschland GmbH
13 Isoplanar Contacting Method Goal: Coil + contacts can be made in one step Conductive Paste RF ID Tag Substrate: - paper - polyester - PVC Thinned Chip Coil: applied by stencil printing or dispensing 20-30µm
14 Isoplanar Contacts of Ultra Thin ICs Benefits of interconnection technology of Ultra Thin IC: Low topography of thinned IC allows isoplanar interconnection, e. g. by screen printing Electronic products become bendable Electronic label is compatible to paper processing (lamination, printing,...) 430 m 20 m Thinned IC com pared to usualic thickness
15 Cross-section of an Isoplanar Contact Electricalinterconnectionis achieved by screen printing ofsilver-filed polym eracrosschipedge 430 m contact pad die attach s ilver-filled polymer IC 20 m 20 m paper s ubs trate
16 Chip In Polymer (CHiP) thin Si chips in HDI layers die attach on core laminate laser drilling of vias electroless contact plating
17 3D-Packages Oberseiten-Routing Landefläche für 3D-Stapel Chip LP-Substrat Unterseiten-Routing (LP Technologie) Lotkugeln LP-Vias (gebohrt) gedünnter IC In FR4 Leiterplatte
18 3D-Package Demonstrator IZM 21 Testchip, 200 µm Pitch, 184 I/Os µm Chipdicke 2-lagiges Leiterplattensubstrat mit Standard-Vias 200 µm Lotkugeln mit 500 µm Pitch 3-fach Stapel, automatisch montierbar 3-fach Stapel auf Leiterplatte montiert
19 Process Flow: Redistribution Using Photolithography & Electroplating Wafer [ w or w/o passivation ] Solder Mask [ 10 µm Photo-BCB ] Polymer Layer [ 5 µm Photo-BCB ] UBM [ Ti:W sp /Cu sp /Ni ep /Au el ] Metallization [ 5 µm Cu ] Bumps [ screen-printing PbSn ] Process Flow Electroless Redistribution Overview of the Redistribution Technology -all steps are on wafer levelelectroless Ni/Au bumping 1st dielectric (vias) surface activation second dielectric (lines) electroless Cu deposition third dielectric (solder mask) solder printing
20 Erfordernisse für zukünftige Prozesse & Technologien Low Cost Geringe Gesamtkosten für den Prozeß Prozeß muß geeignet sein für: High End Produkte & kostengünstige Konsumer Elektronik Hohe Zuverlässigkeit Hohe Flexibilität Umweltfreundlich Technologie geeignet für hochzuverlässige- und hochtemperatur-anwendungen unter extremen Bedingungen Einsatz von Lotlegierungen mit untersch. Schmelzpkt. (unterschiedl.temperaturhierarchien) z.b. geeignet für den Ersatz von Blei (wenn durch den Gesetzgeber verordnet)
21 Stencil Printing Raodmap concerning Packaging Technologies > 2000 Packaging Technologie: Zukünftige Trends Stacked Chips WL-CSP Integrated Passives Low Cost Wafer Bumping ALTERNATIVE LOTE Umwelt- und Gesundheitseinschränkungen Alpha Partikel Emission Semiconductor LC-TB-BGA 3D Packaging Low Cost Redistribution Package 3D CSP SYSTEMINTEGRATION (System on/in Package) 3-D INTEGRATION (3-d Package) Substrate
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