System Integration for High Frequency Applications

Transcription

1 System Integration for High Frequency Applications System Integration for High Frequency Applications J. Wolf, F.J. Schmückle*, W. Heinrich*, M. Töpper**, K. Buschick, A. Owzar**, O. Ehrmann, and H. Reichl Fraunhofer-Institute for Reliability and Microintegration Berlin ** Technische Universität Berlin, Sekr. TIB. 4/2-1 Gustav-Meyer-Allee 25, Berlin, Germany Phone: +49 (0) / Fax: +49 (0) * Ferdinand Braun Institut, Berlin Rudower Chaussee 5, 129 Berlin, Germany Phone: +49 (0) Fax: +49 (0) Abstract Thin film multilayer substrate technology with dielectric polymer layers and sputtered / electroplated wiring provide the highest line density per layer and therefore they are of special interest for MCM applications. A planar integration technology of bare dice embedded in ceramic substrates is used. The components are inserted into premanufactured windows of ceramic substrates and fixed in their position by epoxy. A thin film multilayer structure is realized in a planar fashion on top of the embedded system. The metallization is based on a Ti:W / Cu tie layer, which is subsequently electroplated with Cu. Polyimide Pyralin TM 2722 (Du Pont) and Cyclotene TM (Dow Chemical) are used as interlevel dielectrics. The paper addresses the transmission lines characteristics (MS and CPW) for the chip substrate interconnection. Furthermore, the effect of the meshed ground plane on the line parameter impedance is discussed. The dielectric polymer layers are characterized by the effective permittivity (e r ) and the loss factor (tan d). Key words: MCM-D, Thin Film Technology, Chip First, Impedance Controlled Systems, and HF Application. 1. Introduction Multichip Modules (MCMs) as a group of highly functional electronic devices interconnected to a substrate reduce cost and size and they also provide opportunities to integrate unique functions of chips from various processing technologies into a system. Today, multichip modules present the highest performance in packaging technology. MCMs combine several ICs with a functionally designed substrate which takes full advantage of the IC performance. This complex substrate structure can be realized in different technologies. Thin film multilayer structures on ceramic, silicon, or metal (MCM- D) provide the highest line density per layer. The metallization for the wiring system is deposited by sputtering and electroplating. Polymers with a low dielectric constant (e r < 4) are used as the dielectric materials. In the following, a special MCM technology for high frequency applications is discussed where bare dice are directly embedded into substrate openings or recessed areas (cavities). The interconnection and wiring system is realized using thin film technology on the planar chip/substrate surface. The main advantages of such a configuration are short interconnection lengths between the chip and the substrate, no chip preparation (bumping), planar topography, and high integration density. Additionally, all transmission lines on the substrate and from the substrate to the active or passive components can be realized with a controlled impedance. 2. MCM-D with Embedded Circuits 2.1. Principle There are two main principles which can be used for MCM- D with embedded active or passive components. In the first one, The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 1, First Quarter 1998 (ISSN ) 119

2 Intl. Journal of Microcircuits and Electronic Packaging called chip-first, the chips are mounted into openings in the MCM substrate and the wiring and interconnects are applied by depositing the metallization on top of a first polymer layer which covers the chips as well as the substrate. Via holes are opened in the photosensitive polymer film to contact the embedded chips with the first metallization layer. The metallization is deposited by sputtering and electroplating using a photoresist mask. A second polymer layer with a thickness of 25 µm is deposited and photoprinted. The second metallization layer is deposited and structured in adjustment to the first metal layer 1,2. For the second principle, called chip-last technology, the chips are embedded into the substrate after the realization of the thin film wiring on the substrate. With an additional thin film metallization, the interconnects from the substrate to the embedded chips are realized. Figure 1 shows a schematic cross-section of the chip-first and chip-last constructions. epoxy chip metal 2 (Cu) substrate ceramic Compared to dry-etch materials, photosensitive polymers require fewer processing steps for multilayer metallization. The Photo- Cyclotene TM (Dow Chemical) and the Photo- Pyralin TM 2722 (Du Pont) are therefore the dielectrics of choice for the thin film process at IZM / TUB. In Table 1, the properties of the two polymers are compared 3. Table 1. Properties and processing conditions of the photosensitive polymers used (supplier data). Polymer Cyclotene TM Pyralin TM 2722 Supplier Dow Du Pont Chemical Dielectr. const. ε r at 1kHz Loss factor tan δ at 1kHz Water uptake [%] CTE [ppm/k] T g [ C] > 350 > 400 Cure temp. [ C] 210 for 0.5 h 350 for 2 h chip first metal 1 (Cu) has some advantages due to its moderate curing temperature below 250 C in comparison to the high curing temperature of polyimides in excess of 350 C. After having processed all layers, the films are fully cured for 90 min at 250 C. has a very low degree of shrinkage due to its polymerization reaction (Diels- Alder Cycloaddition) producing no by-products. Film thicknesses of over 25µm are therefore possible to realize in one process step using the batch development system 2 DS The electrical resistance of the vias is in the range of 1 mw for 50 µm vias (mask dimension). Figure 2 shows a cross section of a 50 µm via and Figure 3 presents the electrical resistance of vias in the range from 40 µm to 80 µm diameter. chip last Figure 1. Principles of embedding technology Thin Film Process Dielectrics Polyimides () and Benzocyclobutene () are thin film polymers having a low dielectrical constant in addition to a very high thermal stability (glass transition temperature over 350 C). Figure 2. Via (50µm) in thick Photo- (20 µm) with Cu-metallization (5 µm) 120

3 System Integration for High Frequency Applications R in m Ω Via Diameter Figure 3. Electrical resistance of vias in Photo- (6 wafers). Metallization The thin film metallization is based on a Ti:W/Cu (100nm/200nm) tie layer, which is subsequently electroplated using a photoresist mask (AZ 4562, Kalle-Hoechst).The thickness of the metallization is 5 µm. Figure 4 shows a microstrip structure (Ti:W/Cu / ep-cu) where the polymer is removed with RIE to visualize the planarization of the photo-. A CPW-structure on a ceramic substrate with a layer is shown in Figure 5. Figure 4. SEM of a MS-structure (,Cu); (Polymer etched with RIE). 3. Electrical Characterization of Thin Film Wiring 3.1. Transmission line Types For the interconnections between the different chips and for additional passive elements on the carrier substrate, two line types are of main interest: the microstrip (MS) line and the coplanar waveguide (CPW). Using these structures to connect the chips provides a multichip system with good electrical properties and a high level of reproducibility. The electrical characteristics of the transmission lines are mainly determined by the material properties of the dielectric, the metallization layer, and their dimensions (line width, line space, dielectric thickness). For most applications, it is necessary to realize 50W matching impedance systems. For chip connections on the carrier substrate, the MS line offers the advantage that the electromagnetic field is concentrated in the dielectric between the metallizations. The part of the fields penetrating the ground-metallization layer is attenuated so strongly that the influence of the substrate can be neglected. Thus, the MS transmission properties become independent of the carrier material, which is of interest using low-resistivity silicon for instance. In the case of the CPW structure, on the other hand, the field penetrates into both the dielectric (with a small thickness h) and the substrate. Hence, the electrical properties of the substrate, especially the losses, influence the wave propagation. The connection to the chip is realized either by a direct contact to the pads of the embedded chip or by vias leading through one or two dielectric layers. In order to design connection lines and the transitions between the chip and the carrier substrate properly, one needs to know the electromagnetic characteristics of the transmission line structures for different parameter sets. In the following, corresponding data on both the CPW and the MS structures are presented. The simulations were performed by means of a mode-matching procedure that takes into account losses in both the metallizations and the dielectric material Chip - Substrate Interconnection Figure 5. SEM of a CPW-structure (Cu on ) (gap between signal and ground: 10 µm). In the chip-first approach (TEC 01), the electrical interconnection between the chip and the substrate is realized by the first metallization layer for both, signal and ground (CPW). On chip side, both lines are connected by vias to the chip pads through a thin dielectric layer (, ). The TEC 05 approach (Chip-last) represents the technology where the chip is inserted into the substrate after realization of the substrate wiring. The electrical interconnection is realized as a CPW by a third metal layer. The different structures were investigated with a 3D Finite- Difference code 5 using about 250,000 cells. The structures in Figure 6 are shown, as they were calculated, with a magnetic wall as a symmetry plane in the center of the signal line. The computations The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 1, First Quarter 1998 (ISSN ) 121

4 Intl. Journal of Microcircuits and Electronic Packaging were preformed with a supply MS line on the substrate side and an CPW line on the chip side. In Figure 6, the reflection parameters S 11 of the transmission from substrate to chip for the different technologies are shown as a function of frequency. Due to the present minimum possible gap width in the first run of technologies TEC01 and TEC05, the transmission line over the epoxy gap has an increased characteristic impedance compared to the 50 W supply lines. This leads to reflections larger than -15 db in the frequency range under consideration. variation of ±1 µm in strip width yields a deviation of ±1.8 % of the nominal characteristic impedance. Nevertheless, such deviations are tolerable and meet the practical specifications requirements. Re(Z)/Ohm 63 epoxy gap TEC01 : h2 = 25 µm w(nominal) = 80 µm Chip First : TEC01 Chip First : TEC03 53 substrate GaAs-chip S11 = S22 in db CPW-signal CPW-ground g = 150 µm g = 50 µm g = 100 µm Tra n sitio n MS-signal / Chip Last : TEC delta-w/µm Figure 7. Effects of tolerances in line width w on characteristic impedance of the transmission line elements from substrate to chip for TEC01 with dielectric and at f = 20 GHz. -40 chip adhesive gap substrate MS-ground vias Figure 6. Reflection coefficient of the transmission for different technologies and epoxy adhesive gap widths g. Best performance by TEC05 with a 50 µm coverage of the CPW-bridge. An optimized chip-last structure provides values better than - 20 db for the reflection parameter S 11 even for different epoxy adhesive gap widths g. This should also be valid for structures in technology TEC01, which are presently under investigation. Smaller gap width and wider ground metallizations will be considered in the second technology test-run Coplanar Waveguide (CPW) Characteristics For technological reasons, the CPW transitions contacting the embedded chip pads have wider gaps. Due to their position in the thin film layers, they are guided not on top of the dielectric but inside a dielectric layer. Both these facts result in producing opposite effects. As they compensate mutually, the total deviations of the electrical properties of the CPW-structure remain small. In Figure 7 and Figure 8, the effects of small deviations in line width w on the characteristic impedance are shown for the transmission line elements from the substrate to the chip for TEC01 and TEC 05 with and dielectrics. The values vary slighly in the frequency range GHz. Figure 9 presents the same data for the substrate wiring. Both cases, and dielectrics, are treated. The ground-metallization is 150 µm wide, and the metallization thickness is 5 µm. The values do not change significantly in the frequency range GHz. A Re(Z)/Ohm µm w(nominal) = 65 µm -1 substrate GaAs-chip delta-w/µm epoxy gap Figure 8. Effects of tolerances in line width w on characteristic impedance of the transmission line elements from substrate to chip for TEC05 with dielectric and at f = 20 GHz. Re(Z)/Ohm valid for f = GHz -1 -dielectric w(nominal) = 80 µm delta-w/um -dielectric w(nominal) = 78 µm Figure 9. Effects of small tolerances in the line width w on characteristic impedance of CPW-lines. 122

5 System Integration for High Frequency Applications In Figure 10, the calculated nominal values and the measured data of a CPW on are depicted and demonstrate good agreement. The effects of deviations in the line width w, dielectric constant e r and thickness d may vary the characteristic impedance in a range 47 < Re(Z L ) <54 Ohm as shown by the tolerance curves. Most probably small deviations in both, width w and e r are the reason of the deviation of the measured data from the nominal calculated values Microstrip Characteristics For the MS on -dielectric, Figure 12 depicts the nominal values of the characteristic impedance and e reff =(b/ b 0 ) 2, the square of the real part of the normalized phase constant, in a frequency range up to 30 GHz, as well as their deviations when varying the strip width, the dielectric constant, and the thickness of the dielectric. 56 w = 74 µm 150 µ m 11 µ m 78 µ m m g w κ = 1.74*10^7 S/m d=35 µ m h=550 µ m ε r = 3.3 tan δ = ε r = 9.8 2,8 2,7 2,6 d=25 µ m l=5 µ m κ = 1.74*10^7 S/m µ m w ε r = 2.7 tan δ = Re(ZL)/Ohm h = 44 µm h = 26 µm εr = 2.7 measured nominal εr = 3.9 w = 82 µm Figure 10. Characteristic impedance of a CPW on -dielectric and its deviations depending on the variation of strip width, dielectric constant and thickness of the dielectric (h = 35 µm, e r = 3.3, tan d = 0.02, w=78 µm, ground to ground = 100 µm, ceramic carrier). In Figure 11, the calculated and the measured data of a CPW structure on show also good agreement. The CPW-lines are realized on different substrates and then measured with different equipment systems. They are compared to the calculated results. A -structure (dimensions calculated for -dielectric) but dielectric used is considered. An estimated agreement in the results better than 6 % is demonstrated. Re(Zw)/Ohm ereff ,5 2,4 2,3 2,2 εr = 2.5 h=550 µ m w = 70 µm ε r = 9.8 εr = 2.9 h = 15 µm nominal w = 50 µm h = 35 µm measured 2, ε r = 2.5 ε r = 2.9 w = 70 µm nominal measured κ = 1.74*10^7 S/m h = 35 µm w = 50 µm µ m w κ = 1.74*10^7 S/m d=35 µ m 150 µ m 11 µ m 78 µ m m g w ε r = 2.7 tan δ = h = 15 µm d=25 µ m l=5 µ m h=550 µ m ε r = 2.7 tan δ = ε r = 9.8 Re(Z)/Ohm h=550 µ m ε r = 9.8 calculated Figure 12. Characteristic effective permittivity e reff =(b/b 0 ) 2 and impedance of a MS on -dielectric and their deviations depending on the variation of strip width, dielectric constant and thickness of the dielectric (h = 25 µm, e r = 2.7, tan d = (worst-case), w = µm, ceramic carrier). measured The ground-metallization has a width of 250 µm, and the metallization thickness is 5 µm. The thin film process described above guarantees an accuracy of ±1 µm for strip width and thickness of Figure 11. Comparison of calculated CPW characteristic impedance to measurements. in the characteristic impedance, and the same variation in thickness dielectric. A ±1 µm strip-width variation yields a deviation of ±1.3 % of the dielectric causes ±2.8 % change of the nominal characteristic impedance value. The deviations of e reff are smaller than ±1 %, so that the propagation constant changes by less than ±0.5 %. The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 1, First Quarter 1998 (ISSN ) 123

6 Intl. Journal of Microcircuits and Electronic Packaging The corresponding data for dielectric show that a variation in strip width causes a ±1.2 % deviation in the characteristic impedance, and the same variation of the dielectric thickness leads to a deviation of ±2.8 %. In both cases, the deviations can be tolerated and fulfill the practical requirements. In Figure 13, the effects of small deviations in the line width w on the characteristic impedance of MS-lines are shown for both cases, - and -dielectric, respectively. The values do not change significantly in the frequency range from GHz. Re (Z) /Ohm 51, , ,5 49,5 valid for f = GHz -dielectric w(nominal)=64 µm -dielectric w(nominal)= µm 3.5. Microstrip Structure with Meshed Ground If the ground plane is buried into the dielectric polyimide layer, it is necessary to realize meshed ground structures, due to the outgassing of the polyimide during curing taken into account. The effect of the meshed ground plane on the line parameters, the impedance, and the attenuation constant were investigated for the polymer ( 2722). The high frequency measurements investigate transmission lines (width: 30 µm) for two different meshed ground geometries (40x40 µm², x µm²) and varying disalignment (V= 0 µm - 40 µm) between the signal line and the meshed ground. Figure 15 and Figure 16 present the line parameters the impedance, versus frequency for the 40x40 µm² and x µm² meshed structures, respectively Z [V=5µm] Z [V=10µm] Z [V=20µm] Z [V=30µm] Z [V=35µm] delta-w/µm Figure 13. Effects of small deviations in the line width w onto the characteristic impedance of MS-lines. For synthesis purposes, Figure 14 shows strip width and attenuation for a 50W-MS on -dielectric in dependence of the thickness of the dielectric f[gh z] Figure 15. Characteristic impedance versus frequency ( 2722, 40x40 µm² meshed) : w 2 : alpha 0,16 microstrip W / µm h/µm 1 0,15 0,14 0,13 0,12 0,11 0,1 0,09 0,08 0,07 0,06 alpha / (db/mm) Z Z [V=0µm]. Z [V=10µm] Z [V=30µm] Z [V=40µm] f[gh z] Figure 14. Strip width w and attenuation a versus thickness of dielectric for a MS with -dielectric. Figure 16. Characteristic impedance versus frequency ( 2722, x µm² meshed). 124

7 System Integration for High Frequency Applications The measurement results indicate that the assumption of an increase of the characteristic impedance due to openings in the meshed ground layer is not always a valid assumption. Depending on the thickness of the first polymer layer (h = 10 µm), the influence of the ceramic substrate results in a decreasing impedance with increasing disalignment V for the smaller mesh openings while the impedance increases for the larger ones 6. Table 2 and Figure 17 present the results of the measured conductance and the loss factor tan d for the dielectric 2722 and the material. It is shown that for both materials, the loss factor tan d obtained from the measurements differs strongly from the supplier data. In the case of, the dielectric losses are significant. Since the dielectric losses increase proportionally to the frequency, they become a severe problem in the frequency range over 10 GHz. Table 2. Measured loss factor (tan d ); f = 2GHz. C [pf/cm] G [ms/cm] tgδ[%] Results of the influence of a disalignment between the signal line and the meshed ground on the characteristic impedance for a MSstructure using polyimide as a dielectric are presented. In summary, the results indicate that the impact of small variations in geometry caused by the technological process on the line parameters meets the practical requirements in terms of signal transmission. Microstrip structures for the wiring on the substrate and the as the dielectric are well suited for high frequency applications in the GHz range. Acknowledgments The authors would like especially thank Mr. R. Doerner (FBH), Mr. D. Petter, and Mr. D. Weiher for the electrical measurements. References Conductance[S/cm] 5E-4 4E-4 3E-4 2E-4 1E f[ghz] Figure 17. Conductance versus frequency ( 2722, Cyclotene 4026). 4. Conclusions Highly integrated systems with controlled characteristic impedance can be realized using thin film technology (MCM-D). The combination with a chip embedding technique gives the possibility to realize an impedance-controlled interconnection between the chip and the substrate wiring too, which is of interest for high performance systems. The effect of variation of the linewidth and the dielectric thickness on the impedance is discussed for MS and CPW transmission lines using polyimide ( 2722) and The International (Cyclotene 4026) Journal as dielectrics. of Microcircuits and Electronic Packaging, Volume 21, Number 1, First Quarter 1998 (ISSN ) 1. M. Töpper, K. Buschick, J. Wolf, V. Glaw, R. Hahn, A. Dabok, O. Ehrmann, and H. Reichl, Embedding Technology- A Chip- First Approach using, Procceding of The Third International Symposium on Advanced Packaging Materials, Braselton, Georgia, pp.11-14, March M. Töpper, J. Wolf, V. Glaw, K. Buschick, A. Dabek, L. Dietrich, O. Ehrmann, and H. Reichl, MCM-D with Embedded Active and Passive Components, Proceedings of The International Microelectronics Conference, IMAPS 96, Minneapolis, Minnesota, pp , October A.J.G. Strandjord, Y. Ida, P.E. Garrou, W.B. Rogers, S.L. Cummings, and S.R. Kisting, MCM-D Fabrication with Photosensitive : Processing, Solder Bumping, Systems Assembly, and Testing Proceedings of The International Microelectronics Conference, ISHM 95, Los Angeles, California, pp , October W. Heinrich, Full-Wave Analysis of Conductor Losses on MMIC Transmission Lines, IEEE Transactions On Microwaves Theory and Techniques, MTT, Vol. 38, pp , K. Beilenhoff, W. Heinrich, and H.L.Hartnagel, Improved Finite-Difference Formulation in Frequency Domain for Three- Dimensional Scattering Problems IEEE Transactions On Microwaves Theory and Techniques, MTT, Vol. 40, No. 3, pp , A. Owzar, M. Kasper, and J. Wolf, Electrical Characterization of Thin film Wiring using Meshed Ground, Proccedings of The Third VLSI Packaging Workshop of Japan, Kyoto, Japan, December

8 Intl. Journal of Microcircuits and Electronic Packaging About the authors Jürgen Wolf received the M.S. Degree in Electrical Engineering in From 1979 to 1989, he was working as an R&D engineer for chip&wire interconnection for optoelectronical hybrid systems. In 1990, he joined the Technical University of Berlin - Microperipheric Technologies. He was involved in the development of solder bumping and the application of flip chip technology for multichip modules. In 1994, he joined the Fraunhofer Institute - IZM in Berlin. Currently, he is working in the Packaging Department for MCM where he is responsible for technology development for high frequency systems in MCMs, microsystems, and bumping. He is a member of IMAPS society. field: Development of sputtered metallizations for packaging applications. In 1994 he became head of the department Multichip Modules at the Fraunhofer Institut Reliability and Microintegration (IZM). Herbert Reichl is the Director of the Microperipheric Technology Center at the Technical University of Berlin (TUB) and of the Fraunhofer Institute Reliability and Microintegration (IZM) Berlin. He received his M.S. and Ph.D Degrees in Electrical Engineering from the Technical University of Munich, Germany. Prof. Reichl is the general Chairman of the SMT / ASIC / Hybrid Conference and MicroSystem Technologies Conference in Germany. F. J. Schmückle studied at the FH Wiesbaden ( 77-80) and the TH Darmstadt ( 80-85). He then worked at the Fernuniversität, Germany ( 86-91) together with Prof. Pregla on numerical investigations of electromagnetic fields and waves applying the Method of Lines. After obtaining his Ph.D. Degree, he worked with a CAD-company ( 91-93) and since 1994 he is with the Ferdinand- Braun-Institut, Berlin, Germany where his work focusses on field theory, parameter extraction of passive and active elements, passive structure synthesis, and layout generation. Wolfgang Heinrich was born in Frankfurt, West Germany, in 19. He received the Dipl.-Ing., Dr.-Ing. and the habilitation degrees in 1982, 1987 and 1992, respectively, all from the Technical University of Darmstadt, Germany. In 1983, he joined the staff of the Institut für Hochfrequenztechnik of the same University working on field-theoretical analysis and simulation of planar transmission lines. Since April 1993, he is with the Ferdinand-Braun-Institut at Berlin, Germany, as head of the microwave Department. His present research activities focus on the CAD of MMIC elements and related packaging problems and on microwave circuit design. Michael Toepper studied Chemistry at the University of Karlsruhe, where he received his M.S. Degree in At the Institute of Macromolecular Chemistry, his research work was the investigation of intermolecular forces of polymers and latices. He joined the Microperipherics Technology Center of the Technical University Berlin (TUB) at 1994 as a research scientist. He is in the Packaging Department for MCM of the joint institues of the TUB and IZM. His main working area is the development of thin film polymer processes. Klaus Buschick received the M.S. Degree in Physics from the Technical University of Berlin. He spent 4 years on basic research in radiation chemistry and has 9 years experience in R&D of thin film technology as a specialist for microsystem technologies. Oswin Ehrmann studied Physics at the Technical University of Berlin (TUB). After receiving his diploma in 1987, he joined the Reserch Center of Microperipheric Technologies at the Faculty of Electrical Engineering of TUB. There, he has been working in the 126