Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) Hermetic Through-Wafer Connections in Silicon Substrates
|
|
- Jemimah Golden
- 6 years ago
- Views:
Transcription
1 Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) Hermetic Through-Wafer Connections in Silicon Substrates Abstract We present the design, fabrication technology, and experimental evaluation of the high frequency performance of a new type of hermetically sealed through-wafer interconnects (µ-vias) in silicon substrates. The application of these µ-vias for wafer-scale hermetic packaging of receiver and transmitter optical subassemblies at 10Gbit/s, and for packaging of micro electro mechanical devices (MEMS) is discussed. These examples illustrate the potential of the technology to simplify the design of e.g. ball grid array packages (BGAs) in a cost effective way without sacrificing RF performance even at very high frequencies. Bandwidth measurements of the µ-via structures show reflections below -25dB up to 35GHz in a coplanar configuration even with multiple µ-vias in the path of a 50 Ω coplanar line. Additional losses due to the µ-vias are very low and below the detection limit of a 2.5mm long path. The waveguide losses were about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz. Excellent performance of the µ-vias is achieved by reducing their effective depth. On a 350µm or 500µm thick substrate the effective via depth can e.g. be reduced to only 20µm. The remaining depth is covered by impedance controlled coplanar lines that run down the slanted side wall of cavities in the silicon substrate. The concept thus combines the mechanical stability of substrates that are a few hundreds of microns thick with the ease to fabricate µ-vias in a membrane that is only a few tenths of microns thick. The pitch of these vias can be below 100 µm allowing for very high density interconnects as e.g. required in packaging of multi channel optical modules. The coplanar lines on the cavity side walls are realized by 3D photolithography using an electro-deposited photoresist and proximity exposure. The cavities with angled side walls are wet etched in aqueous KOH solution from one side of the substrate leaving a thin membrane in the bottom of the cavity (e.g. 20µm). This membrane is then opened up from the back side at the locations of the µ-vias in an additional KOH etching step. After structuring the metal lines the openings in the membranes are hermetically sealed by metal plating. The metallization scheme on which the vias and the electrical leads are based is compatible with reflow soldering and wire bonding. As an additional advantage the cavities can be enlarged and used as head room for discrete electro/optical components that are assembled on a lid wafer, or the components can be directly assembled in the cavity. Coplanar metal lines in combination with the proposed via technology allow the R. Hauffe, A. Kilian, M. Winter, L. Shiv, G. Elger, M. Heschel, J. Kuhmann, S. Isaacs, S. Weichel, P. Gaal, H. Korth, A. Hase Hymite GmbH Carl-Scheele-Str. 12, D Berlin rha@hymite.com, tel.: +49 (0) impedance matched connection of these high speed components to a Ball Grid Array (BGA) on the back side of the hermetic enclosure which in turn can be soldered to a rigid circuit board or to a flexible circuit board. Due to the tight control of tolerances and the dense via pitch it is easily possible to route multiple RF ports in and out of the package even in differential configurations and with additional DC control signals while still maintaining a very small footprint and excellent signal integrity. The presented via technology is not only able to fulfill today s requirements in hermetic and cost effective packaging of high bit rate electro/optical modules but scales to bit rates above 40GHz and to packages with very large numbers of I/O counts. Concept and application of broad band RF µ-vias µ-vias in silicon substrates is an enabling technology in wafer level packaging to turn MEMS devices, integrated circuits and subassemblies on silicon benches into FLIP CHIP or BGA components. In combination with wafer bonding and/or soldering they can also be used for wafer stacking and enable complex System On Package (SOP) modules [1-6]. The required key features of such µ-vias are: High power through put Broad band high frequency performance High spatial density of interconnects Hermeticity Low cost. The µ-via concept for silicon substrates described here meets all these requirements and is based on cost effective batch processing like: Wet etching of V-grooves from both sides of a silicon substrate. Wet structuring of metal features on the resultant nonplanar wafer surface. Hermetic sealing of the wet etched through-holes by metal plating. Figure 1 illustrates the concept for a coplanar line that passes from one side of a silicon wafer to the other side. A wafer with this kind of via technology can have standard thicknesses (e.g. 400µm or 500µm) and does not need to be thinned down which simplifies the handling during processing. At high frequencies, a standard via [7] created e.g. by laser ablation, laser cutting, powder blasting, or deep reactive ion etching (DRIE) would introduce significant signal distortion if used for these substrate thicknesses. In the contrary, the proposed µ-via concept covers most of the depth /05/$ IEEE 324
2 with an impedance controlled coplanar line that runs down the side wall of a large silicon cavity. At the bottom of the cavity only a very thin membrane (usually 20µm-60µm) needs to be tunneled by the signal and ground lines, with negligible compromises on impedance matching and field distortion. High power µ-vias can be realized by combining multiple vias per interconnect. The via pitch can be below 100µm. (a) large cavity side silicon wafers a timed etch is required. The depth of the large cavity is usually several hundreds of microns, whereas the depth of the small cavities is a few tenths of microns. The via size at the narrow end, where the two cavities meet, can be very small. Typical values are between 5µm and 20µm with very low tolerances. If wafers with standard orientation are used the angle of the side walls is fixed (54.74 ). The resultant structure is visualized in Figure 4a. m etallization line metallization on the top, the side wall, and the bottom of the cavity m etallization three or more (b) sm all (via) c avity side metallization cavities sealed with plated metal m etallization Figure 2: SEM photograph of a cross section through a µ-via Silicon cavity location of 50 µm line metallization plated Au (c) metal structures on transparent port 1 solder bumps solder dam metal port 2 Figure 1: CPW µ-via connection for silicon substrates Technology for µ-via fabrication The µ-vias are fabricated in silicon wafers (4" or 6" in diameter). Depending on the application, these can be Silicon On Insulator (SOI) wafers or regular silicon wafers both with high or low resistivity. If large bandwidths are required, high resistivity material (>4000Ωcm) is preferable to avoid a loss increase at higher frequencies. The first processing steps create the large and small cavities and include deposition and structuring of silicon oxide and silicon nitride masks for wet etching with e.g. aqueous KOH solution. The etching is done from both sides. For SOI wafers the buried oxide layer (BOX) serves as an etch stop (for the large and the small cavities). For regular DC lines CPW RF lines Silic o n with SiO 2 passivation Figure 3: Photograph of a micro machined silicon chip (BGA) with coplanar lines on a non-planar topography. At the bottom of the cavities the lines tunnel to the back of the chip through µ-vias. For special applications the process is also developed for angle cut wafers that allow one of the side walls to be tilted at 45 (can e.g. serve as a mirror for optical beams). Special care must be taken to keep the side wall roughness at a very low level. After deposition of a thin passivation layer (e.g. less than 1µm of thermal SiO 2 ) a thin film metal stack is evaporated or sputtered on both sides of the wafer. The stack is chosen such that it can serve as a plating base, an under bump metallization (UBM), and a solder dam in different regions of the wafers. The functionality is adjusted by partial (masked) etching of the metal stack. As shown in Figure 3 this metal stack allows the combination of the µ-vias with BGA and Flip Chip applications. 325
3 The thin film metal stack does not seal the through-holes between the wafer sides. The hermetic sealing is achieved by plating several microns of metal (e.g. Au or Cu). If solder deposition is required, Sn can also be added in a plated stack. The cross section of a sealed µ-via is shown in Figure 4b. One of the challenges in the metallization process is the structuring of etch masks and plating masks on highly nonplanar surfaces (large cavities are several 100µm deep). This is done by using an electrophoretic photoresist that is deposited by galvanic. Smallest feature sizes created by proximity lithography are in the range of 20µm with tolerances of a few microns. (a) α= 54,74 large wet etched c avity narrow well defined through connection cap wafer with the µ-vias to a second silicon substrate [8]. The solder is applied either as performs or by electroplating. Very small hermetic enclosures are formed between the two silicon substrates. A schematic drawing of the test samples is shown in Figure 5. Tests were carried out according to the Bellcore GR CORE requirement and included: temperature cycling, high/low temperature storage, damp heat, mechanical shock, vibration and thermal shock. The inspection was carried out by optical leak testing and Helium leak testing (MIL-STD-883D method ). The fail criteria was a leak rate of atm cc/sec or above. Each test group contained at least 11 samples and all samples of each group passed the test. High frequency test structures and measurements A test structure was designed to prove the broad band high frequency potential of the µ-via concept. The test structure is shown in Figure 6. (a) large cavity side (b) small cavity side (b) small wet etched cavity structured metallization on the side wall tapered on cavity side wall port 1 w g port 2 plating base thin film metal stack structured metallization (c) cross section along the plated metal l4 h2 passivation layer hermetically sealed with plated metal Figure 4: Cross section of a µ-via (a: without metallization, b: with metallization). hermetic enclosure sealing ring sealed wafer Silicon cap wafer Figure 5: Schematic drawing of the reliability test samples The reliability (hermeticity) of the µ-vias was demonstrated in combination with a general hermetic packaging concept that involves the soldering of the silicon 326 port 1 l1 l2 l3 l5 port 2 Figure 6: Schematic drawing of the RF test structure The metal lines consist of approximately 7µm plated gold on high resistivity silicon (ρ>4000ωcm) and are designed to achieve minimum reflection and maximum transmission in a 50Ω system for broad band applications. A coplanar line starts out on the through-hole side of the wafer ( port 1), approaches an µ-vias for the signal and ground lines (line segments l 1 and l 2 in Figure 6c), and tunnels to the large cavity side. The CPW continues on the bottom of the large cavity, moves up the slanted cavity side wall and ends up on the thick silicon substrate area at the top of the cavities (line segments l 3, l 4 and l 5 in Figure 6c). The pass is than reversed and ends up on the through-hole side at signal port 2 again. Please note that the s on the cavity side walls and the through-hole side should be tapered to achieve optimum matching to 50Ω throughout the whole structure. This is required as the line impedance depends on the h1
4 substrate thickness. For example a substrate thickness of 370µm (h 1 +h 2 ) requires a line width w in the order of 30µm which is increased above 70µm for a substrate thickness of 20µm (h 1 ). In both cases the gap width is assumed to be g=30µm (definition of variables is given in Figure 6). The following parameter values describe the line for which results are presented below: l 1 =225µm, l 2 =275µm, l 3 =275µm, l 4 =430µm, l 5 =50µm, w=45µm (mean value), g=30µm, h 1 =20µm, h 2 =350µm. The over all link length is more than 2.5mm, far more than is required in typical packaging applications. The link also includes two µ-via connections whereas usually only one will be required for BGA packages. Therefore the µ-via test structure provides a worst case estimate of the achievable broad band RF performance in silicon packages based on this technology. S-parameter measurements were carried out with coplanar 50Ω probes placed at port 1 and port 2. Results are shown in Figures S 21 [db] Figure 9: Transmission from port 1 to port S 11 [db] arg(s 21 ) [ ] Figure 7: Reflections at signal port 1. arg(s 11 ) [ ] Figure 8: Phase shift of reflections at signal port Figure 10: Phase shift of a transmitted signal from signal port 1 to signal port 2. The transmission and reflection values plotted versus frequency clearly indicate that applications with bandwidths of at least 40GHz can be supported with this kind of structure. The waveguide losses are about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz which does not significantly deviate from a simple straight reference line. Consequently it was not possible to extract the losses introduced by the µ-vias experimentally. Simulations indicate that the additional losses are below 0.02dB at 10GHz. Reflections of the full structure remain below -25dB up to 35GHz and below -15dB up to 40GHz. Modeling of test structures Modeling of the test structures was carried out by full 3D FEM simulations and by simplified circuit simulations. In both cases excellent agreement with the measurements was achieved as shown in Figures In the 3D FEM simulations the complete structure of the test samples was implemented and solved (Figure 6). The only free parameter to adjust the simulation to the
5 measurement was the material loss (conductivity of substrate and metal). (a) half test struc ture equivalent circuit segment l1 lumped via equivalent circuit segment l4 be relatively thick (h 1 =300µm); µ-vias were omitted. The over all line length was about 5mm and the line width was w=200µm with a corresponding gap width of g=120µm. As the membrane is relatively thick no tapering of line width and gap width was applied in the cavity region. Due to the large cross section of the CPWs measurements were only performed up to 15GHz. wafer wafer 1 C p segment l2 seg m en t l3 segment l (b) full test structure equivalent circuit port 1 port 2 (c ) lumped via equivalent circuit S 21 [db] S 11 [db] -35 R L wafer wafer 2 c c half test structure equivalent circuit Figure 11: Equivalent circuit for the RF test structure including the µ-vias For the circuit simulations an equivalent circuit was derived (Figure 11). The CPWs were modeled using line equations with propagation constants and line impedances according to the fundamental CPW mode. For the lines on or underneath the slanted side walls (line section l 1 and l 3 ) an effective substrate thickness was assumed (between the values of h 1 and h 1 +h 2 ). The µ-vias are described by a simple R, L, C equivalent circuit whose elements were derived from 3D FEM simulations as: L=10pH, C=1fF, 10GHz and 30GHz. The inductance and capacitance are frequency independent whereas the increase in radiation loss with frequency requires a frequency dependant resistance R. The only additional parasitic element introduced for an adequate fit between measurement and simulation is the parasitic capacitance C p which is justified by the ground plane underneath line segment l 1. Its value was extracted as C p =15fF. The good agreement of the modeled data to the measurements proves the reliability of predicting the high frequency performance of packages based on the described µ- via technology by simulations. Tolerances of coplanar lines on non-planar topologies One of the major concerns for the reliability of the excellent RF via performance are the geometric tolerances of coplanar lines created in the cavities and on the slanted side walls by proximity lithography. Figure 12 shows data from 60 identical s from 3 different wafers (20 lines on each wafer). The wafers were processed individually. The lines run down into a cavity (h 2 =350µm deep) and up again on the other end. To simplify the investigation on tolerances, the membrane on the cavity bottom was chosen to 328 S 21 [db] S 21 [GHz] wafer S 11 [db] S 11 [db] -35 wafer Figure 12: S-parameter data for 60 coplanar waveguides running through silicon cavities Geometric variations are in the order of a few microns and were by visual inspection. These low tolerances are verified by the very low reflections (below -25dB) over the whole frequency range and with low losses below 0.2dB/mm at 10GHz. Application of µ-vias in wafer level packaging The proposed µ-via technology can be implemented in silicon packages for several application fields like Telecommunication, Datacommunication and MEMS.
6 at the cavity bottom ICs and optic al devices assembled in the large cavities (a ) pair of coplanar differential RF lines very short wire bonds to the cavity edge (ground and RF connections) (b) ICs and optic al devices assembled on the flat substrate side Figure 14: Measured sensitivity of a receiver optical subassembly including µ-vias (dbm for a BER of at 10.7 Gbit/s with PRBS23) One example are receiver optical subassemblies (PIN/TIA combinations) for 10Gbit/s (Figure 13) that have been demonstrated to provide excellent sensitivity on silicon submounts including µ-vias in the RF path (Figure 14). optical transparent lid sealing ring under bump metalliza tion Si/SiO 2 solder dam Silicon submount with hermetic (c) plated metal BGA interfac e FLEX wet etched cavity coplanar line Figure 13: Photographs of different receiver optical subassemblies (10Gbit/s) on silicon submounts with µ-vias (a: assembly in large cavities, b: assembly on the flat side of the chip, c: large cavity side of the assembly in (b)). In general the silicon chip serves as a submount for IC components and optical devices or as a micro cap that hermetically seals components that are micro machined or assembled on a second silicon wafer. If the µ-via wafer serves as a submount (or rather a large matrix of submounts) the components are hermetically sealed with either a planar or micro-machined lid wafer by soldering. 329 FLEX interface to planar circuit board Figure 15: Exploded view of a hermetically sealed receiver optical subassembly on a silicon submount with µ-vias, including a FLEX interface. Two fundamentally different assembly strategies can be applied. In the first case, the components are assembled in the large cavities (Figure 13a). In the second case, the components are assembled on the flat side (through-hole side) as shown in Figure 13b. The large cavities are then on the back side of the chip (Figure 3 and Figure 13c) which also
7 serves as the interface to a circuit board or flexible circuit board. The complete packaging concept is visualized in Figure 15 including a flexible circuit board and an optical transparent lid for sealing. Similarly, transmitter optical subassemblies have been demonstrated both for VCSEL and edge emitter applications [9]. (a) cap wafer (c) fine pitch so ld er connection MEMS wafer (b) (d) cap wafer fine pitch so ld er connection solder ball arrray sealing ring Figure 16: Application of the RF µ-vias on cap wafers that hermetically seal RF MEMS devices and turn them into SMD components. (a: schematic cross section through a MEMS and silicon cap assembly, b: schematic drawing of the MEMS and cap chip before assembly, c and d: sealed MEMS device with BGA on the back side of the cap chip) Somewhat different is the application of the µ-via technology on cap wafers that do not serve as submounts for components. In this case the large cavities can serve as head room for components or micro machined structures on the wafer that is sealed with the cap wafer. In addition to the sealing, fine pitch electrical connections are established by soldering, to turn the packaged devices into SMD compatible components with the BGA on the back side of the cap wafer. This packaging principle is depicted in Figure 16. Conclusions We have presented a new type of hermetically sealed RF µ-vias in silicon substrates based on micro-machining and proximity lithography. The excellent broad band RF performance of these µ-vias up to 40GHz was proven by measurements. Reflections were below -25dB up to 35GHz and losses were about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz. It was also shown that structures on non-planar topologies can be reproduced with high accuracy and with the low tolerances required for good impedance matching. Several application examples for this via technology in wafer scale packing of RF and optical components were given along with some performance data of these devices which underlines the great potential of this technology for cost effective high performance packaging solutions. References 1. Umemoto, M. et al., High Performance Vertical Interconnection for high density 3D Stacking Packages, Proc 54 th Electronic Components and Technology Conf, Las Vegas, NV, May. 2004, pp Strohm, K.M. et al., "Via hole technology for microstrip transmission lines and passive elements on high resistivity silicon," Microwave Symposium Digest, 1999 IEEE MTT- S International, Page(s): vol Quine, J.P. et al., "Characterization of via connections in silicon circuit boards," Microwave Theory and Techniques, IEEE Transactions on, Volume: 36, Issue: 1, Jan. 1988, Pages: Tsui, Y.K. et al., "Three-dimensional packaging for multichip module with through-the-silicon via hole," 5th Conference (EPTC 2003), 2003, Pages: Wu, J.H. et al., "A Through-Wafer Interconnect in Silicon for RFICs," Electron Devices, IEEE Transactions on, Volume: 51, Issue: 11, Nov. 2004, Pages: Spiesshoefer, S. et al., "Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development," ECTC '04. Proceedings, 2004., 1-4 June 2004, Pages: Vol.1 7. Polyakow, A. et al, Comparison of Via-Fabrication Techniques for Through-Wafer Electrical Interconnect Applications, Proc 54 th Electronic Components and Technology Conf, Las Vegas, NV, May. 2004, pp Elger, G. et al, Optical Leak Detection for Wafer Level Hermeticity Testing, Proc SEMICON, Winter, M. et al., Simplified Optical Coupling and Alignment Scheme for Cost Effective 10Gbit/s TOSA Modules Based on Edge Emitters Hermetically Packaged in Micro-Machined Silicon Structures, accepted for publication at OFC, Annaheim, CA, March
Low Thermal Resistance Flip-Chip Bonding of 850nm 2-D VCSEL Arrays Capable of 10 Gbit/s/ch Operation
Low Thermal Resistance Flip-Chip Bonding of 85nm -D VCSEL Arrays Capable of 1 Gbit/s/ch Operation Hendrik Roscher In 3, our well established technology of flip-chip mounted -D 85 nm backside-emitting VCSEL
More informationHermetic Packaging Solutions using Borosilicate Glass Thin Films. Lithoglas Hermetic Packaging Solutions using Borosilicate Glass Thin Films
Hermetic Packaging Solutions using Borosilicate Glass Thin Films 1 Company Profile Company founded in 2006 ISO 9001:2008 qualified since 2011 Headquarters and Production in Dresden, Germany Production
More information64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array
64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array 69 64 Channel Flip-Chip Mounted Selectively Oxidized GaAs VCSEL Array Roland Jäger and Christian Jung We have designed and fabricated
More informationA Miniaturized Multi-Channel TR Module Design Based on Silicon Substrate
Progress In Electromagnetics Research Letters, Vol. 74, 117 123, 2018 A Miniaturized Multi-Channel TR Module Design Based on Silicon Substrate Jun Zhou 1, 2, *, Jiapeng Yang 1, Donglei Zhao 1, and Dongsheng
More informationWafer-scale 3D integration of silicon-on-insulator RF amplifiers
Wafer-scale integration of silicon-on-insulator RF amplifiers The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published
More informationHigh Frequency Single & Multi-chip Modules based on LCP Substrates
High Frequency Single & Multi-chip Modules based on Substrates Overview Labtech Microwave has produced modules for MMIC s (microwave monolithic integrated circuits) based on (liquid crystal polymer) substrates
More informationChapter 2. Literature Review
Chapter 2 Literature Review 2.1 Development of Electronic Packaging Electronic Packaging is to assemble an integrated circuit device with specific function and to connect with other electronic devices.
More informationFlip-Chip for MM-Wave and Broadband Packaging
1 Flip-Chip for MM-Wave and Broadband Packaging Wolfgang Heinrich Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH) Berlin / Germany with contributions by F. J. Schmückle Motivation Growing markets
More informationSHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING
SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING M Bartek 1, S M Sinaga 1, G Zilber 2, D Teomin 2, A Polyakov 1, J N Burghartz 1 1 Delft University of Technology, Lab of
More informationTrue Three-Dimensional Interconnections
True Three-Dimensional Interconnections Satoshi Yamamoto, 1 Hiroyuki Wakioka, 1 Osamu Nukaga, 1 Takanao Suzuki, 2 and Tatsuo Suemasu 1 As one of the next-generation through-hole interconnection (THI) technologies,
More informationFlip chip Assembly with Sub-micron 3D Re-alignment via Solder Surface Tension
Flip chip Assembly with Sub-micron 3D Re-alignment via Solder Surface Tension Jae-Woong Nah*, Yves Martin, Swetha Kamlapurkar, Sebastian Engelmann, Robert L. Bruce, and Tymon Barwicz IBM T. J. Watson Research
More informationMEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications
MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications Part I: RF Applications Introductions and Motivations What are RF MEMS? Example Devices RFIC RFIC consists of Active components
More informationIntroduction: Planar Transmission Lines
Chapter-1 Introduction: Planar Transmission Lines 1.1 Overview Microwave integrated circuit (MIC) techniques represent an extension of integrated circuit technology to microwave frequencies. Since four
More informationHigh-yield Fabrication Methods for MEMS Tilt Mirror Array for Optical Switches
: MEMS Device Technologies High-yield Fabrication Methods for MEMS Tilt Mirror Array for Optical Switches Joji Yamaguchi, Tomomi Sakata, Nobuhiro Shimoyama, Hiromu Ishii, Fusao Shimokawa, and Tsuyoshi
More informationCopyright 2008 Year IEEE. Reprinted from IEEE ECTC May 2008, Florida USA.. This material is posted here with permission of the IEEE.
Copyright 2008 Year IEEE. Reprinted from IEEE ECTC 2008. 27-30 May 2008, Florida USA.. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE
More informationAn X band RF MEMS switch based on silicon-on-glass architecture
Sādhanā Vol. 34, Part 4, August 2009, pp. 625 631. Printed in India An X band RF MEMS switch based on silicon-on-glass architecture M S GIRIDHAR, ASHWINI JAMBHALIKAR, J JOHN, R ISLAM, C L NAGENDRA and
More informationA passive circuit based RF optimization methodology for wireless sensor network nodes. Article (peer-reviewed)
Title Author(s) Editor(s) A passive circuit based RF optimization methodology for wireless sensor network nodes Zheng, Liqiang; Mathewson, Alan; O'Flynn, Brendan; Hayes, Michael; Ó Mathúna, S. Cian Wu,
More informationSILICON BASED VERTICAL MICRO-COAXIAL TRAN- SITION FOR HIGH FREQUENCY PACKAGING TECH- NOLOGIES
Progress In Electromagnetics Research B, Vol. 50, 1 17, 2013 SILICON BASED VERTICAL MICRO-COAXIAL TRAN- SITION FOR HIGH FREQUENCY PACKAGING TECH- NOLOGIES Justin Boone *, Subramanian Krishnan, and Shekhar
More informationHigh Performance Silicon-Based Inductors for RF Integrated Passive Devices
Progress In Electromagnetics Research, Vol. 146, 181 186, 2014 High Performance Silicon-Based Inductors for RF Integrated Passive Devices Mei Han, Gaowei Xu, and Le Luo * Abstract High-Q inductors are
More informationThis is the accepted version of a paper presented at 2018 IEEE/MTT-S International Microwave Symposium - IMS, Philadelphia, PA, June 2018.
http://www.diva-portal.org Postprint This is the accepted version of a paper presented at 2018 IEEE/MTT-S International Microwave Symposium - IMS, Philadelphia, PA, 10-15 June 2018. Citation for the original
More informationFlip-Chip Integration of 2-D 850 nm Backside Emitting Vertical Cavity Laser Diode Arrays
Flip-Chip Integration of 2-D 850 nm Backside Emitting Vertical Cavity Laser Diode Arrays Hendrik Roscher Two-dimensional (2-D) arrays of 850 nm substrate side emitting oxide-confined verticalcavity lasers
More informationinsert link to the published version of your paper
Citation Niels Van Thienen, Wouter Steyaert, Yang Zhang, Patrick Reynaert, (215), On-chip and In-package Antennas for mm-wave CMOS Circuits Proceedings of the 9th European Conference on Antennas and Propagation
More informationApplication Note 5525
Using the Wafer Scale Packaged Detector in 2 to 6 GHz Applications Application Note 5525 Introduction The is a broadband directional coupler with integrated temperature compensated detector designed for
More informationCHAPTER 4. Practical Design
CHAPTER 4 Practical Design The results in Chapter 3 indicate that the 2-D CCS TL can be used to synthesize a wider range of characteristic impedance, flatten propagation characteristics, and place passive
More informationSilicon Interposers enable high performance capacitors
Interposers between ICs and package substrates that contain thin film capacitors have been used previously in order to improve circuit performance. However, with the interconnect inductance due to wire
More informationCompact Distributed Phase Shifters at X-Band Using BST
Integrated Ferroelectrics, 56: 1087 1095, 2003 Copyright C Taylor & Francis Inc. ISSN: 1058-4587 print/ 1607-8489 online DOI: 10.1080/10584580390259623 Compact Distributed Phase Shifters at X-Band Using
More informationGood Performance RF-MEMS SP2T Switches in CPW Configuration for Space Applications
International Journal of Electronics Engineering, 3 (2), 2011, pp. 289 292 Serials Publications, ISSN : 0973-7383 Good Performance RF-MEMS SP2T Switches in CPW Configuration for Space Applications Sarla,
More informationAdvanced High-Density Interconnection Technology
Advanced High-Density Interconnection Technology Osamu Nakao 1 This report introduces Fujikura s all-polyimide IVH (interstitial Via Hole)-multi-layer circuit boards and device-embedding technology. Employing
More informationConvergence Challenges of Photonics with Electronics
Convergence Challenges of Photonics with Electronics Edward Palen, Ph.D., P.E. PalenSolutions - Optoelectronic Packaging Consulting www.palensolutions.com palensolutions@earthlink.net 415-850-8166 October
More informationHigh Rejection BPF for WiMAX Applications from Silicon Integrated Passive Device Technology
High Rejection BPF for WiMAX Applications from Silicon Integrated Passive Device Technology by Kai Liu, Robert C Frye* and Billy Ahn STATS ChipPAC, Inc, Tempe AZ, 85284, USA, *RF Design Consulting, LLC,
More informationCHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER
CHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER As we discussed in chapter 1, silicon photonics has received much attention in the last decade. The main reason is
More informationFigure 1 : Topologies of a capacitive switch The actuation voltage can be expressed as the following :
ABSTRACT This paper outlines the issues related to RF MEMS packaging and low actuation voltage. An original approach is presented concerning the modeling of capacitive contacts using multiphysics simulation
More informationManufacture and Performance of a Z-interconnect HDI Circuit Card Abstract Introduction
Manufacture and Performance of a Z-interconnect HDI Circuit Card Michael Rowlands, Rabindra Das, John Lauffer, Voya Markovich EI (Endicott Interconnect Technologies) 1093 Clark Street, Endicott, NY 13760
More informationHigh Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging
High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging Chunghyun Ryu, Jiwang Lee, Hyein Lee, *Kwangyong Lee, *Taesung Oh, and Joungho Kim Terahertz Interconnection and Package
More informationOptical Bus for Intra and Inter-chip Optical Interconnects
Optical Bus for Intra and Inter-chip Optical Interconnects Xiaolong Wang Omega Optics Inc., Austin, TX Ray T. Chen University of Texas at Austin, Austin, TX Outline Perspective of Optical Backplane Bus
More informationHigh Power RF MEMS Switch Technology
High Power RF MEMS Switch Technology Invited Talk at 2005 SBMO/IEEE MTT-S International Conference on Microwave and Optoelectronics Conference Dr Jia-Sheng Hong Heriot-Watt University Edinburgh U.K. 1
More informationIEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2010 Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2010 Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging Christophe Kopp, St ephane Bernab e, Badhise Ben Bakir,
More informationDesign of Experiments Technique for Microwave / Millimeter Wave. Flip Chip Optimization
Design of Experiments Technique for Microwave / Millimeter Wave Flip Chip Optimization Daniela Staiculescu*, Joy Laskar, Manos Tentzeris School of Electrical and Computer Engineering Packaging Research
More informationEM Design of Broadband RF Multiport Toggle Switches
EM Design of Broadband RF Multiport Toggle Switches W. Simon 1, B. Schauwecker 2, A. Lauer 1, A. Wien 1 and I. Wolff, Fellow IEEE 1 1 IMST GmbH, Carl-Friedrich-Gauss-Str. 2, 47475 Kamp Lintfort, Germany
More informationHigh-efficiency, high-speed VCSELs with deep oxidation layers
Manuscript for Review High-efficiency, high-speed VCSELs with deep oxidation layers Journal: Manuscript ID: Manuscript Type: Date Submitted by the Author: Complete List of Authors: Keywords: Electronics
More informationOptical beam steering using a 2D MEMS scanner
Optical beam steering using a 2D MEMS scanner Yves Pétremand a, Pierre-André Clerc a, Marc Epitaux b, Ralf Hauffe c, Wilfried Noell a and N.F. de Rooij a a Institute of Microtechnology, University of Neuchâtel,
More informationModeling, Design, and Demonstration of 2.5D Glass Interposers for 16-Channel 28 Gbps Signaling Applications
Modeling, Design, and Demonstration of 2.5D Glass Interposers for 16-Channel 28 Gbps Signaling Applications Brett Sawyer, Bruce C. Chou, Saumya Gandhi, Jack Mateosky, Venky Sundaram, and Rao Tummala 3D
More informationChapter 11 Testing, Assembly, and Packaging
Chapter 11 Testing, Assembly, and Packaging Professor Paul K. Chu Testing The finished wafer is put on a holder and aligned for testing under a microscope Each chip on the wafer is inspected by a multiple-point
More informationB. Flip-Chip Technology
B. Flip-Chip Technology B1. Level 1. Introduction to Flip-Chip techniques B1.1 Why flip-chip? In the development of packaging of electronics the aim is to lower cost, increase the packaging density, improve
More informationEM Design of an Isolated Coplanar RF Cross for MEMS Switch Matrix Applications
EM Design of an Isolated Coplanar RF Cross for MEMS Switch Matrix Applications W.Simon 1, A.Lauer 1, B.Schauwecker 2, A.Wien 1 1 IMST GmbH, Carl-Friedrich-Gauss-Str. 2, 47475 Kamp Lintfort, Germany; E-Mail:
More informationTesting of Flexible Metamaterial RF Filters Implemented through Micromachining LCP Substrates. Jonathan Richard Robert Dean Michael Hamilton
Testing of Flexible Metamaterial RF Filters Implemented through Micromachining LCP Substrates Jonathan Richard Robert Dean Michael Hamilton Metamaterials Definition Metamaterials exhibit interesting properties
More informationQUADRI-FOLDED SUBSTRATE INTEGRATED WAVEG- UIDE CAVITY AND ITS MINIATURIZED BANDPASS FILTER APPLICATIONS
Progress In Electromagnetics Research C, Vol. 23, 1 14, 2011 QUADRI-FOLDED SUBSTRATE INTEGRATED WAVEG- UIDE CAVITY AND ITS MINIATURIZED BANDPASS FILTER APPLICATIONS C. A. Zhang, Y. J. Cheng *, and Y. Fan
More informationMicro-nanosystems for electrical metrology and precision instrumentation
Micro-nanosystems for electrical metrology and precision instrumentation A. Bounouh 1, F. Blard 1,2, H. Camon 2, D. Bélières 1, F. Ziadé 1 1 LNE 29 avenue Roger Hennequin, 78197 Trappes, France, alexandre.bounouh@lne.fr
More informationA Broadband GCPW to Stripline Vertical Transition in LTCC
Progress In Electromagnetics Research Letters, Vol. 60, 17 21, 2016 A Broadband GCPW to Stripline Vertical Transition in LTCC Bo Zhang 1, *,DongLi 1, Weihong Liu 1,andLinDu 2 Abstract Vertical transition
More informationThrough Glass Via (TGV) Technology for RF Applications
Through Glass Via (TGV) Technology for RF Applications C. H. Yun 1, S. Kuramochi 2, and A. B. Shorey 3 1 Qualcomm Technologies, Inc. 5775 Morehouse Dr., San Diego, California 92121, USA Ph: +1-858-651-5449,
More informationHybrid Integration Technology of Silicon Optical Waveguide and Electronic Circuit
Hybrid Integration Technology of Silicon Optical Waveguide and Electronic Circuit Daisuke Shimura Kyoko Kotani Hiroyuki Takahashi Hideaki Okayama Hiroki Yaegashi Due to the proliferation of broadband services
More informationCapabilities of Flip Chip Defects Inspection Method by Using Laser Techniques
Capabilities of Flip Chip Defects Inspection Method by Using Laser Techniques Sheng Liu and I. Charles Ume* School of Mechanical Engineering Georgia Institute of Technology Atlanta, Georgia 3332 (44) 894-7411(P)
More informationSilicon Light Machines Patents
820 Kifer Road, Sunnyvale, CA 94086 Tel. 408-240-4700 Fax 408-456-0708 www.siliconlight.com Silicon Light Machines Patents USPTO No. US 5,808,797 US 5,841,579 US 5,798,743 US 5,661,592 US 5,629,801 US
More informationAnalysis signal transitions characteristics of BGA-via multi-chip module Baolin Zhou1,a, Dejian Zhou1,b
5th International Conference on Computer Sciences and Automation Engineering (ICCSAE 2015) Analysis signal transitions characteristics of BGA-via multi-chip module Baolin Zhou1,a, Dejian Zhou1,b 1 Electromechanical
More informationThis writeup is adapted from Fall 2002, final project report for by Robert Winsor.
Optical Waveguides in Andreas G. Andreou This writeup is adapted from Fall 2002, final project report for 520.773 by Robert Winsor. September, 2003 ABSTRACT This lab course is intended to give students
More informationAdvances in CO 2 -Laser Drilling of Glass Substrates
Available online at www.sciencedirect.com Physics Procedia 39 (2012 ) 548 555 LANE 2012 Advances in CO 2 -Laser Drilling of Glass Substrates Lars Brusberg,a, Marco Queisser b, Clemens Gentsch b, Henning
More information(12) Patent Application Publication (10) Pub. No.: US 2003/ A1
US 20030091084A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2003/0091084A1 Sun et al. (43) Pub. Date: May 15, 2003 (54) INTEGRATION OF VCSEL ARRAY AND Publication Classification
More informationCHAPTER 11: Testing, Assembly, and Packaging
Chapter 11 1 CHAPTER 11: Testing, Assembly, and Packaging The previous chapters focus on the fabrication of devices in silicon or the frontend technology. Hundreds of chips can be built on a single wafer,
More informationCOMPACT PLANAR MICROSTRIP CROSSOVER FOR BEAMFORMING NETWORKS
Progress In Electromagnetics Research C, Vol. 33, 123 132, 2012 COMPACT PLANAR MICROSTRIP CROSSOVER FOR BEAMFORMING NETWORKS B. Henin * and A. Abbosh School of ITEE, The University of Queensland, QLD 4072,
More informationThe Effects of PCB Fabrication on High-Frequency Electrical Performance
The Effects of PCB Fabrication on High-Frequency Electrical Performance John Coonrod, Rogers Corporation Advanced Circuit Materials Division Achieving optimum high-frequency printed-circuit-board (PCB)
More informationIST IP NOBEL "Next generation Optical network for Broadband European Leadership"
DBR Tunable Lasers A variation of the DFB laser is the distributed Bragg reflector (DBR) laser. It operates in a similar manner except that the grating, instead of being etched into the gain medium, is
More informationHybrid vertical-cavity laser integration on silicon
Invited Paper Hybrid vertical-cavity laser integration on Emanuel P. Haglund* a, Sulakshna Kumari b,c, Johan S. Gustavsson a, Erik Haglund a, Gunther Roelkens b,c, Roel G. Baets b,c, and Anders Larsson
More informationINF 5490 RF MEMS. LN12: RF MEMS inductors. Spring 2011, Oddvar Søråsen Department of informatics, UoO
INF 5490 RF MEMS LN12: RF MEMS inductors Spring 2011, Oddvar Søråsen Department of informatics, UoO 1 Today s lecture What is an inductor? MEMS -implemented inductors Modeling Different types of RF MEMS
More informationMICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation
West Coast Luncheon January 15, 2014. PROMEX PROMEX INDUSTRIES INC. MICROELECTRONICS ASSSEMBLY TECHNOLOGIES The QFN Platform as a Chip Packaging Foundation 3075 Oakmead Village Drive Santa Clara CA Ɩ 95051
More informationMEMS in ECE at CMU. Gary K. Fedder
MEMS in ECE at CMU Gary K. Fedder Department of Electrical and Computer Engineering and The Robotics Institute Carnegie Mellon University Pittsburgh, PA 15213-3890 fedder@ece.cmu.edu http://www.ece.cmu.edu/~mems
More informationIndex. Cambridge University Press Silicon Photonics Design Lukas Chrostowski and Michael Hochberg. Index.
absorption, 69 active tuning, 234 alignment, 394 396 apodization, 164 applications, 7 automated optical probe station, 389 397 avalanche detector, 268 back reflection, 164 band structures, 30 bandwidth
More informationREVISION #25, 12/12/2012
HYPRES NIOBIUM INTEGRATED CIRCUIT FABRICATION PROCESS #03-10-45 DESIGN RULES REVISION #25, 12/12/2012 Direct all inquiries, questions, comments and suggestions concerning these design rules and/or HYPRES
More informationA RECONFIGURABLE HYBRID COUPLER CIRCUIT FOR AGILE POLARISATION ANTENNA
A RECONFIGURABLE HYBRID COUPLER CIRCUIT FOR AGILE POLARISATION ANTENNA F. Ferrero (1), C. Luxey (1), G. Jacquemod (1), R. Staraj (1), V. Fusco (2) (1) Laboratoire d'electronique, Antennes et Télécommunications
More informationMICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS
MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS Patrick Jaenen, John Slabbekoorn, Andy Miller IMEC Kapeldreef 75 B-3001 Leuven, Belgium millera@imec.be Warren W. Flack, Manish Ranjan, Gareth Kenyon,
More informationA 3.9 ns 8.9 mw 4 4 Silicon Photonic Switch Hybrid-Integrated with CMOS Driver
A 3.9 ns 8.9 mw 4 4 Silicon Photonic Switch Hybrid-Integrated with CMOS Driver A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, M. Yang, F. Doany, S. Assefa, C. Jahnes, J. Kash, Y. Vlasov IBM
More informationDesign of Compact Stacked-Patch Antennas in LTCC multilayer packaging modules for Wireless Applications
Design of Compact Stacked-Patch Antennas in LTCC multilayer packaging modules for Wireless Applications R. L. Li, G. DeJean, K. Lim, M. M. Tentzeris, and J. Laskar School of Electrical and Computer Engineering
More informationA Novel WL-Integrated Low-Insertion-Loss Filter with Suspended High-Q Spiral Inductor and Patterned Ground Shields
Progress In Electromagnetics Research C, Vol. 59, 41 49, 2015 A Novel WL-Integrated Low-Insertion-Loss Filter with Suspended High-Q Spiral Inductor and Patterned Ground Shields Tao Zheng 1, 2, Mei Han
More informationOpportunities and challenges of silicon photonics based System-In-Package
Opportunities and challenges of silicon photonics based System-In-Package ECTC 2014 Panel session : Emerging Technologies and Market Trends of Silicon Photonics Speaker : Stéphane Bernabé (Leti Photonics
More informationLaser Solder Attach for Optoelectronics Packages
1 Laser Solder Attach for Optoelectronics Packages Elke Zakel, Lars Titerle, Thomas Oppert, Ronald G. Blankenhorn* Pac Tech Packaging Technologies GmbH Am Schlangenhorst 15-17, Germany Phone:+ 49 (0) 33
More informationMODIFIED MILLIMETER-WAVE WILKINSON POWER DIVIDER FOR ANTENNA FEEDING NETWORKS
Progress In Electromagnetics Research Letters, Vol. 17, 11 18, 2010 MODIFIED MILLIMETER-WAVE WILKINSON POWER DIVIDER FOR ANTENNA FEEDING NETWORKS F. D. L. Peters, D. Hammou, S. O. Tatu, and T. A. Denidni
More informationMAAP Power Amplifier, 15 W GHz Rev. V1. Features. Functional Schematic. Description. Pin Configuration 2. Ordering Information
Features 15 W Power Amplifier 42 dbm Saturated Pulsed Output Power 17 db Large Signal Gain P SAT >40% Power Added Efficiency Dual Sided Bias Architecture On Chip Bias Circuit 100% On-Wafer DC, RF and Output
More informationIntegration Techniques for MMICs and Chip Devices in LTCC Multichip Modules for Radio Frequencies
Integration Techniques for MMICs and Chip Devices in LTCC Multichip Modules for Radio Frequencies R. Kulke *, W. Simon *, M. Rittweger *, I. Wolff *, S. Baker +, R. Powell + and M. Harrison + * Institute
More informationA Low-cost Through Via Interconnection for ISM WLP
A Low-cost Through Via Interconnection for ISM WLP Jingli Yuan, Won-Kyu Jeung, Chang-Hyun Lim, Seung-Wook Park, Young-Do Kweon, Sung Yi To cite this version: Jingli Yuan, Won-Kyu Jeung, Chang-Hyun Lim,
More informationThe Effects of PCB Fabrication on High-Frequency Electrical Performance
As originally published in the IPC APEX EXPO Conference Proceedings. The Effects of PCB Fabrication on High-Frequency Electrical Performance John Coonrod, Rogers Corporation Advanced Circuit Materials
More informationLong-wavelength VCSELs ready to benefit 40/100-GbE modules
Long-wavelength VCSELs ready to benefit 40/100-GbE modules Process technology advances now enable long-wavelength VCSELs to demonstrate the reliability needed to fulfill their promise for high-speed module
More informationPlanar Transmission Line Technologies
Planar Transmission Line Technologies CMB Polarization Technology Workshop NIST/Boulder Edward J. Wollack Observational Cosmology Laboratory NASA Goddard Space Flight Center Greenbelt, Maryland Overview
More informationStudy of a Miniature Air Bearing Linear Stage System
Materials Science Forum Vols. 55-57 (26) pp. 13-18 online at http://www.scientific.net (26) Trans Tech Publications, Switzerland Study of a Miniature Air Bearing Linear Stage System K. C. Fan 1, a, R.
More informationMICROSTRIP PHASE INVERTER USING INTERDIGI- TAL STRIP LINES AND DEFECTED GROUND
Progress In Electromagnetics Research Letters, Vol. 29, 167 173, 212 MICROSTRIP PHASE INVERTER USING INTERDIGI- TAL STRIP LINES AND DEFECTED GROUND X.-C. Zhang 1, 2, *, C.-H. Liang 1, and J.-W. Xie 2 1
More informationWafer-level Vacuum Packaged X and Y axis Gyroscope Using the Extended SBM Process for Ubiquitous Robot applications
Proceedings of the 17th World Congress The International Federation of Automatic Control Wafer-level Vacuum Packaged X and Y axis Gyroscope Using the Extended SBM Process for Ubiquitous Robot applications
More informationMicro-sensors - what happens when you make "classical" devices "small": MEMS devices and integrated bolometric IR detectors
Micro-sensors - what happens when you make "classical" devices "small": MEMS devices and integrated bolometric IR detectors Dean P. Neikirk 1 MURI bio-ir sensors kick-off 6/16/98 Where are the targets
More informationElectromagnetic Bandgap Design for Power Distribution Network Noise Isolation in the Glass Interposer
2016 IEEE 66th Electronic Components and Technology Conference Electromagnetic Bandgap Design for Power Distribution Network Noise Isolation in the Glass Interposer Youngwoo Kim, Jinwook Song, Subin Kim
More informationDEVELOPMENT AND PRODUCTION OF HYBRID CIRCUITS FOR MICROWAVE RADIO LINKS
Electrocomponent Science and Technology 1977, Vol. 4, pp. 79-83 (C)Gordon and Breach Science Publishers Ltd., 1977 Printed in Great Britain DEVELOPMENT AND PRODUCTION OF HYBRID CIRCUITS FOR MICROWAVE RADIO
More informationStreamlined Design of SiGe Based Power Amplifiers
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 13, Number 1, 2010, 22 32 Streamlined Design of SiGe Based Power Amplifiers Mladen BOŽANIĆ1, Saurabh SINHA 1, Alexandru MÜLLER2 1 Department
More informationSignal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
More informationOn-Chip Passive Devices Embedded in Wafer-Level Package
On-Chip Passive Devices Embedded in Wafer-Level Package Kazuya Masu 1, Kenichi Okada 1, Kazuhisa Itoi 2, Masakazu Sato 2, Takuya Aizawa 2 and Tatsuya Ito 2 On-chip high-q spiral and solenoid inductors
More informationHigh-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors
High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors Veerendra Dhyani 1, and Samaresh Das 1* 1 Centre for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi-110016,
More informationMICROBUMP CREATION SYSTEM FOR ADVANCED PACKAGING APPLICATIONS
MICROBUMP CREATION SYSTEM FOR ADVANCED PACKAGING APPLICATIONS Andrew Ahr, EKC Technology, & Chester E. Balut, DuPont Electronic Technologies Alan Huffman, RTI International Abstract Today, the electronics
More information200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC.
C M P C h a r a c t e r I z a t I o n S o l u t I o n s 200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC. 2920 Scott Blvd., Santa Clara, CA 95054 Tel: 408-919-0094,
More informationLicense to Speed: Extreme Bandwidth Packaging
License to Speed: Extreme Bandwidth Packaging Sean S. Cahill VP, Technology BridgeWave Communications Santa Clara, California, USA BridgeWave Communications Specializing in 60-90 GHz Providing a wireless
More informationThe Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications.
The Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications May 8, 2007 Abstract: The challenge to integrate high-end, build-up organic packaging
More informationA 6 : 1 UNEQUAL WILKINSON POWER DIVIDER WITH EBG CPW
Progress In Electromagnetics Research Letters, Vol. 8, 151 159, 2009 A 6 : 1 UNEQUAL WILKINSON POWER DIVIDER WITH EBG CPW C.-P. Chang, C.-C. Su, S.-H. Hung, and Y.-H. Wang Institute of Microelectronics,
More informationBroadband Circular Polarized Antenna Loaded with AMC Structure
Progress In Electromagnetics Research Letters, Vol. 76, 113 119, 2018 Broadband Circular Polarized Antenna Loaded with AMC Structure Yi Ren, Xiaofei Guo *,andchaoyili Abstract In this paper, a novel broadband
More informationResearch Article Compact and Wideband Parallel-Strip 180 Hybrid Coupler with Arbitrary Power Division Ratios
Microwave Science and Technology Volume 13, Article ID 56734, 1 pages http://dx.doi.org/1.1155/13/56734 Research Article Compact and Wideband Parallel-Strip 18 Hybrid Coupler with Arbitrary Power Division
More informationWaveguide-Mounted RF MEMS for Tunable W-band Analog Type Phase Shifter
Waveguide-Mounted RF MEMS for Tunable W-band Analog Type Phase Shifter D. PSYCHOGIOU 1, J. HESSELBARTH 1, Y. LI 2, S. KÜHNE 2, C. HIEROLD 2 1 Laboratory for Electromagnetic Fields and Microwave Electronics
More informationMEMS BASED QUARTZ OSCILLATORS and FILTERS for on-chip INTEGRATION
MEMS BASED QUARTZ OSCILLATORS and FILTERS for on-chip INTEGRATION R. L. Kubena, F. P. Stratton, D. T. Chang, R. J. Joyce, and T. Y. Hsu Sensors and Materials Laboratory, HRL Laboratories, LLC Malibu, CA
More information