Chapter12. Chip Assembly. Figure 12.1: Starting schematic showing the three connected modules
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1 Chapter12 Chip Assembly Figure 12.1: Starting schematic showing the three connected modules
2 236 CHAPTER 12: Chip Assembly Figure 12.2: The Gen From Source dialog box
3 237 Figure 12.3: Initial layout before module and I/O placement
4 238 CHAPTER 12: Chip Assembly Figure 12.4: A placement of modules and IO pins with unrouted nets turned on
5 239 Figure 12.5: Layout showing placement and power routing before routing
6 240 CHAPTER 12: Chip Assembly Figure 12.6: Export to Router dialog box
7 241 Figure 12.7: Initial ccar window
8 242 CHAPTER 12: Chip Assembly Figure 12.8: Layer configuration dialog box
9 243 Figure 12.9: Routing cost factor dialog box
10 244 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.10: Final routed circuit (shown in Virtuoso window)
11 245 (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.11: Symbol for the Three Blocks example core
12 246 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.12: Pad frame with signal wires
13 247 Figure 12.13: Pad frame with signal wires (zoomed view) Figure 12.14: Frame and core components connected together
14 248 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.15: pad in cell with clk and clk i connections (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.16: Expanded pad in cell with clk and clk i connections
15 249 (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.17: Detail of clk i connection (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.18: Expanded detail of clk i connection
16 250 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.19: Frame and core placed in Virtuoso-XL
17 251 Figure 12.20: Frame and core placed in Virtuoso-XL with vdd and gnd routing completed
18 252 CHAPTER 12: Chip Assembly Figure 12.21: Frame and core before routing in ccar
19 253 Figure 12.22: Frame and core after routing in Virtuoso
20 254 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.23: Final wholechip chip with extra rectangles of poly, metal1, and metal2 to meet minimum density requirements
21 255 # Layer map for converting from cadence to GDS format # (SCMOS SCN3M_SUBM processes through MOSIS) # Some of these layers are unlikely to be used... # Erik Brunvand, University of Utah # # Cadence layer Cadence layer purpose GDSII layer # nwell drawing 42 0 pwell drawing 41 0 # note that all three active layers map to GDS layer 43 active drawing 43 0 nactive drawing 43 0 pactive drawing 43 0 nselect drawing 45 0 pselect drawing 44 0 poly drawing 46 0 poly pin 46 0 elec drawing 56 0 metal1 drawing 49 0 metal1 pin 49 0 metal2 drawing 51 0 metal2 pin 51 0 metal3 drawing 62 0 metal3 pin 62 0 # All four contact types go to GDS layer 25 cc drawing 25 0 ca drawing 25 0 cp drawing 25 0 ce drawing 25 0 via drawing 50 0 via2 drawing 61 0 glass drawing 52 0 pad drawing 26 0 highres drawing 34 0 res_id drawing 34 0 Figure 12.24: GDSII map file for SCMOS circuits fabricated through AMI on their C5N CMOS process
22 256 CHAPTER 12: Chip Assembly (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.25: Initial Export Stream dialog box
23 257 (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.26: User-Defined Data dialog box for Export Stream (Copyright c 2006, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.) Figure 12.27: Completion indication from the Export Stream process
24 258 CHAPTER 12: Chip Assembly # Layer map for converting from GDS (SCMOS) to cadence # Some of these layers are unlikely to be used... # # Erik Brunvand, University of Utah # # Cadence layer Cadence layer purpose GDSII layer # nwell drawing 42 0 pwell drawing 41 0 # All layer 43 goes to active, so you can t see the # difference between nactive and pactive any more active drawing 43 0 nselect drawing 45 0 pselect drawing 44 0 poly drawing 46 0 elec drawing 56 0 metal1 drawing 49 0 metal2 drawing 51 0 metal3 drawing 62 0 # All layer 25 goes to cc. cc drawing 25 0 via drawing 50 0 via2 drawing 61 0 glass drawing 52 0 pad drawing 26 0 res_id drawing 34 0 Figure 12.28: Map file for importing GDSII into DFII
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