Stage m. Stage 1. a a. a a

Transcription

1 Low Power Optimiztion Technique or BDD Mpped Finite tte Mchines Mikel Kerttu Per Lindgren Rol Drechsler Mitch Thornton Λ EILAB/Computer Engineering Computer cience Electricl nd Computer Engineering Luleν University otechnology Univeristy o Bremen Mississippi tte University Luleν, weden 859 Bremen, Germny Mississippi tte, M, UA kerttu,plng@sm.luth.se drechsle@inormtik.uni-bremen.de mitch@ece.msstte.edu Abstrct In modern design lows low power spects should be considered s erly s possible to minimize power dissiption in the resulting circuit. A new BDD-bsed design style tht considers switching ctivity optimiztion using temporl correltion inormtion is presented. The technique is developed s n pproximtion method or switching ctivity estimtion. Experimentl results on set o MCNC nd ICA89 benchmrks show the estimted reduction in power dissiption. Introduction The importnce o low power optimiztion is growing due to the incresed use o bttery-powered embedded systems. In order to optimize or low power dissiption sttisticl inormtion bout the behvior o the system cn be exploited. The switching ctivity o circuit node in CMO digitl circuit directly contributes to the overll dynmic power dissiption. Temporl correltion o the occurring input signls cn hve signiicnt eect on the switching ctivity nd hence the power consumption []. Modern design lows should consider these eects rom the very beginning. everl synthesis tools mke use o Binry Decision Digrms (BDDs) [,, ], n eicient dt structure used or solving mny o the problems occurring in VLI CAD. BDDs cn be directly trnsormed into circuits, i ech nodeothe underlying grph is substituted with multiplexer. An pproch or BDD mpping tht lso considers low power spects hs recently be proposed in []. The method combines logic synthesis, re minimiztion nd low power optimiztion together with mpping in single pss. This pproch surpsses the need or circuit extrction nd bck nnottion common to trditionl synthesis methods. However, the ctivity estimtion method used lcks the bility to exploit temporl correltion inormtion. This cn severely ect optimiztion or low power in cses where strong temporl correltion o input signls is present. The problem o switching ctivity minimiztion using temporl correltion inormtion is ddressed in this work. A novel BDD-bsed pproximtion method is described nd it is shown how itcnbeintegrted with the pproch in[]. The power dissiption estimte or mpped BDD node is Λ This work ws supported in prt by the NF under grnts CCR- 89 nd CCR-97 bsed on its switching ctivity nd its nout (corresponding to the cpcitive lod). The resulting circuit is relized by mpping BDD nodes to multiplexer circuits implemented using CMO trnsmission gtes nd sttic inverters. imilr BDD mpping methods bsed on Pss Trnsistor Logic (PTL)circuits [5, ] cn lso be used. The proposed switching ctivity estimtion method hs been vlidted by trnsistor level simultions, showing tht the power dissiption due to switching is dominted by the switching o the multiplexer outputs nd (s the model used here ssumes) the contribution rom internl switching in the multiplexers cn be neglected. To be ble to clculte the power dissiption the cpcitive lod o ll nodes is lso estimted. This problem is hndled by using the inherent structure o BDD mpped circuits. This llows or devising computtionlly eicient cost unction or low power optimiztion. The synthesis technique utilizes sttisticl properties o the primry inputs tht cn be obtined by unctionl simultion. An nlytic method or extrcting sttisticl properties or next stte signls o circuits modeled s FMs is described. In this wy, the need or computtionlly expnsive gte level simultion is voided nd the signl sttistics re utilized or low power synthesis. witching Activity Estimtion In this section n introduction to signl switching ctivity estimtion is given. (For more detils see [].) In the ollowing it is ssumed tht the input signls re mutully independent (sptilly uncorrelted) nd tht the signls cn be modeled s trict-ense ttionry () nd men-ergodic with zero dely []. Tht is, ll switching is crried out simultneously nd tht signl probbility nd switching ctivity do not vry over time. P () denotes the probbility o being (the output probbility o). () denotes the ctivity or (the probbility o chnging vlue rom one cycle to the next). In order to devise n improved low power synthesis method or BDD-mpped circuits n ccurte nd computtionlly eicient switching ctivity estimtion method is needed tht is ble to utilize temporl correltion. To void the high computtionl complexity o n exct method, it is ssumed tht there is no sptil correltion between the hnnon coctors o the unction o interest. The pproximtion technique provides the exct result or the cse where the coctors re sptilly uncorrelted. In the cse where coctors re positively

2 correlted n overestimte is obtined since top vrible switching is less prone to cuse true switching o the node's output. The opposite holds or negtively correlted coctors. This observtion llows or the ppliction o Theorem. rom []. The ormul in Eqution cn then derived using the multiplexer-bsed circuit model. () = (P ( )+P ( ) P ( )P ( )) ( ( )+ ( ) ( ) ( )) ( () + () () ()) ( ( )+ ( ) ( ) ( )) (v)( ( ))( ( )) ( P (v)) (v) = + (v) ( )( (v))( ( )) P (v) (v) = + (v) ( )( (v))( ( )) + (v) ()( ()) + (v) ()( ()) + ( ) ( )( (v)) + (v) () () () In Eqution, v is the input vrible, is the low coctor, nd is the high coctor. This ormul is used recursively in bottom-up pproch nd clcultes the ctivity or ech node in the BDD. Low Power ynthesis. BDD Mpped Circuits A BDD cn be directly mpped to multiplexer-bsed circuit s described in [], to timed" circuit s described in [9] or to pss-trnsistor" bsed circuit s described in [, 5, ]. In ll cses, the resulting circuit cn be considered to be one tht is obtined by replcing BDD vertices with smll sub-circuits nd BDD edges with wires. It is known tht the digrm size (nd thereore the circuit complexity) is sensitive tothe ordering o the unction vribles. It my vry rom liner to exponentil under dierent orderings or some unctions. Both exct nd heuristic methods hve been developed to tckle this problem. However, in this pper we re not only concerned with the complexity o the circuit resulting rom BDD, but to n even greter extent, the power dissiption. A method or low power synthesis o BDD mpped circuits ws irst introduced in []. The power dissiption o ech node ws computed by the estimted switching ctivity nd the node's nout. The vrible order o the underlying BDD ws shown to inluence not only the re (number o nodes) but lso the internl switching ctivity. An optimiztion lgorithm bsed on locl vrible exchnge (siting) ws proposed. ince the switching ctivity estimte, nd thereore the cost unction, could be implemented solely by locl opertions on the digrm, the method ws shown to be computtionlly eective. However, the estimtion technique did not consider ny temporl signl correltion. The technique cn lso be used with BDDs using complemented edges. The use o complemented edges hs shown both to reduce BDD complexity nd improve perormnce o opertions, [, ]. The sttements bove pply or BDDs using complemented edges by mking the ollowing observtions:. The output probbility P [] o is equl to P [].. The switching ctivity [] o is equl to []. These properties re used to compute locl switching probbilities during vrible exchnge opertions on BDDs with complemented edges.. Power Dissiption Modeling A cost model bsed on the totl circuit switching ctivity under given set o dependent vrible output probbilities is deined. The dependent vribles re denoted s support vribles. We ttempt to minimize the sum o ll internl switching ctivities t ech BDD vertex. The pproch then mps ech BDD node into multiplexer-bsed circuit s shown in Figure. The number o stges o ctive buers is determined by thenout o ech BDD node which is equivlent to the number o BDD edges pointing to the node. tge tge VDD () V tge m tge VDD (b) V Figure : BDD node mpping into multiplexer circuits The power dissiption or the mpped node n is estimted using the reltionship in Eqution. PD n = (n) Λ driver( nout(n)) + lekge(n) () Eqution ws vlidted by conducting trnsistor level simultions using models rom commercilly vilble CMO process. The results show tht the power dissiption o externl switching (driving the nout lod cpcitnce) domintes over the internl switching in the multiplexer by ctor o over to under unity lod ( single nout). Thus, the eect o internl switching cn be disregrded. Power switch v, =, = 887 switch v,, (=stble) v=, switch, = 88 v=, =,switch Cpcitive lod nd lekge prmeters re strongly process dependent. In the ollowing, lekge current is ignored

3 nd driver power dissiption is ssumed to be liner with the nout (cpcitive lod). Any prsitic cpcitnces due to routing re lso ignored. The power dissiption rom the buering o input signls re not considered in this model, however this could be included or better ccurcy.. Approximtion Chrcteristics The switching ctivity estimtion method described in Eqution is nlyzed urther to show vrious properties nd how it cn be pplied to low power synthesis or BDD mpped circuits. The totl power dissiption o the mpped circuit is computed s: PD tot = X 8n (n) driver( nout(n)) + lekge(n) () Consider the XOR unction = x Φ x given the input probbilities P (x ) = =;P(x ) = = nd the switching ctivities (x ) = =;(x ) = = s shown in Figure. The ollowing tble shows the estimted switching ctivity or ech BDD node,,nd nd the totl estimted power dissiption Power. As shown in the tble, the technique lbeled Probbilistic leds to n underestimtion, while the proposed multiplexer-bsed pproximtion (MUX Approx.) comes closer to the exct result. x x () x x Figure : Vrible wp () ( ) ( ) Power Over Est. [] ο : ο :75 ο :75 :9 Exct Est. [] ο :7 ο :75 ο :75 :7 Probbilistic [] :5 :5 :5 :5 MUX Approx. :58 :75 :75 :8 When the BDD vrible order is chnged s shown in Figure (b), the switching ctivities re swpped nd the overll power dissiption or the exct method is reduced to. Also the other pproximtion methods indicte reduction s shown in the ollowing tble (except or the Probbilistic pproch which is unble to utilize the signl ctivity inormtion). () ( ) ( ) Power Over Est. [] ο : ο :7 ο :7 :75 Exct Est. [] ο :7 ο :7 ο :7 Probbilistic [] :5 :5 :5 :5 MUX Approx. :5 :7 :7 :88 (b) D min() computed sw [ totl] or ech vrible sit to position minimizing D sw [ totl] g repet until no urther improvement g Figure : Minimiztion o Power Dissiption D sit(upper, lower) D sw [ totl] -=(D sw [ upper] + D sw [ lower] +D sw [ below]) re remove edges to(upper,lower) perorm locl vrible exchnge re dd edges to(upper,lower) 5 D sw [ totl] +=(D sw [ upper] + D sw [ lower] +D sw [ below]) g Figure : Updting Power Dissiption During iting The switching estimte in the tble lbeled Probbilistic is computed solely by locl opertions on the BDD. However, the pproximtion technique lbeled MUX Approx. tht is proposed here lso considers the pproximted switching ctivity o ech node's successors so tht the locl condition no longer holds. This implies tht ter locl vrible exchnge, switching ctivity estimtes need to be propgted towrd preceding levels in the digrm. While this leds to more complexity in the switching ctivity estimtion lgorithm, CPU times re resonble or the set o benchmrk unctions used in the experiments.. Heuristic Minimiztion Algorithm The proposed heuristic minimiztion lgorithm itertively seeks vrible order tht reduces the mpped circuits' switching ctivity weighted by the n-out cost or ech node. This procedure is outlined in psuedocode in Figure. The siting nd re-clcultion o output probbilities nd switching ctivities is perormed solely through locl opertions on the BDD representtion. The totl estimted power dissiption due to switching (D sw [ totl]) cn lso be updted by locl opertions on the two levels sited (upper nd lower) nd nodes connecting to the sited levels (below). By mintining reerence counters (i.e., the number o incoming edges) or ech node, the eect o nout chnges or nodes below in the digrm cn be hndled. Figure shows how the totl switching ctivity is updted during siting. In line, the contribution o the two levels to be sited (D sw [ upper]+d sw [ lower]) nd the contribution o nouts rom connecting nodes (D sw [ below]) is subtrcted. The number o reerences or connecting nodes re updted (line ) beore pplying the siting (line ). Ater the vrible exchnge is perormed, the reerence counters o the connecting nodes (line ) is updted nd the totl estimted power dissiption in line 5 is computed. Due to the vrible exchnge, switching ctivities nd reerence counters my chnge thereby lso chnging the estimted power dissiption D sw [ totl]. Exmple Figure 5 () shows portion o BDD beore siting. The number t ech node denotes the number o incoming edges (the nout in multiplexer-bsed mpping).

4 Beore siting the nout chnges o the lower level in the BDD shown in Figure 5(b) need tobe determined. Note tht only nodes connecting to the upper" nd lower" levels re updted. Ater siting is perormed, the new n-out vlues (reerence counters) o the connecting nodes re computed s illustrted infigure 5 (c). upper b b b lower c below c c Figure : FM sttes e () d e (b) d 5 e (c) d C C C C N N N N Figure 5: Reerence Count Updte During iting FM Anlysis The optimiztion lgorithm described here utilizes the sttisticl inormtion o the input signls. The bility to gther this inormtion is essentil or optimizing or lowpower. The signl properties or the next stte vector re deined rom the FM trnsition reltion together with the properties o the primry input signls. In this section method to extrct this inormtion by modeling the FM behvior s Mrkov chin [8] is described. There re severl pproches or eicient FM spnning []. In this work the spnning unction is implemented in strightorwrd wy by depth-irst recursive lgorithm, which lso clcultes the trnsition probbility mtrix represented by n Algebric Decision Digrm ADD in the sme pss. In [7] nd [8] ADDs were used to represent the trnsition probbility mtrix nd the stedy stte probbilities were clculted in n eicient wy. The clcultions described here were implemented using ADDs in n itertive mnner s described in the ollowing.. pn FM ttes The BDD representing the next stte unctions re used to spn the FM. trting rom the reset stte ech possible new stte is recursively visited (depth irst) until n lredy visited stte is reched. During the recursion, trnsition probbility mtrix is constructed. This usully sprse mtrix is eiciently represented by n ADD. The mtrix is ddressed with the current stte s the columns nd the next stte s the rows. The vlue in echentry in the mtrix (corresponding to n ADD le) represents the probbility o trnsition rom current stte to next stte. Exmple When the trnsition probbilities re clculted the mtrix strts empty nd new entries re dded during the recursion. We ssume tht the probbility tht input signl I is t logic- vlue is / (P(I)=/). There istrnsition rom stte to stte nd the probbility o P(I) is dded to row nd column. C C C C N N / N N Finlly ter ll rechble sttes re ound, the complete mtrix is represented. C C C C N / / / N / / N / N. Clcultion o tte Probbilities The ADD obtined by spnning the FM is used to clculte the stedy stte probbilities or ech stte. The FM is viewed s Mrkov chin [8, 7] nd is used in the clcultion o the stte probbilities. The ADD is multiplied with n initil stte probbility vector. Eqution describes this opertion mthemticlly. Aμx =μx () A is the mtrix represented by the ADD, μx nd μx re the stedy stte probbility vectors ter the itertions. The itertion termintes when μx nd μx re within the speciied tolernce rom ech other. The resulting μx contins the resulting stedy stte probbility vector. Exmple The stte probbility vector is initilized such tht ech stte entry hs the vlue nr rechblesttes except or the unrechble stte entries, which hve the vlue. = = = = = = 7 5 = = 7 = 5= = = = 7 5 (5)

5 = = = = = = 7 5 = =5 = 7 5= = =5 = The stedy stte probbilities(p )re shown below: P ([ : ] = ) = P () = = P ([ : ] = ) = P () = =5 P ([ : ] = ) = P () = = P ([ : ] = ) = P () =. Extrcting ignl ttistics 7 5 () The trnsition probbility mtrix nd the stedy stte probbility vector cn be used to clculte the bit probbility nd the switching ctivity o the next stte bits. This is ccomplished using the ADD nd eqution 8. (8i)P (N[i : i]) = X 8[N :]l[i:i]= (7) P ([N : ]) (8) To clculte the ctivity or ech bit, the ADD with the stte trnsition probbilities nd the stedy stte probbilities clculted erlier re used. P (n) denotes the stedy stte probbility or stte n, n[i : i] isthei th bit o vector n, A is the mtrix contining the stte trnsition probbilities (A[N k ][C n ] = P (N k jc n )), nd (N[i : i]) is the ctivity or the next stte bit i nd is given by the ormul in Eqution 9. (8i)(N[i : i]) = X 8n P (n) X 8kl(k[i:i]=n[i:i]) 5 Experimentl Results P (N k jc n ) (9) Benchmrk circuits were synthesized using the low power optimiztions described here nd lso or optimizing with respect to re minimiztion. As compred to the previous pproch in[], urther power reductions were obtined since this method incorportes the use o temporl signl correltions. As shown in Tble the verge power estimte reduction or the synthesis method described here is % s compred to the re optimized circuit. This results were obtined ssuming lrge ctivity devition (P = :5 nd lternting i =:; :9; :;:::). Using the sme ssumptions with the method in [] resulted in power reduction o only 8.% compred to the re optimizer. Furthermore we hve nlyzed the inite stte mchines s described in ection on set o ICA89 benchmrks nd extrcted sttisticl inormtion s in in ection. nd used this inormtion within the synthesis tool. As shown in Tble the results indicte n verge power estimte reduction o % using the new method proposed here compred to the re optimized method. The power estimte reductions rnge rom % to 95%, The mjority o the tests show signiicnt power estimte reduction or the FM optimized circuits compred with the re optimized ones. The results lso show tht the power optimized circuits hve n incresed re o 5% on verge over the re optimized circuit. In two cses the power optimizer synthesized smller circuits thn the re optimizer. This is due to the heuristic lgorithm tht the re optimizer utilizes, which my cuse it to get stuck in locl minimum. Conclusions nd Future Work A synthesis method tht reduces the dynmic power dissipted in CMO circuit obtined using BDD-mpping technique ws presented. The technique utilizes switching ctivity estimte tht is bsed on the structure o the subcircuit used to represent ech BDD node. Furthermore, temporl correltion sttistics were extrcted rom the trnsition unctions o inite stte mchine nd lso included in the low power optimiztion technique. Experimentl results show nverge decrese in power dissiption o % s compred to circuits synthesized with re minimiztion. In the uture this technique will be extended to tke dvntge o ny sptil correltion mong the input signls. Also, it is plnned to consider prsitic cpcitnces rom routing nd to incorporte power estimtes due to sttic lekge currents nd input signl buers. Reerences [].B. Akers. Binry decision digrms. IEEE Trns. on Comp., 7:59 5, 978. [] V. Bertcco,. Minto, P. Verpletse, L. Benini, nd G. De Micheli. Decision digrms nd pss trnsistor logic synthesis. In Int'l Workshop on Logic ynth., 997. [] K.. Brce, R.L. Rudell, nd R.E. Brynt. Eicient implementtion o BDD pckge. In Design Automtion Con., pges 5, 99. [] R.E. Brynt. Grph - bsed lgorithms or Boolen unction mnipultion. IEEE Trns. on Comp., 5(8):77 9, 98. [5] P. Buch, A. Nryn, A.R. Newton, nd A.L. ngiovnni-vincentelli. Logic synthesis or lrge pss trnsistor circuits. In Int'l Con. on CAD, pges 7, 997. [] G. Cbodi, P. Cmurti, nd. Quer. Improving symbolic rechbility nlysis by mens o ctivity proiles. IEEE Trns. on Comp., 9(9):5 75,. [7] G.D. Hchtel, E. Mcii, A. Prdo, nd F. omenzi. Probbilistic nlysis o lrge inite stte mchines. In Design Automtion Con., pges 7 75, 99. [8] G.D. Hchtel, E. Mcii, A. Prdo, nd F. omenzi. Mrkovin nlysis o lrge inite stte mchines. IEEE Trns. on Comp., 5():79 9, 99. [9] L. Lvgno, P. McGeer, A. ldnh, nd A.L. ngiovnni-vincentelli. Timed shnnon circuits: A power-eicient design style nd synthesis tool. In Design Automtion Con., pges 5, 995.

6 Tble : Are Optimized circuits compred with Low Power Optimized circuits Are Optimized Low Power Optimized nme in/out Prob Locl Mux Prob Locl Mux 5xp 7/ dd / pex7 9/ bc / chkn 9/ duke / exp 8/ in 9/ in7 / inc 7/ intb 5/ misex / so / til / vg 5/ xdn 9/ um Tble : ICA89 benchmrks Are opt NonFM opt FM opt Percent Chnge nme ize PD ^ ize PD ^ ize PD ^ ize PD ^ s s s s s s8... s8 9 - s... s s s s s s s

7 [] P. Lindgren, M. Kerttu, M. Thornton, nd R. Drechsler. Low power optimiztion technique or BDD mpped circuits. In AP Design Automtion Con., pges 5,. [] R. Mrculescu D. Mrculescu nd M. Pedrm. Eicient power estimtion or highly correlted input strems. In Design Automtion Con., 995. []. Minto, N. Ishiur, nd. Yjim. hred binry decision digrms with ttributed edges or eicient Boolen unction mnipultion. In Design Automtion Con., pges 5 57, 99. [] K. Roy nd. Prsd. Low-Power CMO VLI Circuit Design. Wiley Interscience,. [] C. choll nd B. Becker. On the genertion o multiplexer circuits or pss trnsistor logic. In Design, Automtion nd Test in Europe,.