Asymmetric Integrated Gate- Commutated Thyristor 5SHY 35L4511

Transcription

1 V DRM = 4500 V I GQM = 3800 A I SM = A V (0) = 1.7 V r = mw V DC-link = 2800 V Asymmetric Integrated Gate- Commutated hyristor Doc. No. 5SYA June 07 High snubberless turn-off rating Optimized for medium frequency (<1 khz) and low turn-off losses High reliability High electromagnetic immunity Simple control interface with status feedback AC or DC supply voltage Contact factory for series connection Blocking Rep. peak off-state voltage V DRM Gate Unit energized 4500 V Permanent DC voltage for 100 FI failure rate of GC V DC-link Reverse voltage V RRM IGC in Ambient cosmic radiation at sea level in open air. Gate Unit energized 2800 V off-state 17 V on-state 10 V Rep. peak off-state current I DRM V D = V DRM, Gate Unit energized 50 ma Mechanical data (see Fig. 11, 12) Mounting force F m kn Pole-piece diameter D p ± 0.1 mm 85 mm Housing thickness H mm Weight m 2.9 kg Surface creepage distance D s Anode to Gate 33 mm Air strike distance D a Anode to Gate 10 mm Length l ± 1.0 mm 439 mm Height h ± 1.0 mm 40 mm Width IGC w ± 1.0 mm 173 mm 1) Maximum rated values indicate limits beyond which damage to the device may occur

2 GC Data On-state (see Fig. 3, 4, 5, 6, 14, 15) Max. average on-state current I (AV)M Half sine wave, C = 85 C, Double side cooled 1420 A Max. RMS on-state current I (RMS) 2240 A Max. peak non-repetitive surge on-state current Limiting load integral Max. peak non-repetitive surge on-state current Limiting load integral Stray inductance between GC and antiparallel diode Critical rate of rise of onstate current I SM t p = 10 ms, j = 125 C, sine wave A after surge: V D = V R = 0 V I 2 t A 2 s I SM t p = 30 ms, j = 125 C, sine wave A after surge: V D = V R = 0 V I 2 t L D di /dt cr Only relevant for applications with antiparallel diode to the IGC For higher di /dt and current lower than 100 A an external retrigger puls is required A 2 s 300 nh 200 A/µs On-state voltage V I = 3300 A, j = 125 C V hreshold voltage V (0) j = 125 C 1.7 V Slope resistance I = A mω r urn-on switching (see Fig. 14, 15) Critical rate of rise of onstate current di /dt cr f = Hz, j = 125 C, V D = 2800 V, I M 3300 A 1000 A/µs urn-on delay time t don V D = 2800 V, j = 125 C 3.5 µs urn-on delay time status t I = 3300 A, di/dt = V D / L i don SF 7 µs feedback L i = 5 µh C CL = 10 µf, L CL = 0.3 µh Rise time t r 1 µs urn-on energy per pulse E on 1.5 J urn-off switching (see Fig. 7, 8, 10, 14, 15) urn-off delay time t doff V D = 2800 V, j = 125 C 7 µs urn off delay time status t V DM V DRM, R S = 0.65 Ω doff SF 7 µs feedback I GQ = 3300 A, L i = 5 µh C CL = 10 µf, L CL = 0.3 µh urn-off energy per pulse J E off Doc. No. 5SYA June 07 page 2 of 9

3 Gate Unit Data Power supply (see Fig. 2, 9, 10, 12, 13) Gate Unit voltage (Connector X1) Min. current needed to power up the Gate Unit V GIN,RMS AC square wave amplitude (15 khz - 100kHz) or DC voltage. No galvanic isolation to power circuit. I GIN Min Rectified average current see application note 5SYA V 2.1 A Gate Unit power consumption P GIN Max 100 W Internal current limitation I GIN Max Rectified average current limited by 8 the Gate Unit A Optical control input/output 2) Min. on-time t on 40 µs Min. off-time t off 40 µs Optical input power P on CS CS: Control signal dbm Optical noise power P off CS SF: Status feedback -45 dbm Optical output power P Valid for 1mm plastic optical fiber on SF dbm (POF) Optical noise power -50 dbm P off SF Pulse width threshold t GLICH Max. pulse width without response 400 ns External retrigger pulse width t retrig ns 2) Do not disconnect or connect fiber optic cables while light is on. Connectors 2) (see Fig. 11, 12, 13) Parameter Symbol Description Gate Unit power connector X1 AMP: MA-156, Part Number ) LWL receiver for command signal CS Agilent, ype HFBR ) LWL transmitter for status feedback SF Agilent, ype HFBR ) 2) Do not disconnect or connect fiber optic cables while light is on. 3) AMP, 4) Agilent echnologies, Visual feedback (see Fig. 13) Parameter Symbol Description Color Gate OFF LED1 "Light" when GC is off (green) Gate ON LED2 "Light" when gate-current is flowing (yellow) Fault LED3 "Light" when not ready / Failure (red) Power supply voltage OK LED4 "Light" when power supply is within specified range (green) Doc. No. 5SYA June 07 page 3 of 9

4 hermal Junction operating temperature vj C Storage temperature range stg C Ambient operational temperature a C hermal resistance junction-to-case of GC R th(j-c) Double side cooled 8.5 K/kW hermal resistance case-toheatsink of GC R th(c-h) Analytical function for transient thermal impedance: Double side cooled 3 K/kW Z th(j-c) (t) = n i= 1 R(1- i e -t/ τ i R i (K/kW) τ i (s) i ) Max. urn-off current for Lifetime operation Fig. 1 ransient thermal impedance (junction-tocase) vs. time (max. values) calculated lifetime of on-board capacitors 20 years with slightly forced air cooling (air velocity > 0.5 m/s) strong air cooling allows for increased ambient temperature Fig. 2 Max. turn-off current vs. frequency for lifetime operation Doc. No. 5SYA June 07 page 4 of 9

5 Max. on-state characteristic model: V 25 = A + B I + C ln( I + 1) + D Valid for i = A I Max. on-state characteristic model: V 125 = A + B I + C ln( I + 1) + D Valid for i = A I A 25 B 25 C 25 D 25 A 125 B 125 C 125 D Fig. 3 GC on-state voltage characteristics Fig. 4 GC on-state voltage characteristics Fig. 5 Surge on-state current vs. pulse length, halfsine wave Fig. 6 Surge on-state current vs. number of pulses, half-sine wave, 10 ms, 50Hz Doc. No. 5SYA June 07 page 5 of 9

6 Fig. 7 GC turn-off energy per pulse vs. turn-off current Fig. 8 Safe Operating Area Fig. 9 Max. Gate Unit input power in chopper mode Fig. 10 Burst capability of Gate Unit Doc. No. 5SYA June 07 page 6 of 9

7 Fig. 11 Outline drawing; all dimensions are in millimeters and represent nominal values unless stated otherwise 1) V GIN (AC or DC+) 2) V GIN (AC or DC+) 3) Cathode 4) V GIN (AC or DC-) 5) V GIN (AC or DC-) Fig. 12 Detail A: pin out of supply connector X1 AS-IGC Gate Unit AS-GC X1 Supply (V GIN ) Internal Supply (No galvanic isolation to power circuit) Anode LED1 LED2 LED3 LED4 urn- On Circuit Gate CS SF Command Signal (Light) Status Feedback (Light) x Rx Logic Monitoring urn- Off Circuit Cathode Fig. 13 Block diagram Doc. No. 5SYA June 07 page 7 of 9

8 urn-on di /dt I M External Retrigger pulse urn-off V DSP V DM V D V D I 0.9 V D I 0.4 I GQ 0.1 V D V D CS CS CS SF SF SF t don SF t retrig t doff SF t don t doff t r t on t off Fig. 14 General current and voltage waveforms with IGC - specific symbols L i L CL L D R s DU VDC C CL L Load Fig. 15 est circuit Doc. No. 5SYA June 07 page 8 of 9

9 Related documents: 5SYA 2031 Applying IGC Gate Units 5SYA 2032 Applying IGCs 5SYA 2036 Recommendations regarding mechanical clamping of Press Pack High Power Semiconductors 5SYA 2046 Failure rates of IGCs due to cosmic rays 5SYA 2048 Field measurements on High Power Press Pack Semiconductors 5SYA 2051 Voltage ratings of high power semiconductors 5SZK 9107 Specification of enviromental class for pressure contact IGCs, OPERAION available on request, please contact factory Please refer to for current version of documents. ABB Switzerland Ltd Doc. No. 5SYA June 07 Semiconductors Fabrikstrasse 3 CH-5600 Lenzburg, Switzerland elephone +41 (0) Fax +41 (0) abbsem@ch.abb.com Internet