SILICON MMIC QUADRATURE MODULATOR

Transcription

1 FEATURES WDE SUPPLY VOLTAGE RANGE: 2.7 ~ 5.5 V BROADBAND OPERATON: MODOUT = MHz, / = DC to 0 MHz NTERNAL 90 PHASE SHFTER POWER SAVE FUNCTON LOW POWER CONSUMPTON: 6 ma 3 V SMALL SSOP 6 PACKAGE TAPE AND REEL PACKAGNG AVALABLE DESCRPTON The Silicon MMC / Modulator is manufactured using the NESAT MMC process. The NESAT process produces transistors with ft approaching 20 GHz. The device was designed for use in Digital Mobile Communications circuits such as 900 MHz Digital Cordless and Cellular Phones, WLAN and PCN/PCS Handset Transmitters. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. SLCON MMC UADRATURE ELECTRCAL CHARACTERSTCS (TA = 25 C, VCC = 3.0 V, VPS. V) FUNCTONAL BLOCK DAGRAM PART NUMBER PACKAGE OUTLNE S6 (SSOP 6) SYMBOLS PARAMETERS AND CONDTONS UNTS MN TYP MAX CC Total Circuit Current (no signal) VPS. V ma VPS.0 V µa 0. 5 PMOD Output Power - Modulator dbm EAK Local Oscillator Leakage dbc mr mage Rejection V/ =.5 V (DC) dbc M3/ / 3rd Order ntermodulation Distortion mvp-p (AC) dbc RLN / LO nput Return Loss db 20 DSCONTNUED Z/ nput mpedance and Port kω 20 TPS(RSE) Power Save Rise Time VPS.0 V to VPS.V µs 2 5 TPS (FALL) Power Save Fall Time VPS. V to VPS.0 V µs 2 5 φ 0 LO California Eastern Laboratories

2 ABSOLUTE MAXMUM RATNGS (TA = 25 C) SYMBOLS PARAMETERS UNTS RATNGS VCC Supply Voltage V 6.0 VPS Enable Voltage for Power Save V 6.0 PD Power Dissipation 2 mw 530 TOP Operating Temperature C to +5 TSTG Storage Temperature C -65 to +50 Notes:. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50x50x.6 mm double copper clad epoxy glass PWB (TA = 5 C). LO Leakage, ; mage Rejection, mr; M3 / (dbc) OUTPUT POWER, LO LEAKAGE, MAGE REJECTON AND / 3rd ORDER NTERMODULATON DSTORTON vs. / NPUT SGNAL MR M3 / / nput Signal, P /N (Vp-p) RECOMMENDED OPERATNG CONDTONS SYMBOLS PARAMETERS UNTS MN TYP MAX VCC Supply Voltage V TOP Operating Temperature C fmodout Modulator Output Frequency MHz flon LO nput Frequency MHz f/n / nput Frequency 2 MHz DC 0 Notes:. PLON = dbm. 2. P/N = 600 mvp-p max. TYPCAL PERFORMANCE CURVES (TA = 25 C, VCC = VPS = 3 V, / DC Offset = / DC Offset =.5 V, / nput Signal = 500 mvp-p (Single-ended), PLON = dbm unless otherwise specified) OUTPUT POWER, LO LEAKAGE, MAGE REJECTON AND / 3rd ORDER NTERMODULATON DSTORTON vs.lo NPUT POWER LO Leakage, ; mage Rejection, mr; M3 / (dbc) MR M3 /O 0 +0 LO nput Power, PLON (dbm) OUTPUT POWER, LO LEAKAGE, MAGE REJECTON AND / 3rd ORDER NTERMODULATON DSTORTON vs. LO NPUT FREUENCY LO Leakage, ; mage Rejection, mr; M3 / (dbc) MR M3 /O LO nput Frequency, flo (MHz) DSCONTNUED

3 PN FUNCTONS Pin No. Symbol Supply Voltage Pin Voltage Description Equivalent Circuit LON 0 2 LON (Bypass) 3 4 VCC/2 *2 5 VCC/2* 2 6 VCC/2* 2 7 VCC/2* 2 2 MODOUT LO input for the phase shifter. This input impedance is internally matched to 50 Ω. Bypass of the LO input.this pin is grounded through an internal capacitor. For a single-ended design this pin should be left open. Connect to ground with minimum inductance. Track length should be kept as short as possible. nput for signal. This input The relationship between the amplitude and the DC bias of the input signal are as follows: * VCC/2 (V) Amp. (mvp-p) nput for signal. This input VCC/2 biased DC signal should be input. nput for signal. This input The relationship between the amplitude and the DC bias of the input signal are as follows: VCC/2 (V) Amp. (mvp-p) Output from the modulator. This is emitter follower output. Connect approx. 5 Ω in series to match to 50 Ω. *: n case / input signals are single ended. / signal inputs can be used either single-ended or differentially with proper terminations. *2: VCC/2 DC bias must be supplied to,,,. nput for signal. This input VCC/2 biased DC signal should be input. 50 Ω DSCONTNUED 2 2

4 PN FUNCTONS Pin No. Symbol Supply Voltage Pin Voltage Description Equivalent Circuit VPS VPS (Power Save) 6 VCC 2.7~5.5 NTERNAL FUNCTONS Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the On/Sleep state with bias as follows: VPS (V) STATE.~5.5 ON 0~.0 SLEEP Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variation. Block Function/Operation Block Diagram 90 Buffer Amplifier Mixer Adder nput signal from LO is sent to a T-type flip-flop through a frequency doubler. The output signal from the T-type F/F is changed to the same frequency as LO input with a quadrature phase shift of 0, 90, 0, or 270. These circuits provide self phase correction for proper quadrature signals. Buffer amplifiers for each phase signal are sent to each mixer. Each signal from the buffer amps is quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to provide excellent image rejection. Output signal from each mixer is added and sent through a final amplifier stage to pin 6 for further off-chip filtering if necessary.. from LOin x 2 2 F / F DSCONTNUED 5 To MODout

5 NTERNAL BLOCK DAGRAM OUTLNE DMENSONS (Units in mm) LO N LO N ORDERNG NFORMATON PART NUMBER -E Note: Embossed Tape, 2 mm wide. APPLCATON CRCUT RX TX SW REG Low-noise Transistor PA VCC V PS (POWER SAVE) MOD OUT UANTTY 2500/Reel. Max VCO + N PLL.44 0.±0. PACKAGE OUTLNE SSOP NEC C05G XXXXX 5.50 Max LEAD CONNECTONS. LON 2. LON nput 5. nput 6. nput 7. nput Max 0.20± ± ± ± MODOUT VPS (Power Save) 6. VCC All dimensions are typical unless specified otherwise. XXX = Lot/Date Code DSCONTNUED UPC06T 0 DEMO PLL 0.9±0.2 EXCLUSVE NORTH AMERCAN AGENT FOR RF, MCROWAVE & OPTOELECTRONC SEMCONDUCTORS CALFORNA EASTERN LABORATORES Headquarters 4590 Patrick Henry Drive Santa Clara, CA (40) Telex FAX (40) Hour Fax-On-Demand: (U.S. and Canada only) nternet: DATA SUBJECT TO CHANGE WTHOUT NOTCE PRNTED N USA ON RECYCLED PAPER -3/97