BIPOLAR ANALOG INTEGRATED CIRCUITS PC2709TB

Transcription

1 DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUITS PC279TB 5 V, SUPER MINIMOLD SILICON MMIC MEDIUM OUTPUT POWER AMPLIFIER DESCRIPTION The PC279TB is asilicon monolithic integrated circuits designed as 1st IF amplifier for DBS tuners. This IC is packaged in super minimold package which is smaller than conventional minimold. The PC279TB has compatible pin connections and performance to PC279T of conventional minimold version. So, in the case of reducing your system size, PC279TB is suitable to replace from PC279T. These IC is manufactured using NEC s 2 GHz ft NESAT III silicon bipolar process. This process uses silicon nitride passivation film and gold electrodes. These materials can protect chip surface from external pollution and prevent corrosion/migration. Thus, this IC has excellent performance, uniformity and reliability. FEATURES High-density surface mounting : -pin super minimold package ( mm) Wideband response : fu = 2.3 GHz db bandwidth Medium output power : PO (sat) = dbm@f =1GHz with external inductor Supply voltage : VCC = 4.5 to 5.5 V Power gain : GP = 23 db = 1 GHz Port impedance : input/output 5 APPLICATIONS 1st IF amplifiers in DBS converters RF stage buffer in DBS tuners, etc. ORDERING INFORMATION (PB-Free) Part Number Package Marking Supplying Form PC279TB-E3-A -pin super minimold C1E Embossed tape 8 mm wide. 1, 2, 3 pins face the perforation side of the tape. Qty 3 kpcs/reel. Remark To order evaluation samples, please contact your local sales office (Part number for sample order: PC279TB-A). Caution Electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Document No. P1253EJ3VDS (3rd edition) Date Published November 2 N CP(K) The mark shows major revised points.

2 PIN CONNECTIONS (Top View) (Bottom View) Pin No. Pin Name 1 INPUT C1E GND 3 GND 4 OUTPUT 5 GND VCC PRODUCT LINE-UP OF 5 V-BIAS SILICON MMIC MEDIUM OUTPUT POWER AMPLIFIER (TA = +25 C, VCC =Vout = 5. V, ZS =ZL = 5 ) Part No. fu (GHz) PO (sat) (dbm) GP (db) NF (db) ICC (ma) Package Marking PC278T PC278TB = 1 GHz 2 -pin minimold -pin super minimold C1D PC279T PC279TB = 1 GHz 25 -pin minimold -pin super minimold C1E PC271T PC271TB =.5 GHz 22 -pin minimold -pin super minimold C1F PC277T PC277TB = 1 GHz 25 -pin minimold -pin super minimold C2L Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. Caution The package size distinguishes between minimold and super minimold. 2 Data Sheet P1253EJ3VDS

3 SYSTEM APPLICATION EXAMPLE EXAMPLE OF DBS CONVERTERS BS Antenna (DBS ODU) Parabola Antenna RF Amp. Mixer IF Amp. To IDU PC279TB Oscillator EXAMPLE OF 9 MHz BAND, 1.5 GHz BAND DIGITAL CELLULAR TELEPHONE RX DEMOD. I Q SW PLL PLL Driver 2 I TX PA F/F PC279TB 9 Q Data Sheet P1253EJ3VDS 3

4 PIN EXPLANATION Pin No. Pin Name Applied Voltage (V) Pin Voltage Function and Applications Internal Equivalent Circuit (V) Note 1 INPUT 1.5 Signal input pin. A internal matching circuit, configured with resistors, enables 5 connection over a wide band. A multi-feedback circuit is designed to cancel the deviations of hfe and resistance. This pin must be coupled to signal source with capacitor for DC cut. 4 OUTPUT Voltage as same Signal output pin. The inductor must be attached between VCC as VCC and output pins to supply current through to the internal output transistors. external inductor IN 1 4 VCC OUT VCC 4.5 to 5.5 Power supply pin, which biases the internal input transistor. This pin should be externally equipped with bypass capacitor to minimize its impedance GND GND GND Ground pin. This pin should be connected to system ground with minimum inductance. Ground pattern on the board should be formed as wide as possible. All the ground pins must be connected together with wide ground pattern to decrease impedance defference. Note Pin voltage is measured at 4 Data Sheet P1253EJ3VDS

5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Ratings Unit Supply Voltage VCC TA = +25 C, Pin 4 and V Total Circuit Current ICC TA = +25 C ma Power Dissipation PD Mounted on double copper clad mm epoxy glass PWB (TA =+85 C) 27 mw Operating Ambient Temperature TA 4 to +85 C Storage Temperature Tstg 55 to +15 C Input Power Pin TA = +25 C +1 dbm RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Remark Supply Voltage VCC V The same voltage should be applied to pin 4 and. Operating Ambient Temperature TA C ELECTRICAL CHARACTERISTICS (TA = +25 C, VCC =Vout = 5. V, ZS =ZL = 5 ) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Circuit Current ICC No input signal ma Power Gain GP f = 1 GHz db Saturated Output Power PO (sat) f = 1 GHz, Pin = dbm dbm Noise Figure NF f = 1 GHz 5..5 db Upper Limit Operating Frequency fu 3 db down below flat gain at f =.1 GHz GHz Isolation ISL f = 1 GHz 2 31 db Input Return Loss RLin f = 1 GHz 7 1 db Output Return Loss RLout f = 1 GHz 7 1 db Gain Flatness GP f =.1 to 1.8 GHz 1. db Data Sheet P1253EJ3VDS 5

6 TEST CIRCUIT VCC 1 pf C3 L 5 IN C1 1 4 C2 5 OUT 1 pf 1 pf 2, 3, 5 COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS EXAMPLE OF ACTURAL APPLICATION COMPONENTS Type Value Type Value Operating Frequency C1 to C2 Bias Tee 1 pf C1 to C3 Chip capacitor 1 pf 1 MHz or higher C3 Capacitor 1 pf L Chip inductor 3 nh 1 MHz or higher L Bias Tee 1 nh 1 nh 1 MHz or higher 1 nh 1. GHz or higher INDUCTOR FOR THE OUTPUT PIN The internal output transistor of this IC consumes 2 ma, to output medium power. To supply current for output transistor, connect an inductor between the VCC pin (pin ) and output pin (pin 4). Select large value inductance, as listed above. The inductor has both DC and AC effects. In terms of DC, the inductor biases the output transistor with minimum voltage drop to output enable high level. In terms of AC, the inductor make output-port impedance higher to get enough gain. In this case, large inductance and Q is suitable. CAPACITORS FOR THE VCC, INPUT, AND OUTPUT PINS Capacitors of 1 pf are recommendable as the bypass capacitor for the VCC pin and the coupling capacitors for the input and output pins. The bypass capacitor connected to the VCC pin is used to minimize ground impedance of VCC pin. So, stable bias can be supplied against VCC fluctuation. The coupling capacitors, connected to the input and output pins, are used to cut the DC and minimize RF serial impedance. Their capacitance are therefore selected as lower impedance against a 5 load. The capacitors thus perform as high pass filters, suppressing low frequencies to DC. To obtain a flat gain from 1 MHz upwards, 1 pf capacitors are used in the test circuit. In the case of under 1 MHz operation, increase the value of coupling capacitor such as 1 pf. Because the coupling capacitors are determined by equation, C = 1/(2 Rfc). Data Sheet P1253EJ3VDS

7 ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD AMP-2 Top View C1E 5 4 Mounting direction IN C L C OUT C VCC COMPONENT LIST Value C 1 pf L 3 nh Notes mm double sided copper clad polyimide board. 2. Back side: GND pattern 3. Solder plated on pattern 4. : Through holes For more information on the use of this IC, refer to the following application note: USAGE AND APPLICATION OF SILICON MEDIUM-POWER HIGH-FREQUENCY AMPLIFIER MMIC (P12152E). Data Sheet P1253EJ3VDS 7

8 TYPICAL CHARACTERISTICS (Unless otherwise specified, TA =+25 C) CIRCUIT CURRENT vs. SUPPLY VOLTAGE 4 No input signal 35 CIRCUIT CURRENT vs. OPERATING AMBIENT TEMPERATURE 4 No input signal 35 Circuit Current ICC (ma) Circuit Current ICC (ma) Supply Voltage VCC (V) Operating Ambient Temperature TA ( C) Noise Figure NF (db) Power Gain GP (db) NOISE FIGURE, POWER GAIN vs. FREQUENCY GP NF VCC = 5.5 V 5.5 V 5. V 4.5 V Power Gain GP (db) POWER GAIN vs. FREQUENCY 4 C TA = +25 C +85 C V Frequency f (GHz) Frequency f (GHz) ISOLATION vs. FREQUENCY INPUT RETURN LOSS, OUTPUT RETURN LOSS vs. FREQUENCY Isolation ISL (db) Input Return Loss RLin (db) Output Return Loss RLout (db) RLin RLout Frequency f (GHz) Frequency f (GHz) 8 Data Sheet P1253EJ3VDS

9 Output Power Pout (dbm) OUTPUT POWER vs. INPUT POWER OUTPUT POWER vs. INPUT POWER f = 1. GHz 5.5 V f = 1. GHz C V TA = 4 C +85 C Output Power Pout (dbm) Input Power Pin (dbm) Input Power Pin (dbm) OUTPUT POWER vs. INPUT POWER +15 f = 2. GHz 5.5 V +1 OUTPUT POWER vs. INPUT POWER Output Power Pout (dbm) V Output Power Pout ( dbm) f =.5 GHz f = 1. GHz f = 2. GHz Saturated Output Power PO(sat) (dbm) Input Power Pin (dbm) SATURATED OUTPUT POWER vs. FREQUENCY 2 18 Pin = dbm V V Frequency f (GHz) Input Power Pin (dbm) 3RD ORDER INTERMODULATION DISTORTION vs. OUTPUT POWER OF EACH TONE f1 = 1. GHz f2 = 1.2 GHz 5 3rd Order Intermodulation Distortion IM3 (dbc) V 5.5 V Output Power of Each Tone PO(each) (dbm) Remark The graphs indicate nominal characteristics. Data Sheet P1253EJ3VDS 9

10 S-PARAMETERS (TA =+25 C, VCC = Vout =5.V) S11-FREQUENCY.1 G 1. G 3. G S22-FREQUENCY 3. G.1 G 2. G 1. G 1 Data Sheet P1253EJ3VDS

11 TYPICAL S-PARAMETER VALUES (TA = +25 C) VCC =Vout = 5. V, ICC = 2 ma Frequency S11 S21 S12 S22 K MHz MAG. ANG. MAG. ANG. MAG. ANG. MAG. ANG Data Sheet P1253EJ3VDS 11

12 PACKAGE DIMENSIONS -PIN SUPER MINIMOLD (UNIT: mm) to MIN. 12 Data Sheet P1253EJ3VDS

13 NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). All the ground pins must be connected together with wide ground pattern to decrease impedance difference. (3) The bypass capacitor should be attached to the VCC pin. (4) The inductor (L) must be attached between VCC and output pins. The inductance value should be determined in accordance with desired frequency. (5) The DC cut capacitor must be attached to input and output pin. RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Infrared Reflow VPS Wave Soldering Soldering Conditions Package peak temperature: 235 C or below Time: 3 seconds or less (at 21 C) Count: 3, Exposure limit: None Note Package peak temperature: 215 C or below Time: 4 seconds or less (at 2 C) Count: 3, Exposure limit: None Note Soldering bath temperature: 2 C or below Time: 1 seconds or less Count: 1, Exposure limit: None Note Recommended Condition Symbol IR35--3 VP15--3 WS--1 Partial Heating Pin temperature: 3 C Time: 3 seconds or less (per side of device) Exposure limit: None Note Note After opening the dry pack, keep it in a place below 25 C and 5% RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C1535E). Data Sheet P1253EJ3VDS 13

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