ONE of the greatest challenges in the design of a

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1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE Characterizing the Effects of the PLL Jitter Due to Substrate Noise in Discrete-Time Delta-Sigma Modulators Payam Heydari, Member, IEEE Abstract This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling 16 modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the 16 modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the 16 modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order 16 modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models. Index Terms 16 modulator, jitter, oversampling datat converter, phase-locked loop (PLL), phase noise, substrate noise. I. INTRODUCTION ONE of the greatest challenges in the design of a system-on-a-chip (SOC) is the need to place sensitive analog circuits and large complex digital signal processing components on the same die. Due to the high-level of interactions between the noisy digital blocks with the noise-sensitive analog portion of the system through various propagation mechanisms it is highly possible that the large-signal switching transients of the digital circuits corrupt the performance of the analog sub-blocks. In an SOC, coupling from digital circuits into analog components mostly propagates through the common substrate, thereby being named as substrate noise. Substrate coupling degrades analog signal integrity in mixed-signal integrated circuits where thousands of digital gates may inject noise into the substrate, especially during clock transitions, introducing hundreds of millivolts of disturbance in the substrate potential [1] [4]. The peak amplitude and pulse-width of substrate noise is multiple orders of magnitude larger than those of device noise sources (e.g, thermal noise and -noise), thereby making substrate noise to be the dominant noise sources that influence the performance mixed analog digital (A/D) integrated circuit. Manuscript received November 12, 2003; revised September 9, This paper was recommended by Associate Editor A. Ushida. The author is with the Department of Electrical Engineering and Computer Science, University of California, Irvine, CA USA ( payam@eecs.uci.edu). Digital Object Identifier /TCSI modulation is a ubiquitous technique widely used in mixed-signal integrated circuits to achieve high resolution systems including oversampling data converters [5] [8], and frequency synthesizers [9] [14]. Depending on the implementation there are two types of modulators discrete-time (DT) [5], and continuous-time (CT) [15]. The more popular DT modulators, which are the focus of this paper, are less susceptible to noise than the CT counterparts and are easily implemented using switched capacitor circuits. Although numerous papers use the oversampling technique to design high-resolution systems that target various types of design criteria and applications [5], only a few papers study the effect of substrate noise on the performance of oversampling data converters. Blalack et al. in [16] presented an experimental study of the effects of switching noise in a high resolution oversampling data converter. With the design of an experimental test circuit, the authors were able to make interesting observations about the temporal spacing of the noise clock transitions with respect to the sampling clock transitions and its impact on the signal-to-noise+distortion ratio (SNDR) of the converter. The authors, however, did not quantify their observations and experiments. Therefore, some of their experimental results are valid only for a particular architecture that was used in their experiments. [15] studies the performance degradation in CT modulator due to the clock jitter. The noise model used by [15] is inaccurate and this model is not properly incorporated in the behavioral model of the CT modulator. Demir et al. in [17] proposed a generalized methodology for the evaluation of the interference noise caused by the digital switching activity. The authors used Markov chains to model the digital switching activities. The propagation media (e.g., substrate, the power-grid network) is modeled by a linear time-invariant (LTI) system. The methodology is very general and as a result, cannot address specific problems in conjunction with the modulators. The goal of this paper is to consider the effects of substrate noise on the performance of the DT oversampling modulators. The main contributions of this paper are as follows: an efficient stochastic model for substrate noise coupling in heavily doped substrates; a new study on the effects of phase-locked loop (PLL) jitter induced by substrate noise in the performance of the DT modulators. Section II presents a general overview of modulators. Section III explains a new mathematical model for substrate noise. Next, a detailed analytical model for the PLL clock jitter /$ IEEE

2 1074 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 Fig. 1. (a) Block diagram of an oversampling A/D converter. (b) Block diagram of an oversampling D/A converter. induced by substrate noise is proposed in Section IV. The impact of the clock jitter on the modulator is presented in Section V. Section VI summarizes the experimental results. Finally, Section VII presents the conclusions of our paper. Fig. 2. (a) Spectrum of the quantization noise of an 8-bit quantizer. (b) Spectrum of the noise-shaped 8-bit quantizer. II. OVERVIEW OF / MODULATORS / modulation is a noise-shaping technique that is realized using a closed-loop feedback around the quantizer. When combined with the high oversampling ratio, which is well above the highest input frequency, it allows us to achieve high signal-to-noise ratio (SNR) and dynamic range (DR) by adopting a coarse quantizer followed by digital filtering and sampling rate reduction [1]. The concept of the modulation technique is well understood in the context of oversampling data converters [Fig. 1(a) and (b)]. Some of the advantages of oversampling data converters over their Nyquist-rate counterparts are as follows. 1) Oversampling data converters are often easily implemented in fine-line SOC system due to the fact that they require much less precise analog components than the Nyquist-rate converters at the expense of massive use of digital signal processing techniques. 2) Oversampling converters have a superior performance in the presence of noise and interference. 3) Oversampling converters relax the stringent requirements imposed on the analog anti-aliasing filters for the A/D converters. As its name suggests, the basic idea behind an oversampling data converter is to sample [re-sample in the case of a digital analog (D/A) converter] the input signal at a rate significantly faster than the Nyquist rate so as to spread the quantization noise power-spectral density (PSD) over a bandwidth,, which is much greater than the Nyquist frequency, ( is the signal bandwidth). The SNR is enhanced by as much as, which is called oversampling ratio (OSR). Higher resolutions and wider dynamic ranges are attained through the use of the modulator, which effectively reshapes the quantization noise over the frequency band of interest, and enhance the SNR. The noise shaping phenomenon associated with a modulator is better illustrated using a simple example where the spectrum of the quantization noise of an 8-bit quantizer without the modulator is compared with that of the same 8-bit quantizer in the presence of a second-order modulator. Shown in Fig. 2(a) and (b) are the simulation results of this example. The modulator reshapes the spectrum of the quantization Fig. 3. Output spectrum of a second-order 16 modulator proposed in [18] with MATLAB and HSPICE simulations. error and highly attenuates the lower frequency components of the error. This will in turn lead to a higher SNDR if the modulator is employed in an oversampling data converter. In practice, the noise spectrum of a modulator deviates from the smooth frequency response of Fig. 2(b). Shown in Fig. 3 is the output PSD of a second-order modulator proposed in [18], and designed in a m standard CMOS process. The modulator is stimulated using a 1 khz input signal. Results of HSPICE simulation are processed using digital filtering and decimation in MATLAB. The output spectrum of the modulator using MATLAB (ideal) and HSPICE (transistor level) simulations is demonstrated in Fig. 3. The zeros of the noise transfer function (NTF) are displaced due to the finite gain of the constituent op-amp, hence, the output SNR degrades and noise level at low frequencies is not shaped as in ideal modulator. Due to their better performance in the presence of clock jitter and noise, the DT modulators are used in mixed-signal integrated circuits compared to their continuous-time counterparts [18], [19]. Therefore, we focus our analysis on the discrete-time modulators, although a similar study can also be carried out for the continuous-time modulators. There are many architectures proposed for the DT modulators [7], [18], [20]. All topologies may be characterized by

3 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1075 Fig. 4. System block diagram of a discrete-time 16 modulator. two transfer functions the NTF and the signal transfer function (STF). The NTF determines to what extent the quantization noise is reduced in a given bandwidth and hence determines the overall SNR of the converter. From a system viewpoint all single-quantizer loops are indicated by the universal architecture shown in Fig. 4. Depending on the specific application and the frequency band of the input signals can be either a low-pass filter (LPF) (in the base-band processing) or a bandpass filter (in RF and wireless applications). modulators are more noise sensitive than other blocks in Fig. 1(a) and (b). Like any feedback system, they can potentially be driven to instability, if the closed-loop poles are close to the unit-circle in the -plane. They are also susceptible to clock jitter due to substrate noise. To understand this effect, substrate noise must first be characterized. Fig. 5. Cross-sectional view of a static CMOS inverter along with chip-package interface parasitics. III. SUBSTRATE NOISE CHARACTERIZATION Substrate noise and power/ground (P/G) bounce are predominant environmental noise sources in mixed A/D integrated circuits are [2], [21]. Since a dominating component of the substrate noise injection is due to the leakage of the voltage bounce on the supply/return path, an accurate circuit model for substrate noise must incorporate the circuit model for the noisy supply and ground rails, a phenomenon that was not considered in previous researches. [21] considered the contribution of supply noise injection on the substrate noise ignoring the noise caused by the large-signal switching transients in the digital circuit. On the other hand, [22] focused on the substrate coupling induced by the large-signal switching transients of the circuit, neglecting the P/G bounce. An accurate analytical study of substrate noise should include both the direct coupling as well as the coupling due to fluctuations on the power and ground rails. In this section, an efficient model for substrate noise due to direct coupling of switching circuits as well as fluctuations on the P/G rails coupling is developed. The proposed analytical model will contain the statistical nature of the switching activity of digital circuits. The model is germane to epi-type heavily doped substrate used in mixed-signal circuits. Note that this model is less accurate compared to three-dimensional (3-D) models proposed in [23]. However, the advantage of the proposed model is that it can appropriately be incorporated in the analytical models developed for the PLL as well as the DT / modulator in this paper. In a CMOS mixed A/D integrated circuit the substrate is normally composed of a lightly doped epitaxial layer grown on a heavily doped substrate in order to minimize the transistor latch-up [1]. In an epi-type substrate technology the injected lateral current from the source of a digital circuit (e.g., a CMOS inverter) flows through the heavily doped substrate material because of its low resistivity compared to the inter-layer silicon Fig. 6. (a) Crcuit consisting of multistage tapered buffers for substrate noise injection. (b) Substrate noise waveform. or epitaxial layer [1]. The bulk can thus be modeled as a single electrical node for any given technology (see [1]). One of the dominant contributors to substrate noise is the leakage of the voltage bounce on the power/ground rails into substrate. The power/ground bounce itself is dominated by the simultaneous switching noise of output buffers. In the meantime, most CMOS logic elements can be reduced or decomposed into CMOS inverters [21]. These notions indicate the importance of studying the substrate noise injection mechanism in CMOS inverters. Shown in Fig. 5 is the cross-sectional view of a static CMOS inverter along with all electrical parasitics resulting from interactions between semiconductor materials with different doping concentrations. Fig. 5 also includes the electrical parasitics of P/G wires and the chip-package interface. According to this figure the chip s pin parasitics are represented by an RLC circuit (,, ) for the power supply pin, and an RLC circuit (,, ) for the ground pin. The parasitics introduced by bondwires and die pads are also modeled as an RLC circuit (,, ) for the power supply connection, and an RLC circuit (,, ) for the ground connection. Currents flowing through the bondwires and pin-to-die interface exhibit large slew-rates during output transitions, hence the supply voltage waveform seen by the on-chip circuitry experiences a large amount of switching noise. Fig. 6(a) depicts the circuit schematic being utilized to generate the substrate noise injection in an epitaxial CMOS technology.

4 1076 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 The circuit is comprised of forty 1-pF capacitors each driven by 6-stage CMOS tapered buffers in m CMOS technology. To reduce the simultaneous switching noise, every ten tapered buffers are connected to a single ground and supply pin. Electrical parasitics seen in regard to a single inverter are included in the circuit to accurately model the substrate and P/G wires. More precisely, in Fig. 6(a),, are P/G impedances modeling the chip-package interface parasitics including the chip bondwires and package traces. These impedances are highly inductive, as also depicted in Fig. 5 for a single inverter. represents the equivalent substrate impedance consisting of the substrate bias resistance and inductance, respectively. is the equivalent impedance from the chip ground to the heavily doped substrate including the wiring capacitance and junction capacitance of nmos device. is the equivalent impedance from the chip power supply to the heavily doped substrate including the nwell junction capacitance and the nwell physical resistance. is the equivalent load impedance including the gate capacitance of the following fan-out stages. is the on-chip decoupling capacitor used to reduce the P/G bounce. Since the substrate is tightly coupled to the return path by distributed surface substrate contacts, the voltage bounce arising from logic switching, especially on the ground path, appears as substrate noise. Fig. 6(b) shows the substrate noise for a complete one-cycle simultaneous switching of the buffers. The underdamped oscillatory behavior of substrate coupling injected by the P/G bounce is due to the highly inductive behavior of the bondwires and on-chip global interconnects at high frequencies. Substrate noise coupling resulting from fluctuations on the on-chip power supply lines and ground wires due to signal switching of output buffers can have excessively large values when multiple output drivers switch simultaneously, as also considered in Fig. 6(a). Power and ground fluctuations are out of phase, therefore, we introduce a new term for the fluctuations on the P/G lines. The effective P/G noise is the algebraic summation of ringings on the power and ground rails [24]. In fact, the effective P/G bounce is the main source of substrate noise, which causes logic and timing failure in the circuits. To reduce the effective P/G bounce, which is a high frequency waveform, on-chip decoupling capacitors have to be placed in close proximity of output buffers, as also shown in Fig. 6(a). In practice, decoupling capacitors can be placed at any location that is free after floorplanning. On-chip decoupling capacitors across output buffers make the supply fluctuations in phase with the ground fluctuations, and remove high frequency components from supply and ground variations. In the time domain, an on-chip decoupling capacitor smooths out the variations on power supply and ground wires that would have otherwise been spike-like waveforms. In the frequency domain, it shrinks the spectral bandwidth of the variations. Reference [2], provides a comprehensive study of the effect of on-chip decoupling capacitors and the mathematical relationship between the peak value of the P/G noise and required capacitance value to reduce the effective P/G noise. In order to characterize the statistics of substrate coupling due to the circuit switching and effective P/G noise, an observation is made that is based on actual experimental test circuits carried out in [1]. In a lightly doped epitaxial layer grown on a heavily doped substrate, if the analog and digital circuits are separated by Fig. 7. Substrate noise coupling. atleastfourtimesthethicknessoftheepitaxiallayer, theresistance between the substrate contacts will be independent of their separations [1]. Therefore, the spacing between the switching blocks causes solely a random phase shift on the noise fluctuations. On the other hand, the peak amplitudes of damped oscillations for each noise waveform and,[cf. Fig. 6(b)] are a function of switching activities of digital circuits and are thus represented by discrete-time random processes. The above observations help us derive a mathematically robust and efficient stochastic model fo substrate noise, as follows: Substrate noise is comprised of two additive terms. The first term is due to the low-to-high signal transition, and the second one is due to the high-to-low signal transition, as depicted in Fig. 7. is a discrete-time random process that accounts for the number of adjacent switching circuits switching simultaneously. and are a set of uniformly distributed independent random variables in the interval ( is the clock cycle-time). Their presence in the noise expression is because the digital circuits switch randomly across the chip. The random switching of the digital circuits located at different locations across the chip are directly translated to random signal propagation delays toward the sensitive analog terminals inside the chip. The analysis can easily be extended to a more general scenario in which there are multiple synthesized frequencies across the chip. Theorem 1 proves useful in determining the spectral contents of. Theorem 1: Consider the following wide-sense cyclo-stationary stochastic process: where process (1) is a discrete-time random-process. The shifted,given

5 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1077 is a wide-sense stationary process, whose PSD is Proof: This theorem is an extension of Theorem 2 in [25, p. 374]. Using Theorem 1 and (2) the PSD of substrate noise is obtained as follows: (2) (3) Applying (3) on a special example regarding substrate noise proves useful in forthcoming discussions. This example includes the case in which the ringing duration of substrate noise is small compared to the duty cycle of the synthesized signal of the PLL. In this case, the substrate noise is accurately modeled as impulse train with normally distributed random area and a uniformly distributed random time-shift to account for the switching activity and random signal propagation delay, respectively. Consequently, the noise expression in (1) is simplified to a stochastic impulse train specified by The PSD of substrate noise for this particular example simplifies to The above analytical model is used in Section IV to derive the phase noise of the voltage-controlled oscillator (VCO) and the PLL timing jitter. IV. PLL CLOCK JITTER DUE TO SUBSTRATE NOISE The operation of a discrete-time modulator implemented using the switched-capacitor circuits depends on the complete charging or discharging during each phase of the clock. Therefore, the effects of clock jitter induced by substrate noise on a switched capacitor circuit can be analyzed by examining its effect on the sampling of the input signal and the reconstruction of the output signal. This also implies an important observation, that is, the effects of the clock jitter on a switched-capacitor modulator is independent of the structure or order of the modulator. Discrete-time modulators are clocked with a monolithic PLL. To analyze the effects of clock jitter induced by substrate noise, it is needed to study the noise impact on the PLL timing jitter. In this section we briefly study the timing jitter induced by substrate noise in closed-loop PLLs. [26] [28] discuss the PLL timing jitter in more depth and detail. The jitter and phase noise in a free-running oscillator are not discussed (see [29] and [30]). Due to their desirable features (e.g., not exhibiting any false lock, having a fast acquisition-time, and retaining a zero-phase offset in the lock condition), charge-pump PLLs, shown in Fig. 8, have found widespread use in frequency synthesis and timing (4) (5) Fig. 8. System block diagram of the charge-pump PLL. recovery applications. The output voltage of the sequential PFD can be expressed as a linear function of the phase difference. The output voltage of the PFD acts like a control voltage for the switched current sources of the charge pump circuit. Finally, the transfer function of the second-order PLL having a simple RC circuit as the LPF is easily obtained. For the related formulations and derivations, refer to [31]. The main focus is thus on charge-pump PLLs, although the analysis is easily extended to any type of phase-locked loop (e.g., the -based PLL). Fig. 8 shows a simplified system block diagram of a charge-pump PLL circuit employed as a clock generator. In a PLL-based clock generator circuit, the VCO is the most noise-sensitive circuit among other sub-blocks. The reason is that the VCO is a closed-loop ring oscillator where corrupted zero crossings of the oscillations due to substrate and supply noise are recirculated in the loop. Moreover, fast jitter components generated by the VCO are not suppressed by the PLL (the PLL operates as a highpass filter to the VCO noise input). On the other hand, the jitter coming from the input terminal does not have much of an effect because firstly, in a PLL-based clock generator the input is coming from a very low-jitter source, and secondly, the PLL loop filter eliminates the in-band components of the input jitter. The VCO phase noise analysis is carried out by studying a simple conventional differential delay stage commonly used in a ring VCO. To understand the substrate noise effect on the VCO operation, consider a four stage fully differential ring oscillatorbased VCO shown in Fig. 9 [31]. The VCO incorporates a replica biasing circuitry that always biases the delay element such that the output voltage swing of each differential delay stage is fixed and independent of supply variation. Shown in Fig. 10 is the circuit topology of a differential delay stage being incorporated in the implementation of Fig. 9. The capacitor pair has been employed to neutralize the feedforward transition provided by of the MOS devices. Each MOS transistor of the differential source-coupled pair experiences a large-signal gate voltage and therefore, it experiences multiple transitions in its region of operation. Moreover, the - relationship of a MOS transistor is nonlinear for both triode and saturation regions. All these phenomena cause the VCO frequency to be a nonlinear function of the supply and input control voltages. This nonlinear relationship is also dependent on the circuit topology being adopted for a delay stage, however, as will be seen later in this section, the general relationship between the excess VCO frequency and substrate noise remains approximately the same.

6 1078 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 Fig. 9. The VCO based on differential ring oscillator with the voltage controlled resistor and replica biasing. Fig. 11. Substrate injection mechanism for a differential delay stage. Fig. 10. Simple differential delay stage. In most of today s differential ring oscillator architectures the VCO gain is controlled by the tail current which makes it possible to have a wider tuning range and a pseudo-linear frequency-voltage relationship. The noise propagated through the substrate due to the effective P/G bounce and large-signal switching appear as a common-mode signal for the differential pair transistors, thus does not affect the delay and dynamic operation of the differential pair (cf. Fig. 11). On the other hand, substrate noise affects through both the control path and the direct coupling to the tail current s transistor, as shown in Fig. 11. The former component is attenuated by using a differential control input while the latter being almost intact. As will be illustrated in Section VI, the circuits will be designed using a submicron CMOS process. To capture the short-channel effect of submicron devices, the short-channel MOS model is employed throughout the analysis, i.e., Using (6) (8), the tail current is (6) (7) In (6), is the drain-source voltage at which the velocity saturation occurs, and is the saturated drift velocity. In (7), measures the degree of velocity saturation (with the longitudinal electric field). is the electric field when the velocity saturation comes into play. Since the velocity-saturated drain source voltage,,is also a nonlinear function of the gate-source voltage, the tail current becomes a nonlinear function of substrate noise which introduces harmonic distortion at the VCO output. (8) (9) To quantify the VCO phase noise and subsequently, the PLL jitter induced by substrate noise, we first obtain the VCO phase noise in response to substrate noise variations. For the ultimate design criteria of having a small coupling from the substrate material and P/G rails to the PLL circuit we can simplify (9) and derive the autocorrelation function of excess frequency variation in terms of the autocorrelation of substrate noise. Starting with (9), the current variations of the tail current due to substrate noise is equal to (10) where, and accounts for the total contributions of coupled noise on the control input line and coupled noise through the substrate bulk. The assumption in (10) is readily satisfied by placing on-chip decoupling capacitors across the large current drivers. Note that each delay stage inside the ring VCO is driven by a similar delay stage, and is driving another similar delay stage. The large-signal input applied to the differential pair causes the bias points of differential pair transistors to vary periodically. The output differential current is a nonlinear function of the instantaneous input voltage and the tail current. Differential operation reduces the noise to a great extent. Nonetheless, the large-signal operation of a ring VCO influences the overall VCO sensitivity to substrate noise. The modulating noise on the input signal to each delay stage has a negligible contribution to the differential output of the stage compared to the coupled noise from the tail current. The reason is that the differential transconductance is nonzero only in a small transition region around the zero crossing points of the input differential voltage, where the switching devices are in the saturation region [34]. In this small transitional interval, the input signal variation attains its maximum rate of change, therefore, the modulating substrate noise from the previous stage will have a negligible effect. A significant differential component of noise and fluctuations for each delay stage of the ring VCO is due to the variations of the tail current of that stage induced by the substrate noise. These observations are verified using an HSPICE simulation of a four-stage differential ring VCO circuit, where each stage delay stage is shown in Fig. 10. Fig. 12(a) and (b) compare the differential output waveforms of the first and the third delay stages in Fig. 9 with and without substrate noise. As observed in Fig. 12(a) and (b), modulating fluctuation

7 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1079 Fig. 13. The kth and (k +1)th stages of a differential ring VCO along with the parasitic capacitances. Fig. 12. (a) Differential output voltage of the first stage. (b) Differential output of the second stage. (c) Output spectrum of the third stage with and without substrate noise. on the differential output signal of each stage are mainly dominated by the noise of that stage. Shown in Fig. 12(c) is a comparison between the spectrum of the differential output of the third stage with and without substrate noise. Two important phenomena are observed. First, the phase noise of the VCO output is significantly increased. Secondly, a noise-induced frequency shift in the center frequency is taking place, affecting the accuracy of the PLL that incorporates this VCO. The tail current s fluctuations induced by substrate noise thus appears as an additive noise at the differential output voltage of each delay stage. To predict the VCO phase noise induced by substrate noise, the VCO frequency is first calculated. Fig. 13 shows the stage in a chain of stage differential ring-vco along with the capacitors that contribute to the delay calculation. The common node shown in Fig. 13 experiences a double-frequency variation compared to the voltage variations at the gate terminals of switch-pair transistors [31]. The input capacitance seen at the gate terminal of the th stage is therefore expected to be slightly smaller than the gate-source capacitance. Ignoring the channel length modulation in MOS devices, and assuming the gate terminals of the the stage to have fully differential voltages, the current voltage relationship of at each gate terminal of the stage is expressed as follows (see Appendix I): where. Equation (11) states that the large-signal input impedance of the differential pair can be defined using a nonlinear voltage-dependent effective capacitance. The value of this effective input capacitance is a function of the input voltage, thereby varying with time. Assuming a sinusoidal input with the amplitude of, the time average of this effective capacitance is calculated as follows [32]: (12) where represents the natural logarithm of. Using (12), the 50% delay of the stage under a step input is calculated as follows: (13) where is the output resistance of the stage, and is an external capacitance added to achieve the desired VCO center frequency. Since pmos transistors are biased to be in the triode region, is approximately equal to the pmos output resistance. Assuming identically matched delay stages, the VCO output frequency is given as follows: (14) (11) where is the constant coefficient, which in the case of delay stage of Fig. 10, is Both and are nonlinear functions of substrate noise, thereby making to be a nonlinear

8 1080 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 function of substrate noise. Nonetheless, this nonlinear dependence has a negligible contribution to the phase noise. This is proved by deriving an upper bound for the load capacitance in the presence of substrate noise. To arrive at such upper-bound, we calculate the first-order truncation of Taylor series expansion of the overall nonlinear junction capacitance,, with respect to the substrate noise. Using this approach, an upperbound for the load capacitance is (15) where is the total load capacitance with a zero-valued substrate noise, is the junction coefficient, and is the build-in potential. The second additive term is very small compared to unity for given submicrometer technology, which justifies our assumption of ignoring the effect of substrate noise on junction capacitances. Having obtained the current variation of the tail current due to substrate noise, the excess VCO frequency in terms of the substrate voltage is readily calculated, i.e., (16) where is characterized by (1). Substrate noise therefore modulates the current gain of the differential delay stage, thereby making the VCO excess frequency to be a cyclo-stationary process. Hence, the VCO excess frequency becomes. The general form of (16) holds true for any arbitrary differential stage, while varies with the circuit topology. The time-average of autocorrelation function of the VCO excess frequency is a stationary process [25], and can be derived as (17) where represents the time-average operator. The time-average autocorrelation of the VCO excess frequency variation is a linear function of the autocorrelation of the effective P/G noise. The time-average PSD of the VCO excess phase is referred to as the phase noise. Consequently, the phase noise of the VCO,, induced by substrate noise is obtained using the following equation: (18) where is the PSD of substrate noise given by (3), or (5) in the simplified case of having impulsive noise. The simplified linear relationship between substrate noise and the incremental current variation of the tail current allows one to consider the effect of substrate noise as an additive noise in the closed-loop PLL system, however with a different VCO gain,. A general noise analysis of the PLL must be carried out using the nonlinear stochastic modeling of the PLL and by solving the characteristic Fokker Plank stochastic differential equations thereof. In a robust PLL circuit with a larger than required lockrange, the VCO phase noise induced by substrate and P/G noise generates the timing jitter at the PLL output without unlocking the PLL loop. Therefore, the PLL timing jitter in response to the VCO phase noise is obtained under the locked condition. The closed-loop PLL system is a linear feedback system under the locked condition and the PSD of the output is related to the spectral density of the VCO phase variations by the squared magnitude of the closed-loop transfer function (19) where is the loop filter, is the constant current source in the charge-pump circuit, and represents the frequency division factor, as also shown in Fig. 8. is the PSD of the excess phase induced by substrate noise. The PLL phase noise and timing jitter due to substrate noise are derived using (5), (18), and (19). For a second-order PLL circuit incorporating the first-order series RC circuit ( - ) as the loop-filter, and depending on the PLL circuit parameters, the closed-form expressions can be in one of the two possible following forms (the critically damped response is derived as a special case of the underdamped response): (20) (21) where represents the total average noise power of substrate noise. In practice, the number of adjacent switching circuits is uncorrelated to the number of adjacent switching circuits in another location inside the chip. Therefore, the random amplitude of the noise spikes in (1),, can be modeled as white noise process, which simplifies the noise calculation. Moreover, and are the closed-loop poles of the second-order charge-pump PLL circuit [roots of Laplace transform of the denominator in (25)]. The closed-loop poles of the PLL circuit will appear as a complex conjugate pair (i.e., ) if the output phase exhibits an underdamped transient response. The poles lie on the negative real axis for an overdamped transient response (i.e.,, ). In general, the timing jitter of the PLL is defined as [27], [29] (22) where is the delay from the reference edge, and represents the autocorrelation of the PLL excess phase. This definition is in accordance to the procedure taken during the actual measurements of the PLL timing jitter, where the synthesized PLL signal is used as both the trigger and the input to digital oscilloscope or a communications signal analyzer. The oscilloscope compares the phase difference between the phase transitions in the clock waveform, separated by an interval from the reference edge (cf. Fig. 14). The oscilloscope, in fact, measures the variance of the zero crossings.

9 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1081 Fig. 14. Definition of the accumulated jitter. The timing jitter is thus equal to (a) (b) Fig. 15. (a) In-band component of the jitter-induced output error. (b) Out-of-band component of the jitter-induced output error. (23) where is the discrete-time Fourier transform of the second term in (26). Note that the quantization error,, in the presence of the clock jitter differs from the quantization noise,, of a jitter-free modulator. The spectrum of the jitter-induced output error, is (24) Equations (23) and (24) state that the random variations in the zero crossing time instants of the signal have a characteristic, therefore the error will have a spectrum that appears as a skirt on the spectral line of the fundamental frequency component. V. IMPACT OF CLOCK JITTER ON MODULATORS Consider the general block diagram of a DT modulator shown in Fig. 4. If the synthesized clock contains the timing jitter, the front-end sample-and-hold (S/H) circuit will sample the input analog signal at the wrong instant of time, thereby producing sampling uncertainties that degrades the SNR of the data converter. In the absence of the clock jitter, the discretetime Fourier transform of the output signal of the modulator in Fig. 4 is (25) In the presence of the clock jitter induced by substrate noise, the sampling instants are now placed at ( ), where is the random perturbation around the ideal sampling instant,. In practice, the clock jitter is a small portion of the clock cycle-time, which allows one to use the first-order Taylor series expansion to linearize the input sampling (26) The discrete-time output signal in the presence of clock jitter induced by substrate noise both suffers from the quantization error and clock jitter due to substrate noise (27) (28) where. Equation (28) actually states that the sampling uncertainties due to the clock jitter generates an in-band jitter-induced noise component, as also graphically illustrated in Fig. 15, that directly results in the performance degradation. Furthermore, the modulator is incapable of reducing the impact of this noise through its noise shaping property. In a data converter, the modulator is accompanied by a digital LPF (cf. Fig. 1) to filter out all of the out-of-band noise components, and to meet the anti-aliasing requirements of the input signal. Therefore, only the error term that lies in the modulator passband is considered. The passband is determined by the poles of which are the zeros of the NTF. The jitter-induced output error is thus approximated as The PSD of the jitter-induced output error becomes (29) (30) The PSD,, is the Fourier transform of the discrete-time autocorrelation,, of. Since, the autocorrelation function, is thus equal to (31) The first multiplicative term gives the variance of the deterministic signal (the derivative of the input signal) with specifying the time-average operation, while the second term represents the autocorrelation function of the clock jitter discretized at multiple integers of the clock cycle-time. This autocorrelation function is readily derived using the inverse Fourier

10 1082 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 transform of the PSD of the output excess phase, PLL circuit given in (19), of the (32) Having obtained the autocorrelation function, the PSD of the jitter-induced output error is thus obtained by taking the discrete-time Fourier transform of. The total jitter induced noise power of the modulator in the passband is the area under the PSD curve, which is the autocorrelation at (i.e., (33) where represents the energy of the STF of the / modulator, and is the constituent resistor in the loop filter of the PLL circuit. Note that the average power of the jitter-induced noise at the output of the modulator is a decreasing function of the OSR which is the ratio between the sampling frequency,, and the passband. Moreover, the output noise power is directly proportional to the power of the time-derivative of the input signal. As a consequence, the modulator will exhibit more noise for high-frequency and higher amplitude input signals. The noise power also increases with the VCO noise gain and the substrate noise power, and decreases with the chargepump current and the resistor of the PLLs loop filter. Assuming a sinusoidal input with an amplitude and frequency in the passband, the power will be. The average power of the jitter-induce noise at the output of modulator thus becomes (34) If the SNR is completely limited by the jitter rather than the noise-shaped quantization error, then for a sinusoidal input with an amplitude the SNR expression is (35) VI. SIMULATION RESULTS The above analytical models are utilized to predict the phase noise and jitter of a PLL-based clock generator due to substrate noise and also to investigate the SNR degradation of the data converter. To verify the proposed analytical models, the following experimental setup is constructed. Fig. 16. Circuit diagram of the designed second-order 16 modulator in standard 0.25-m CMOS process. To better understand the performance of the modulator in the presence of substrate noise and verify our analytical model, a second-order fully differential modulator with a two-level quantizer similar to the one proposed in [18] is designed in a m standard CMOS process. The circuit diagram is shown in Fig. 16. The op-amp used in each delay stage is a simple two-stage fully differential amplifier with a continuous-time common-mode feedback (CMFB) circuit similar to the one proposed in [35]. The latched comparator consists of a pmos differential pre-amplifier followed by a doubly used pmos and nmos cross-coupled regenerative latch. The modulated is operated at the clock rate of 100 MHz. The clock to the circuits is provided by a charge-pump PLL circuit similar to the one proposed in [33]. The PLL circuit is also designed in m CMOS process with a lock range of 1 MHz-500 MHz at 2.5 V supply voltage. To experimentally emulate the switchings of digital circuits and to generate the substrate noise caused by logic switching, 40 tapered inverters driving 1-pF capacitors are placed around the PLL clock circuit [cf. Fig. 6(a)]. The circuit is laid out in a low epi process. Post-layout simulations are carried out to account for the metal and interconnect parasitics. To maximally dampen the direct substrate coupling on the sampling network, physical separation is provided between the second-order modulator and the noisy digital circuit. The proposed chip-level substrate network consists of three layers supply parasitics, the switching transistor circuits, and the resistive mesh modeling the signal propagation in the substrate. The p+ guard ring surrounding the modulator is modeled using a low-resistive network. In an EPI-type substrate technology the injected lateral current from the source of a CMOS circuit (e.g., a CMOS inverter) flows through the heavily doped substrate material because of its low resistivity compared to the inter-layer silicon or epitaxial layer [Su93]. Moreover, to encompass the randomness of the switching activity of digital circuits, the input signals to the tapered buffers are generated by a pseudo-random generator with a Gaussian distribution. All the circuit simulations are performed using HSPICE. We will investigate the effects of clock jitter induced by substrate noise on the modulator performance. Fig. 17(a) shows simulated P/G noise resulting from the simultaneous switching of tapered buffers. Fig. 17(b) depicts substrate noise injected by the signal fluctuations on the powersupply and ground lines. To carry out the phase and jitter simulation and verify the analytical models developed in this paper, the average energy of

11 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1083 Fig. 19.Phase noise of the PLL output phase versus frequency. (a) Underdamped (b) Overdamped. Fig. 17. (a) P/G noise due to simultaneous switching of the output buffers. (b) Effective substrate noise injected by the fluctuations of power supply and ground lines. Fig. 20. Jitter variance of the PLL output phase versus the delay with respect to the reference edge. (a) Underdamped. (b) Overdamped. Fig. 18. Comparison between the phase noise of the designed VCO obtained using simulation and the one using (18). substrate noise per cycle and the time at which substrate noise reaches its maximum are calculated. The noise information are then used to calculate the VCO phase noise and the PLL jitter using the proposed analytical models. Results of the calculation are compared with those obtained by the direct use of HSPICE simulation of the PLL circuit. A. Clock Jitter Experiment First, the noise spectra of the composing VCO circuit in the presence of substrate noise injection is obtained. Fig. 18 indicates the phase noise (in dbc/hz) of the designed ring VCO calculated, once using the simulation; and then using (18). A comparison between the simulation and (18) reveals that the model accurately follows the simulation results over the frequency offset range of [10 khz, 1 MHz]. The second experiment involves the phase noise of the PLL circuit for two cases of having an underdamped response and having an overdamped response. The overdamped and underdamped cases are achieved by varying the damping ratio of the loop transfer function using two different values for the resistor of the loop filter. Fig. 19(a) depicts the PLL phase noise versus frequency for the underdamped response. The phase noise is simulated under three different substrate noise couplings with different average power. The proposed analytical model closely follows the simulation results over the frequency offset range and for different noise average power. Fig. 19(b) demonstrates the PLL phase noise versus frequency for the overdamped response and under the three different substrate coupling waveforms with different average power. Once again, the analytical model is accurately predicting the phase noise variations with respect to the frequency. In the next simulation experiment, we compare the jitter variance of the closed-loop PLL with respect to the delay from the reference edge obtained from simulation and derived from the analytical model. Such performance comparison is made under three different substrate noise couplings. The jitter variance of the designed PLL circuit is calculated for two cases of an underdamped response and an overdamped response. Fig. 20(a) shows the jitter versus delay for the underdamped response. The analytical model accurately follows the overshoot in the jitter profile that is predicted by simulation results for all three different substrate noise couplings. Fig. 20(b) shows the PLL jitter versus delay for the overdamped response. Once again, the analytical model is accurately predicting the phase noise variations with respect to the delay from the reference edge. As expected, the underdamped system shows a larger accumulated jitter.

12 1084 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 Fig. 21. (a) SNR versus input amplitude. (b) SNR versus noise power. B. Performance Degradation of DT / Modulators To experimentally verify the foregoing analytical models for modulator, the designed PLL circuit is used to provide clock signal to the second-order modulator in Fig. 16. As mentioned above, P+ guard-rings are used around the modulator during the layout design. Therefore, only the impact of the clock jitter on the modulator is examined. First, all the digital circuits are deactivated and the SNR is simulated without any noise injection. The surrounding tapered buffers are then activated and the SNR is calculated for the oversampling ratio of 256. Fig. 21(a) indicates the SNR in terms of the input amplitude with and without clock jitter induced by substrate noise injection. The simulations are performed for the input data range from db to db. Jitter induced noise in DT modulators scales with the input amplitude, therefore, SNR remains intact for different input signal amplitudes, as was predicted by (35). For large input signals, the precision of the converter is limited by the harmonic distortion of the op-amp rather than quantization noise. Fig. 21(b) demonstrates the overall SNR of the designed DT modulator with respect to the average power of substrate noise. A comparison has been made between (35) and simulation results. The high-level of accuracy of the closed-form analytical model is evident from Fig. 21(b). Fig. 22. Circuit schematic of a neutralized differential pair. APPENDIX Consider a neutralized differential pair driven by fully differential signals shown in Fig. 22. The gate current is expressed as follows: (A.1) The voltage across the tail current is the superposition of the high-frequency and low-frequency components (A.2) where specifies the overall grounded capacitance at the common node. is characterized using the large-signal - model of the differential pair [31] (A.3) VII. CONCLUSION In this paper, the effects of clock jitter induced by substrate noise in discrete-time modulators was studied. First, a new stochastic model for substrate noise was proposed. This model was then utilized to study the clock jitter in PLL clock generators. Next, the effect of the clock jitter on the performance of the modulator was studied. A circuit consisting of a second-order modulator, a charge-pump PLL, and forty multistage tapered inverters driving 1-pF capacitors was designed in a standard CMOS process. Several experiments on the designed circuit verified the high accuracy of the proposed analytical models. where is the input common-mode voltage, and is the device threshold voltage. The AC components of the drain current currents and of the differential pair sum to zero. Therefore, Substituting (A.4) in (A.1) results in the following: In practice,, which leads to (11). (A.4)

13 HEYDARI: CHARACTERIZING THE EFFECTS OF PLL JITTER 1085 REFERENCES [1] D. K. Su, M. J. Loinaz, A. Masui, and B. A. Wooley, Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp , Apr [2] P. Heydari and M. Pedram, Ground bounce in digital VLSI circuits, IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 11, no. 2, pp , Apr [3] P. Heydari, Characterizing the effects of clock jitter due to substrate noise in discrete-time 1/6 modulators, in Proc. IEEE/ACM Design Automation Conf. (DAC), Jun. 2003, pp [4] M. Van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. G. E. Engels, and I. Bolsens, Analysis and experimental verification of digital substrate noise generation for epi-type substrates, IEEE J. Solid-State Circuits, vol. 35, no. 7, pp , Jul [5] S. R. Norsworthy et al., Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, [6] S. Rabii and B. A. Wooley, A 1.8-V digital-audio sigma-delta modulator in 0.8-m CMOS, IEEE J. Solid-State Circuits, vol. 32, no. 6, pp , Jun [7] I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S.-L. Chan, A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 2 oversampling ratio, IEEE J. Solid-State Circuits, vol. 35, no. 12, pp , Dec [8] J. Grilo, I. Galton, K. Wang, and R. G. Montemayor, A 12-mW ADC delta-sigma modulator with 80 db of dynamic range integrated in a single-chip bluetooth transceiver, IEEE J. Solid-State Circuits, vol. 37, no. 3, pp , Mar [9] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, Delta-sigma modulation in fractional-n frequency synthesis, IEEE J. Solid-State Circuits, vol. 28, no. 5, pp , May [10] M. H. Perrott, T. L. Tewksbury III, and C. G. Sodini, A 27-mW CMOS fractional-n synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE J. Solid-State Circuits, vol. 28, no. 12, pp , Dec [11] W. Rhee, B.-S. Song, and A. Ali, A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order 16 Modulator, IEEE J. Solid-State Circuits, vol. 35, no. 10, pp , Oct [12] S. Wilingham, M. Perrott, B. Setterberg, A. Grzegorek, and B. McFarland, An integrated 2.5 GHz 61 frequency synthesizer with 5 s settling and 2 Mb/s closed loop modulation, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp [13] K. Vleugels, S. Rabii, and B. A. Wooley, A 2.5-V sigma-delta modulator for broad-band communications applications, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp , Dec [14] M. H. Perrott, M. D. Trott, and C. G. Sodini, A modeling approach for 6 1 fractional-n frequency synthesizers allowing straightforward noise analysis, IEEE J. Solid-State Circuits, vol. 37, no. 8, pp , Aug [15] J. A. Cherry and W. M. Snelgrove, Clock jitter and quantizer metastability in continuous-time delta-sigma modulators, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp , Jun [16] T. Blalack and B. A. Wooley, The effects of switching noise on an oversampling A/D converter, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1995, pp [17] A. Demir and P. Feldmann, Modeling and simulation of the interference due to digital switching in mixed-signal ICs, in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1999, pp [18] B. Boser and B. A. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE J. Solid-State Circuits, vol. 23, no. 12, pp , Dec [19] J. Nedved, J. Vanneuville, D. Gevaert, and J. Sevenhans, A transistoronly switched current sigma-delta A/D converter for a CMOS speech CODEC, IEEE J. Solid-State Circuits, vol. 30, no. 7, pp , Jul [20] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping, IEEE J. Solid-State Circuits, vol. SC-22, no. 12, pp , Dec [21] M. Badaroglu, M. Van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. G. E. Gielen, and H. J. De Man, Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits, IEEE J. Solid-State Circuits, vol. 37, no. 11, pp , Nov [22] M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp , Mar [23] N. K. Verghese, D. J. Allstot, and M. A. Wolfe, Verification techniques for substrate coupling and their application to mixed-signal IC design, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp , Mar [24] P. Heydari and M. Pedram, Jitter-induced power/ground noise in CMOS PLLs: A design perspective, in Proc. IEEE Int. Conf. on Computer Design, Sep. 2001, pp [25] A. Papoulis, Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, [26] P. Heydari and M. Pedram, Analysis of jitter due to power-supply noise in phase-locked loops, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2000, pp [27] A. Hajimiri, Noise in phase-locked loops, in Proc. IEEE Southwest Symp. Mixed-Signal Design, Feb. 2001, pp [28] M. Mansuri and C.-K. K. Yang, Jitter optimization based on phaselocked loop design parameters, IEEE J. Solid-State Circuits, vol. 37, no. 11, pp , Nov [29] A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE J. Solid-State Circuits, vol. 33, no. 2, pp , Feb [30] A. Demir, A. Mehrotra, and J. Roychowdhury, Phase noise in oscillators; A unifying theory and numerical methods for characterization, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 5, pp , May [31] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, [32] P. Heydari and R. Mohanavelu, Design of ultrahigh-speed low-voltage CMOS CML buffers and latches, IEEE Trans. Very Large-Scale Integration (VLSI) Syst., vol. 12, no. 10, pp , Oct [33] J. G. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp , Nov [34] P. Heydari, Design and analysis of low-voltage current-mode logic buffers, in Proc. IEEE Int. Symp. Quality Electrical Design, Mar. 2003, pp [35] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, Payam Heydari (S 98 M 00) received the B.S. degree in electronics engineering and the M.S. degree (with honors) in electrical engineering from the Sharif University of Technology, Tehran, Iran,in 1992, 1995,and 2001, respectively, and the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, in During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer very large-scale integrated (VLSI) circuits. He worked at IBM T. J. Watson Research Center, Troy, NY, working on gradient-based optimization and sensitivity analysis of custom-integrated circuits during the summer of Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is high-speed analog and RF integrated circuits design and analysis. Prof. Heydari currently serves as the member of the Technical Program Committees on the International Symposium on Low-Power Electronics and Design (ISPLED), International Symposium on Quality Electronic Design (ISQUED), and the local arrangement Chair of the ISPLED Conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in He served on the Technical Program Committee of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and the 2003 International Symposium on Physical Design (ISPD). Dr. Heydari received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Best Paper Award. He was recognized as the 2004 Outstanding Faculty by the EECS Department, University of California, Irvine. He also received the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE Systems, University of Southern California, and the 2001 Technical Excellence Award in Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage.