VIPER28. Off-line high voltage converters. Features. Description. Application

Transcription

1 Off-line high volage converers Feaures 800 V avalanche rugged power secion PWM operaion wih frequency jiering for low EMI Operaing frequency: 60 khz for L ype 115 khz for H ype Sandby power < 50 mw a 265 V AC Limiing curren wih adjusable se poin Adjusable and accurae over-volage proecion On-board sof-sar Safe auo-resar afer a faul condiion Hysereic hermal shudown Delayed overload proecion Applicaion Auxiliary power supply for consumer and home equipmen ATX auxiliary power supply Low / medium power AC-DC adapers SMPS for se-op boxes, DVD players and recorders, whie goods Descripion The device is an off-line converer wih an 800 V rugged power secion, a PWM conrol, wo levels of over-curren proecion, over-volage and overload proecions, hysereic hermal proecion, sof-sar and safe auo-resar afer any faul condiion removal. Burs mode operaion and device very low consumpion helps o mee he sandby energy saving regulaions. Advance frequency jiering reduces EMI filer cos. The exra power imer allows he managemen of oupu peak power for a designed ime window. The high volage sar-up circui is embedded in he device. Figure 1. Typical opology + DC inpu high volage wide range - DRAIN DRAIN EPT GND VIPER28 VDD CONT FB DIP-7 + DC Oupu volage - Table 1. Device summary Order codes Package Packaging VIPER28LN VIPER28HN DIP-7 Tube January 2009 Rev 2 1/

2 Conens VIPER28 Conens 1 Block diagram Typical power Pin seings Elecrical daa Maximum raings Thermal daa Elecrical characerisics Typical elecrical characerisics Typical circui Operaion descripions Power secion and gae driver High volage sarup generaor Power-up and sof-sar up Power down operaion Auo resar operaion Oscillaor Curren mode conversion wih adjusable curren limi se poin Over-volage proecion (OVP) Abou CONT pin Feed-back and overload proecion (OLP) Burs-mode operaion a no load or very ligh load Exra power managemen funcion (EPT) nd level over-curren proecion and hiccup mode Package mechanical daa Revision hisory /28

3 Block diagram 1 Block diagram Figure 2. Block diagram Vcc VDD DRAIN LEB EPT Tovl EPT Tov l BLOCK OLP OSCILLATOR Inernal Supply bus & Reference Volages SUPPLY & UVLO UVLO HV_ON Isar-up THERMAL SHUTDOWN CONT SOFT START OCP BLOCK + - OCP BURST TURN-ON LOGIC LEB S R Q OTP OVP DETECTION LOGIC OVP PWM BLOCK PWM Disable 2nd OCP - + 2nd OCP LOGIC Q OTP OVP OLP S R HV_ON BURST-MODE REFERENCES BURST-MODE LOGIC BURST Rsense FB GND 2 Typical power Table 2. Typical power Par number 230 V AC V AC Adaper (1) Open frame (2) Adaper (1) Open frame (2) VIPER28 18 W 24 W 10 W 13 W 1. Typical coninuous power in non venilaed enclosed adaper measured a 50 C ambien. 2. Maximum pracical coninuous power in an open frame design a 50 C ambien, wih adequae hea sinking. 3/28

4 Pin seings VIPER28 3 Pin seings Figure 3. Connecion diagram (op view) GND VDD DRAIN DRAIN CONT FB BR EPT Noe: The copper area for hea dissipaion has o be designed under he DRAIN pins. Table 3. Pin descripion N. Name Funcion 1 GND This pin represens he device ground and he source of he power secion. 2 VDD 3 CONT 4 FB 5 EPT 7,8 DRAIN Supply volage of he conrol secion. This pin also provides he charging curren of he exernal capacior during sar-up ime. Conrol pin. The following funcions can be seleced: 1. curren limi se poin adjusmen. The inernal se defaul value of he cycleby-cycle curren limi can be reduced by connecing o ground an exernal resisor. 2. oupu volage monioring. A volage exceeding 3 V shus he IC down reducing he device consumpion. This funcion is srobed and digially filered for high noise immuniy. Conrol inpu for duy cycle conrol. Inernal curren generaor provides bias curren for loop regulaion. A volage below 0.6 V acivaes he burs-mode operaion. A level close o 3.3 V means ha he device is approaching he cycle-by-cycle over-curren se poin. This pin allows he connecion of an exernal capacior for he exra power managemen. If he funcion is no used, he pin has o be conneced o GND. High volage drain pin. The buil-in high volage swiched sar-up bias curren is drawn from his pin oo. Pins conneced o he meal frame o faciliae hea dissipaion. 4/28

5 Elecrical daa 4 Elecrical daa 4.1 Maximum raings Table 4. Absolue maximum raings Symbol Pin Parameer Min Value Max Uni V DRAIN 7, 8 Drain-o-source (ground) volage 800 V E AV 7, 8 Repeiive avalanche energy (limied by T J = 150 C) 5 mj I AR 7, 8 Repeiive avalanche curren (limied by T J = 150 C) 1.5 A I DRAIN 7, 8 Pulse drain curren 3 A V CONT 3 Conrol inpu pin volage (wih I CONT = 1 ma) -0.3 Self limied V V FB 4 Feed-back volage V V EPT 5 EPT inpu pin volage V V DD 2 Supply volage (I DD = 25 ma) -0.3 Self limied V I DD 2 Inpu curren 25 ma P TOT Power dissipaion a T A < 50 C 1 W T J Operaing juncion emperaure range C T STG Sorage emperaure C 4.2 Thermal daa Table 5. Thermal daa Symbol Parameer Max value Uni R hjp R hja R hja Thermal resisance juncion pin (Dissipaed power = 1 W) Thermal resisance juncion ambien (Dissipaed power = 1 W) Thermal resisance juncion ambien (Dissipaed power = 1 W) 25 C/W 100 C/W 80 (1) C/W 1. When mouned on a sandard single side FR4 board wih 100 mm 2 (0.155 sq in) of Cu (35 µm hick) 5/28

6 Elecrical daa VIPER Elecrical characerisics (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Table 6. Power secion Symbol Parameer Tes condiion Min Typ Max Uni V BVDSS I OFF R DS(on) C OSS Break-down volage OFF sae drain curren Drain-source on sae resisance Effecive (energy relaed) oupu capaciance I DRAIN = 1 ma, V FB = GND T J = 25 C V DRAIN = max raing, V FB = GND I DRAIN = 0.4 A, V FB = 3 V, V EPT = GND, T J = 25 C I DRAIN = 0.4 A, V FB = 3 V, V EPT = GND, T J = 125 C 800 V 60 μa 7 Ω 14 Ω V DRAIN = 0 o 640 V 40 pf Table 7. Supply secion Symbol Parameer Tes condiion Min Typ Max Uni Volage V DRAIN_START Drain-source sar volage V I DDch Sar up charging curren V DRAIN = 120 V, V EPT = GND, V FB = GND, V DD = 4 V ma V DRAIN = 120 V, V EPT = GND, V FB = GND, V DD = 4 V afer faul ma V DD Operaing volage range Afer urn-on V V DDclamp V DD clamp volage I DD = 20 ma 23.5 V V DDon V DDoff V DD(RESTART) Curren V DD sar up hreshold V DD under volage shudown hreshold V DD resar volage hreshold V DRAIN = 120 V, V EPT = GND, V FB = GND V DRAIN = 120 V, V EPT = GND, V FB = GND V V V I DD0 I DD1 I DD_FAULT I DD_OFF Operaing supply curren, no swiching Operaing supply curren, swiching Operaing supply curren, wih proecion ripping V FB = GND, F SW = 0 khz, V EPT = GND, V DD = 10 V V DRAIN = 120 V, F SW = 60 khz V DRAIN = 120 V, F SW = 115 khz 0.9 ma 2.5 ma 3.5 ma 400 ua Operaing supply curren wih V DD < V DD_OFF V DD = 7 V 270 ua 6/28

7 Elecrical daa Table 8. Conroller secion (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Symbol Parameer Tes condiion Min Typ Max Uni Feed-back pin V FBolp Over-load shu down hreshold V V FBlin Linear dynamics upper limi V V FBbm Burs mode hreshold Volage falling 0.6 V V FBbmhys Burs mode hyseresis Volage rising 100 mv I FB Feed-back sourced curren V FB = 0.3 V ua 3.3 V < V FB < 4.8 V -3 ua R FB(DYN) Dynamic resisance V FB < 3.3 V kω H FB ΔV FB / ΔI D 2 6 V/A CONT pin VCONT_l Low level clamp volage I CONT = -100 µa 0.5 V Curren limiaion I Dlim Max drain curren limiaion V FB = 4 V, I CONT = -10 µa T J = 25 C A SS Sof-sar ime 8.5 ms T ON_MIN Minimum urn ON ime ns d Propagaion delay 100 ns LEB Leading edge blanking 300 ns I D_BM Peak drain curren during burs mode V FB = 0.6 V 160 ma Oscillaor secion VIPER28L F OSC VIPER28H V DD = operaing volage range, V FB = 1 V khz khz FD Modulaion deph VIPER28L ±4 khz VIPER28H ±8 khz FM Modulaion frequency 250 Hz D MAX Maximum duy cycle % 7/28

8 Elecrical daa VIPER28 Table 8. Conroller secion (coninued) (T J = -25 o 125 C, V DD = 14 V; unless oherwise specified) Symbol Parameer Tes condiion Min Typ Max Uni Over-curren proecion (2 nd OCP) I DMAX Second over-curren hreshold 1.2 A Over-volage proecion V OVP T STROBE Over-volage proecion hreshold Over-volage proecion srobe ime V 2.2 us Exra power managemen I DLIM_EPT Drain curren limi wih EPT funcion EPT shu down hreshold I CONT < -10 μa T J = 25 C 85% IDLIM V EPT(STOP) 4 V V EPT(RESTART) EPT resar hreshold I CONT < -10 μa 0.6 V I EPT Sourced EPT curren 5 μa Thermal shudown A T SD T HYST Thermal shudown emperaure Thermal shudown hyseresis C 30 C 8/28

9 Elecrical daa Figure 4. Minimum urn-on ime es circui EPT Figure 5. OVP hreshold es circuis EPT (The OVP proecion is riggered afer four consecuive oscillaor cycles) 9/28

10 Typical elecrical characerisics VIPER28 5 Typical elecrical characerisics Figure 6. Curren limi vs T J Figure 7. Swiching frequency vs T J Figure 8. Drain sar-up volage vs T J Figure 9. HFB vs T J Figure 10. Operaing supply curren (no swiching) vs T J Figure 11. Operaing supply curren (swiching) vs T J 10/28

11 Typical elecrical characerisics Figure 12. Curren limi vs R LIM Figure 13. Power MOSFET on-resisance vs T J Figure 14. Power MOSFET break down volage vs T J 11/28

12 Typical elecrical characerisics VIPER28 Figure 15. Thermal shudown T J T SD T HYST V DD V DD ON V DD OFF V DD RESTART V DS 12/28

13 Typical circui 6 Typical circui Figure 16. Min-feaures flyback applicaion EPT Figure 17. Full-feaure flyback applicaion EPT 13/28

14 Operaion descripions VIPER28 7 Operaion descripions VIPER28 is a high-performance low-volage PWM conroller chip wih an 800 V, avalanche rugged power secion. The conroller includes: he oscillaor wih jiering feaure, he sar up circuis wih sof-sar feaure, he PWM logic, he curren limi circui wih adjusable se poin, he second over-curren circui, he burs mode managemen circui, he EPT circui, he UVLO circui, he auo-resar circui and he hermal proecion circui. The curren limi se-poin is se by he CONT pin. The burs mode operaion guaranies high performance in he sand-by mode and helps in he energy saving norm accomplishmen. All he faul proecions are buil in auo resar mode wih very low repeiion rae o preven IC's overheaing. 7.1 Power secion and gae driver The power secion is implemened wih an avalanche ruggedness n-channel power MOSFET, which guaranees safe operaion wihin he specified energy raing as well as high dv/d capabiliy. The power secion has a BV DSS of 800 V min. and a ypical R DS(on) of 7 Ω a 25 C. The inegraed SenseFET srucure allows a virually loss-less curren sensing. The gae driver is designed o supply a conrolled gae curren during boh urn-on and urnoff in order o minimize common mode EMI. Under UVLO condiions an inernal pull-down circui holds he gae low in order o ensure ha he Power secion canno be urned on accidenally. 7.2 High volage sarup generaor The HV curren generaor is supplied hrough he DRAIN pin and i is enabled only if he inpu bulk capacior volage is higher han V DRAIN_START hreshold, 80 V DC ypically. When he HV curren generaor is ON, he I DDch curren (3 ma ypical value) is delivered o he capacior on he V DD pin. In case of Auo Resar mode afer a faul even, he I DDch curren is reduced o 0.6 ma, yp. in order o have a slow duy cycle during he resar phase. See Figure 18 on page /28

15 Operaion descripions 7.3 Power-up and sof-sar up If he inpu volage rises up ill he device sar level (V DRAIN_START ), he V DD volage begins o grow due o he I DDch curren (see Table 6 on page 6) coming from he inernal high volage sar up circui. If he V DD volage reaches V DDon hreshold (~14 V) he power MOSFET sars swiching and he HV curren generaor is urned OFF. See Figure 19 on page 16. The IC is powered by he energy sored in he capacior on he VDD Pin, C VDD, unil he selfsupply circui (ypically an auxiliary winding of he ransformer and a seering diode) develops a volage high enough o susain he operaion. C VDD capacior mus be sized enough o avoid fas discharge and keep he needed volage value higher han V DDoff hreshold: a oo low capaciance value could erminae he swiching operaion before he conroller receives any energy from he auxiliary winding. The following formula can be used for he V DD capacior calculaion: Equaion 1 I C DDch SSaux VDD = V DDon V DDoff The SSaux is he ime needed for he seady sae of he auxiliary volage. This ime is esimaed by applicaor according o he oupu sage configuraions (ransformer, oupu capaciances, ec.). During he converer sar up ime, he drain curren limiaion is progressively increased o he maximum value. In his way he sress on he secondary diode is considerably reduced. I also helps o preven ransformer sauraion. The sof-sar ime lass 8.5 ms and he feaure is implemened for every aemp of sar up converer or afer a faul. See Figure 20 on page 16. Figure 18. Sar up I DD curren I DD V DS = 120V F SW = 0 khz 2 ma AFTER FAULT 1 ma IDD0 I DD_FAULT IDD_OFF IDS_CH_FAULT -1 ma V DDresar V DDoff V DDon V DD -2 ma -3 ma IDS_CH -4 ma 15/28

16 Operaion descripions VIPER28 Figure 19. Timing diagram: normal power-up and power-down sequences Vin V Sar V DD Vcc V Vcc DD ON V Vcc DD OFF regulaion is los here V Vcc DD resar V DRAIN I DDch I charge 3 ma Power -on Normal operaion Power - off Figure 20. Sof-sar: iming diagram IDRAIN ss IDLIM VFB V FB OLP V FB_lin 16/28

17 Operaion descripions 7.4 Power down operaion A converer power down, he sysem loses regulaion as soon as he inpu volage is so low ha he peak curren limiaion is reached. The V DD volage drops and when i falls below he V DDoff hreshold (8 V ypical) he power MOSFET is swiched OFF, he energy ransfer o he IC is inerruped and consequenly he V DD volage coninues o decreases, Figure 19 on page 16. Laer, if he V IN is lower han V DRAIN_START (80 V ypical), he sar up sequence is inhibied and he power down compleed. This feaure is useful o preven converer s resar aemps and ensures monoonic oupu volage decay during he sysem power down. 7.5 Auo resar operaion If afer a converer power down, he V IN is higher han V DRAIN_START, he sar up sequence is no inhibied and will be acivaed only when he V DD volage drops down he V DDresar hreshold (4.5 V ypical). This means ha he HV sar up curren generaor resars he V DD capacior charging only when he V DD volage drops below V DDresar. The scenario above described is for insance a power down because of a faul condiion. Afer a faul condiion, he charging curren is 0.6 ma (yp.) insead of he 3 ma (yp.) of a normal sar up converer phase. This feaure ogeher wih he low V DDresar hreshold (4.5 V) ensures ha, afer a faul, he resar aemps of he IC has a very long repeiion rae and he converer works safely wih exremely low power hroughpu. The Figure 21 shows he IC behavioral afer a shor circui even. Figure 21. Timing diagram: behavior afer shor circui Shor circui occurs here V DD V DDon V DDoff V DD(RESTART) VDS Trep < 0.03Trep IDD_CH 0.6 ma FB Pin 4.8 V 3.3 V 17/28

18 Operaion descripions VIPER Oscillaor The swiching frequency is inernally fixed o 60 khz or 115 khz. In boh case he swiching frequency is modulaed by approximaely ±4 khz (60 khz version) or ±8 khz (115 khz version) a 250 Hz (ypical) rae, so ha he resuling spread-specrum acion disribues he energy of each harmonic of he swiching frequency over a number of side-band harmonics having he same energy on he whole bu smaller ampliudes. 7.7 Curren mode conversion wih adjusable curren limi se poin The device is a curren mode converer: he drain curren is sensed and convered in volage ha is applied o he non invering pin of he PWM comparaor. This volage is compared wih he one on he feed-back pin hrough a volage divider on cycle by cycle basis. The VIPER28 has a defaul curren limi value, I DLIM, ha he designer can adjus according he elecrical specificaion, by he R LIM resisor conneced o he CONT see Figure 12 on page 11. The CONT pin has a minimum curren sunk needed o acivae he I DLIM adjusmen: wihou R LIM or wih high R LIM (i.e. 100 kω) he curren limi is fixed o he defaul value (see I DLIM, Table 8 on page 7). 7.8 Over-volage proecion (OVP) The device can monior he converer oupu volage. This operaion is done by CONT pin during power MOSFET OFF-ime, when he volage generaed by he auxiliary winding racks converer's oupu volage, hrough urn raio N AUX See Figure 22. In order o perform he oupu volage monior, he CONT pin has o be conneced o he aux winding hrough a resisor divider made up by R LIM and R OVP (see Figure 17 (R3, R4 are respecively R OVP and R LIM )and Figure 23). If he volage applied o he CONT pin exceeds he inernal 3 V reference for four consecuive imes he conroller recognizes an over-volage condiion. This special feaure uses an inernal couner; ha is o reduce sensiiviy o noise and preven he lach from being erroneously acivaed. see Figure 22 on page 19. The couner is rese every ime he OVP signal is no riggered in one oscillaor cycle. Referring o he Figure 17, he resisors divider raio k OVP will be given by: Equaion 2 N SEC k OVP N AUX N SEC V OVP = ( V OUTOVP + V DSEC ) V DAUX 18/28

19 Operaion descripions Equaion 3 k OVP = R LIM R LIM + R OVP Where: V OVP is he OVP hreshold (see Table 8 on page 7) V OUT OVP is he converer oupu volage value o acivae he OVP se by designer N AUX is he auxiliary winding urns N SEC is he secondary winding urns V DSEC is he secondary diode forward volage V DAUX is he auxiliary diode forward volage R OVP ogeher R LIM make he oupu volage divider Than, fixed R LIM, according o he desired I DLIM, he R OVP can be calculaing by: Equaion 4 1 k OVP R OVP = R LIM k OVP The resisor values will be such ha he curren sourced and sunk by he CONT pin be wihin he raed capabiliy of he inernal clamp. Figure 22. OVP iming diagram V DS VAUX 0 CONT (pin 4) 3V STROBE 2 µs 0.5 µs OVP COUNTER RESET COUNTER STATUS FAULT NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE 19/28

20 Operaion descripions VIPER Abou CONT pin Referring o he Figure 23, hrough he CONT PIN, he below feaures can be implemened: 1. Curren limi se poin 2. Over-volage proecion on he converer oupu volage The Table9 on page20 referring o he Figure 23, liss he exernal resisance combinaions needed o acivae one or plus of he CONT pin funcions. Figure 23. CONT pin configuraion Daux Rov p CONT SOFT START Curr. Lim. BLOCK Curren Limi OCP Comparaor - + To PWM Logic Auxiliary winding Rlim OVP DETECTION LOGIC From SenseFET To OVP Proecion Table 9. CONT pin configuraions Funcion / componen R LIM R OVP D AUX I Dlim reducion See Figure 6 No No OVP 80 KΩ See Equaion 4 Yes I Dlim reducion + OVP See Figure 6 See Equaion 4 Yes 7.10 Feed-back and overload proecion (OLP) The VIPER28 is a curren mode converer: he feedback pin conrols he PWM operaion, conrols he burs mode and acives he overload proecion of he device. Figure 24 on page 22 and Figure 25 show he inernal curren mode srucure. Wih he feedback pin volage beween V FB_bm and V FBlin, (respecively 0.6 V and 3.5 V, ypical values) he drain curren is sensed and convered in volage ha is applied o he non invering pin of he PWM comparaor. This volage is compared wih he one on he feedback pin hrough a volage divider on cycle-by-cycle basis. When hese wo volages are equal, he PWM logic orders he swich off of he power MOSFET. The drain curren is always limied o I DLIM value. In case of overload he feedback pin increases in reacion o his even and when i goes higher han V FBlin he drain curren is limied or o he defaul I DLIM value or he one imposed hrough a resisor a he CONT pin (using he R LIM, see Figure 6 on page 10); he PWM comparaor is disabled. 20/28

21 Operaion descripions A he same ime an inernal curren generaor sars o charge he feedback capacior (C FB ) and when he feedback volage reaches he V FBolp hreshold, he converer is urned off and he sar up phase is acivaed wih reduced value of I charge o 0.6 ma. During he firs sar up phase of he converer, afer he sof-sar up ime (ypical value is 8.5 ms) he oupu volage could force he feedback pin volage o rise up o he V FBolp hreshold ha swiches off he converer iself. To avoid his even, he appropriae feedback nework has o be seleced according o he oupu load. More he nework feedback fixes he compensaion loop sabiliy. The Figure 24 on page 22 and Figure 25 on page 22 show he wo differen feedback neworks. The ime from he overload deecion (VFB = V FBlin ) o he device shudown (VFB = V FBolp ) can be calculaed by C FB value (see Figure 24 on page 22 and Figure 25), using he formula: Equaion 5 V FBolp V FBlin T OLP delay = C FB μA In he Figure 24, he capacior conneced o FB pin (C FB ) is used as par of he circui o compensae he feedback loop bu also as elemen o delay he OLP shu down owing o he ime needed o charge he capacior (see Equaion 5). Afer he sar up ime, 8.5 ms yp value, during which he feedback volage is fixed a V FBlin, he oupu capacior could no be a is nominal value and he conroller inerpreers his siuaion as an overload condiion. In his case, he OLP delay helps o avoid an incorrec device shu down during he sar up face. Owing o he above consideraions, he OLP delay ime mus be long enough o by-pass he iniial oupu volage ransien and check he overload condiion only when he oupu volage is in seady sae. The oupu ransien ime depends from he value of he oupu capacior and from he load. When he value of he C FB capacior calculaed for he loop sabiliy is oo low and canno ensure enough OLP delay, an alernaive compensaion nework can be used and i is showed in Figure 25 on page 22. Using his alernaive compensaion nework, wo poles (f PFB, f PFB1 ) and one zero (f ZFB ) are inroduced by he capaciors C FB and C FB1 and he resisor R FB1. The capacior C FB inroduces a pole (f PFB ) a higher frequency han f ZB and f PFB1. This pole is usually used o compensae he high frequency zero due o he ESR (Equivalen Series Resisor) of he oupu capaciance of he fly-back converer. The mahemaical expressions of hese poles and zero frequency, considering he scheme in Figure 25 are repored by he equaions below: Equaion 6 f ZFB 1 = 2 π C FB1 R FB1 21/28

22 Operaion descripions VIPER28 Equaion 7 f PFB R = 2 π C FB(DYN) FB + R FB1 ( R R ) FB(DYN) FB1 Equaion 8 PFB1 The R FB(DYN) is he dynamic resisance seen by he FB pin and repored on Table 8 on page 7. The C FB1 capacior fixes he OLP delay and usually C FB1 resuls much higher han C FB. The equaion Equaion 5 can be sill used o calculae he OLP delay ime bu C FB1 has o be considered insead of C FB. Using he alernaive compensaion nework, he designer can saisfy, in all case, he loop sabiliy and he enough OLP delay ime alike. Figure 24. FB pin configuraion f = 2 π C FB1 1 ( R + R ) FB1 FB(DYN) PWM CONTROL From sense FET PWM To PWM Logic + - Cfb BURST-MODE REFERENCES BURST-MODE LOGIC BURST OLP comparaor + To disable logic 4.8V - Figure 25. FB pin configuraion PWM CONTROL From sense FET PWM To PWM Logic + - Rfb1 Cfb1 Cfb BURST-MODE REFERENCES BURST-MODE LOGIC BURST OLP comparaor + To disable logic 4.8V - 22/28

23 Operaion descripions 7.11 Burs-mode operaion a no load or very ligh load When he load decrease he feedback loop reacs lowering he feedback pin volage. As he volage reach he burs mode hreshold V FBbm MOSFET sops swiching. Afer he MOSFET sops, as a resul of he feedback reacion o he energy delivery sop, he feedback pin volage increases and exceeding V FBbm hreshold of 100 mv, he burs mode hyseresis ypical value MOSFET he power device sar swiching again. Figure 26 shows his behavior called burs mode. Sysems alernaes period of ime where power MOSFET is swiching o period of ime where power MOSFET is no swiching. The power delivered o oupu during swiching periods exceeds he load power demands; he excess of power is balanced from no swiching period where no power is processed. The advanage of burs mode operaion is an average swiching frequency much lower hen he normal operaion working frequency, up o some hundred of herz, minimizing all frequency relaed losses. During he burs mode operaion he drain curren is limied o I D_BM, 160 ma yp. value. Figure 26. Burs mode iming diagram, ligh load managemen FB VFBBM mv hyser. I DS Normal - mode Burs-mode Normal - mode 7.12 Exra power managemen funcion (EPT) Some applicaions need an exra power for a limied ime window during which he converer regulaion has o be guaraneed. The exra power managemen funcion allows o design a converer ha can saisfy his reques and is provided by he EPT pin, see Table 8 on page 8. This funcion requires he use of a capacior on EPT pin (C EPT ) ha is charged or discharged by means of a 5 µa curren cycle by cycle. When he drain curren raises over 85 % of Idlim value, see I DLIM_EPT (Table 8 on page 7), he curren generaor charges C EPT while when he drain curren is below I DLIM_EPT discharges he capacior. If C EPT s volage reaches he V EPT hreshold (ypical, 4 V), he converer is shu down. Afer he converer shu down, he V DD volage will drop below he V DD(ON) sar up hreshold (yp V) and according o he auo resar operaion (see Secion 7.5 on page 17) he VDD pin volage have o fall below he V DD(RESTART) hreshold (ypical, 4.5 V) in order o charge again he V DD capacior. Moreover he PWM operaion is enabled again only when he volage on EPT pin, drop below he V EPT(RESTART) (ypical, 0.6 V). The low C EPT discharge curren in combinaion wih is low resar hreshold, 23/28

24 Operaion descripions VIPER28 ensures safe operaions and avoids overheaing in case of repeaed overload evens. The value of C EPT has o be seleced in order o preven he device overheaing. The EPT pin can be conneced o GND if he funcion is no used nd level over-curren proecion and hiccup mode The VIPER28 is proeced agains shor circui of he secondary recifier, shor circui on he secondary winding or a hard-sauraion of fly-back ransformer. Such as anomalous condiion is invoked when he drain curren exceed 1 A ypical. To disinguish a real malfuncion from a disurbance (e.g. induced during ESD ess) a warning sae is enered afer he firs signal rip. If in he subsequen swiching cycle he signal is no ripped, a emporary disurbance is assumed and he proecion logic will be rese in is idle sae; oherwise if he 2 nd OCP hreshold is exceeded for wo consecuive swiching cycles a real malfuncion is assumed and he power MOSFET is urned OFF. The shudown condiion is lached as long as he device is supplied. While i is disabled, no energy is ransferred from he auxiliary winding; hence he volage on he V DD capacior decays ill he V DD under volage hreshold (V DDoff ), which clears he lach. The sar up HV curren generaor is sill off, unil V DD volage goes below is resar volage, V DD(RESTART). Afer his condiion he V DD capacior is charged again by 600 µa curren, and he converer swiching resar if he V DDon occurs. If he faul condiion is no removed he device eners in auo-resar mode. This behavioral, resuls in a low-frequency inermien operaion (Hiccup-mode operaion), wih very low sress on he power circui. See he iming diagram of Figure 27. Figure 27. Hiccup-mode OCP: iming diagram V DD Vcc V DD ON V DD OFF Secondary diode is shored here V Vccres DD IDRAIN IDmax VDS 24/28

25 Package mechanical daa 8 Package mechanical daa In order o mee environmenal requiremens, ST offers hese devices in differen grades of ECOPACK packages, depending on heir level of environmenal compliance. ECOPACK specificaions, grade definiions and produc saus are available a: ECOPACK is an ST rademark. Table 10. Dim. DIP-7 mechanical daa mm Typ Min Max A 5,33 A1 0,38 A2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 D 9,27 9,02 10,16 E 7,87 7,62 8,26 E1 6,35 6,10 7,11 e 2,54 ea 7,62 eb 10,92 L 3,30 2,92 3,81 M (6)(8) 2,508 N 0,50 0,40 0,60 N1 0,60 O (7)(8) 0, The leads size is comprehensive of he hickness of he leads finishing maerial. 2- Dimensions do no include mold prorusion, no o exceed 0,25 mm in oal (boh side). 3- Package ouline exclusive of meal burrs dimensions. 4- Daum plane H coinciden wih he boom of lead, where lead exis body. 5- Ref. POA MOTHER doc Creepage disance > 800 V 7- Creepage disance 250 V 8- Creepage disance as shown in he CEI / IEC sandard. 25/28

26 Package mechanical daa VIPER28 Figure 28. Package dimensions 26/28

27 Revision hisory 9 Revision hisory Table 11. Documen revision hisory Dae Revision Changes 30-Sep Iniial release 22-Jan Updaed Figure 3 on page 4 27/28

28 Please Read Carefully: Informaion in his documen is provided solely in connecion wih ST producs. STMicroelecronics NV and is subsidiaries ( ST ) reserve he righ o make changes, correcions, modificaions or improvemens, o his documen, and he producs and services described herein a any ime, wihou noice. All ST producs are sold pursuan o ST s erms and condiions of sale. Purchasers are solely responsible for he choice, selecion and use of he ST producs and services described herein, and ST assumes no liabiliy whasoever relaing o he choice, selecion or use of he ST producs and services described herein. No license, express or implied, by esoppel or oherwise, o any inellecual propery righs is graned under his documen. If any par of his documen refers o any hird pary producs or services i shall no be deemed a license gran by ST for he use of such hird pary producs or services, or any inellecual propery conained herein or considered as a warrany covering he use in any manner whasoever of such hird pary producs or services or any inellecual propery conained herein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK. Resale of ST producs wih provisions differen from he saemens and/or echnical feaures se forh in his documen shall immediaely void any warrany graned by ST for he ST produc or service described herein and shall no creae or exend in any manner whasoever, any liabiliy of ST. ST and he ST logo are rademarks or regisered rademarks of ST in various counries. Informaion in his documen supersedes and replaces all informaion previously supplied. The ST logo is a regisered rademark of STMicroelecronics. All oher names are he propery of heir respecive owners STMicroelecronics - All righs reserved STMicroelecronics group of companies Ausralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ialy - Japan - Malaysia - Mala - Morocco - Singapore - Spain - Sweden - Swizerland - Unied Kingdom - Unied Saes of America 28/28