COMP VFF TIME OUT OFF2 LOW CLAMP & DISABLE LINE VOLTAGE FEEDFORWARD. Ref erence voltages Internal supply. Vth. 400 ua 5.7V BURST-MODE R Q S

Transcription

1 Mulimode conroller for SMPS Daashee producion daa Feaures Selecable mulimode operaion: fixed frequency or quasi-resonan On-board 840 V high volage sarup Advanced ligh load managemen Low quiescen curren (< 3 ma) Adapive UVLO Line feedforward for consan power capabiliy vs. mains volage Pulse-by-pulse OCP, shudown on overload (lached or auo-resar) Transformer sauraion deecion Programmable frequency modulaion for EMI reducion Lached or auo-resar OVP Brownou proecion Figure 1. Block diagram -600/+800 ma oem pole gae driver wih acive pull-down during UVLO SO16N package Applicaions Indusrial SMPS SO16N SMPS running off recified 3-phase inpu line VREF SS COMP VFF HV VCC 1 IHV 5 10 VOLTAGE REGULATOR & ADAPTIVE UVLO 14 SOFT-START & FAULT MNGT Ref erence volages Inernal supply UVLO TIME OUT VCC 9 15 LOW CLAMP & DISABLE Vh OFF2 LINE VOLTAGE FEEDFORWARD - + PWM OVP - + OCP VCC V 6.4V I charge V Q VCC LEB OVPL 7 CS FMOD OSC MODE/SC ZCD mv 100 mv 11 OSCILLATOR - + UVLO_SHF - + ZERO CURRENT DETECTOR MODE SELECTION & TURN-ON LOGIC OVERVOLTAGE PROTECTION 400 ua 5.7V OVP + - BURST-MODE TIME OUT OVPL LATCH IC_LATCH R Q S OFF2 Hiccup-mode OCP logic OCP2 DRIVER 14V V + 8 GD DIS AC_OK 16 3 V 15 µa 0.450V 0.485V - + AC_FAIL UVLO DISABLE 3 April 2012 Doc ID Rev 2 1/51 This is informaion on a produc in full producion. 51

2 Conens Conens 1 Descripion Pin seings Connecions Pin descripion Elecrical daa Maximum raing Thermal daa Elecrical characerisics Applicaion informaion High volage sarup generaor Zero-curren deecion and riggering block; oscillaor block Burs-mode operaion a no load or very ligh load Adapive UVLO PWM conrol block PWM comparaor, PWM lach and volage feedforward blocks Hiccup-mode OCP Frequency modulaion Lached disable funcion Sof-sar and delayed lached shudown upon overcurren OVP block Brownou proecion Slope compensaion Summary of power managemen funcions Applicaion examples and ideas /51 Doc ID Rev 2

3 Conens 7 Package mechanical daa Order codes Revision hisory Doc ID Rev 2 3/51

4 Lis of ables Lis of ables Table 1. Pin funcions Table 2. Absolue maximum raings Table 3. Thermal daa Table 4. Elecrical characerisics Table 5. ligh load managemen feaures Table 6. proecion Table 7. Exernal circuis ha deermine IC behavior upon OVP and OCP Table 8. SO16N mechanical daa Table 9. Order codes Table 10. Documen revision hisory /51 Doc ID Rev 2

5 Lis of figures Lis of figures Figure 1. Block diagram Figure 2. Typical sysem block diagram Figure 3. Pin connecion (hrough op view) Figure 4. Mulimode operaion wih QR opion acive Figure 5. High volage sarup generaor: inernal schemaic Figure 6. Timing diagram: normal power-up and power-down sequences Figure 7. Timing diagram showing shor-circui behavior (SS pin clamped a 5 V) Figure 8. V HV raing vs. emperaure Figure 9. Drain ringing cycle skipping as he load is gradually reduced Figure 10. Operaion of ZCD, riggering and oscillaor blocks (QR opion acive) Figure 11. Load-dependen operaing modes: iming diagrams Figure 12. Addiion of an offse o he curren sense lowers he burs-mode operaion hreshold Figure 13. Adapive UVLO block Figure 14. Possible feedback configuraions ha can be used wih he Figure 15. Exernally conrolled burs-mode operaion by driving he COMP pin: iming diagram Figure 16. Typical power capabiliy change vs. inpu volage in QR flyback converers Figure 17. Lef: overcurren sepoin vs. VFF volage; righ: line feedforward funcion block Figure 18. Hiccup-mode OCP: iming diagram Figure 19. Frequency modulaion circui Figure 20. Operaion afer lached disable acivaion: iming diagram Figure 21. Sof-sar pin operaion under differen operaing condiions and seings Figure 22. OVP funcion: inernal block diagram Figure 23. OVP funcion: iming diagram Figure 24. Maximum allowed duy cycle vs. swiching frequency for correc OVP deecion Figure 25. Brownou proecion: inernal block diagram and iming diagram Figure 26. Volage sensing echniques o implemen brownou proecion wih he Figure 27. Slope compensaion waveforms Figure 28. Typical low-cos applicaion schemaic Figure 29. Typical full-feaure applicaion schemaic (QR operaion) Figure 30. Typical full-feaure applicaion schemaic (FF operaion) Figure 31. Frequency foldback a ligh load (FF operaion) Figure 32. Lached shudown upon mains overvolage Figure 33. SO16N package drawing Figure 34. Recommended fooprin (dimensions are in mm) Doc ID Rev 2 5/51

6 Descripion 1 Descripion The is an exremely versaile curren-mode primary conroller IC, specifically designed for high-performance offline flyback converers running off recified 3-phase inpu lines. I is also suied o single-sage, single-swich, inpu-curren-shaping converers (single-sage PFC) for applicaions ha mus comply wih EN or JEITA-MITI regulaions. Boh fixed-frequency (FF) and quasi-resonan (QR) operaion are suppored. The user can choose eiher of he wo depending on applicaion needs. The device feaures an exernally programmable oscillaor: i defines he converer swiching frequency in FF mode and he maximum allowed swiching frequency in QR mode. When FF operaion is seleced, he ICs work as a sandard curren-mode conroller wih a maximum duy cycle limied o 70% min. The oscillaor frequency can be modulaed o miigae EMI emissions. QR operaion, when seleced, occurs a heavy load and is achieved hrough a ransformer demagneizaion sensing inpu ha riggers MOSFET urn-on. Under some condiions, ZVS (zero-volage swiching) can be achieved. The converer s power capabiliy rise wih he mains volage is compensaed by line volage feedforward. A medium and ligh load, as he QR operaing frequency equals he oscillaor frequency, a funcion (valley skipping) is acivaed o preven furher frequency rise and keep he operaion as close o ZVS as possible. Wih eiher FF or QR operaion, a very ligh load he ICs ener a conrolled burs-mode operaion ha, along wih he buil-in, non-dissipaive, high-volage sarup circui and he low quiescen curren, helps keep he consumpion from he mains low and mee energy saving recommendaions. An innovaive adapive UVLO helps minimize he issues relaed o he flucuaions of he self-supply volage due o ransformer parasies. The proecion funcions included in his device are: no-lached inpu undervolage (brownou), oupu OVP (auo-resar or lach-mode selecable), a firs-level OCP wih delayed shudown o proec he sysem during overload or shor-circui condiions (auoresar or lach-mode selecable), and a second-level OCP ha is invoked when he ransformer sauraes or here is a shor-circui of he secondary diode. A lached disable inpu allows easy implemenaion of OTP wih an exernal NTC, while an inernal shudown prevens IC overheaing. Programmable sof-sar, leading-edge blanking on he curren sense inpu for greaer noise immuniy, slope compensaion (in FF mode only), and a shudown funcion for exernally conrolled burs-mode operaion or remoe ON/OFF conrol complee he feaures of his device. 6/51 Doc ID Rev 2

7 Descripion Figure 2. Typical sysem block diagram FLYBACK DC-DC CONVERTER Recified & Filered Mains Volage Voudc Doc ID Rev 2 7/51

8 Pin seings 2 Pin seings 2.1 Connecions Figure 3. Pin connecion (hrough op view) HVS 1 16 AC_OK N.C VFF GND 3 14 SS GD 4 13 OSC Vcc 5 12 MODE/SC FMOD 6 11 ZCD CS 7 10 VREF DIS 8 9 COMP AM11479v1 2.2 Pin descripion Table 1. Pin funcions N Pin Funcion 1 HVS 2 N.C. 3 GND 4 GD High volage sarup. The pin, able o wihsand 840 V, is o be ied direcly o he recified mains volage. A 1 ma inernal curren source charges he capacior conneced beween he Vcc pin (5) and GND pin (3) unil he volage on he Vcc pin reaches he urn-on hreshold, i is hen shu down. Normally, he generaor is reenabled when he Vcc volage falls below 5 V o ensure a low power hroughpu during shor-circui. Oherwise, when a lached proecion is ripped he generaor is re-enabled 0.5 V below he urn-on hreshold, o keep he lach supplied; or, when he IC is urned off by he COMP pin (9) pulled low, he generaor is acive jus below he UVLO hreshold o allow a faser resar. No inernally conneced. Provision for clearance on he PCB o mee safey requiremens. Ground. Curren reurn for boh he signal par of he IC and he gae drive. All of he ground connecions of he bias componens should be ied o a rack going o his pin and kep separae from any pulsed curren reurn. Gae driver oupu. The oem pole oupu sage is able o drive Power MOSFETs and IGBTs wih a peak curren capabiliy of 800 ma source/sink. 8/51 Doc ID Rev 2

9 Pin seings Table 1. Pin funcions (coninued) N Pin Funcion 5 Vcc 6 FMOD 7 CS 8 DIS 9 COMP 10 VREF Supply volage of boh he signal par of he IC and he gae driver. The inernal high volage generaor charges an elecrolyic capacior conneced beween his pin and GND (pin 3) as long as he volage on he pin is below he urn-on hreshold of he IC, afer ha i is disabled and he chip is urned on. The IC is disabled as he volage on he pin falls below he UVLO hreshold. This hreshold is reduced a ligh load o counerac he naural reducion of he self-supply volage. Someimes a small bypass capacior (0.1 µf yp.) o GND migh be useful o obain a clean bias volage for he signal par of he IC. Frequency modulaion inpu. When FF mode operaion is seleced, a capacior conneced from his pin o GND (pin 3) is alernaely charged and discharged by inernal curren sources. As a resul, he volage on he pin is a symmerical riangular waveform wih he frequency relaed o he capaciance value. By connecing a resisor from his pin o pin 13 (OSC) i is possible o modulae he curren sourced by he OSC pin and hen he oscillaor frequency. This modulaion is o reduce he peak value of EMI emissions by means of a spread-specrum acion. If he funcion is no used, he pin is lef open. Inpu o he PWM comparaor. The curren flowing in he MOSFET is sensed hrough a resisor, he resuling volage is applied o his pin and compared wih an inernal reference o deermine MOSFET urn-off. The pin is equipped wih 150 ns min. blanking ime afer he gae-drive oupu goes high for improved noise immuniy. A second comparison level locaed a 1.5 V laches he device OFF and reduces is consumpion in he case of ransformer sauraion or secondary diode shor-circui. The informaion is lached unil he volage on he Vcc pin (5) goes below he UVLO hreshold, herefore resuling in inermien operaion. A logic circui improves sensiiviy o emporary disurbances. IC lached disable inpu. Inernally, he pin connecs a comparaor ha, when he volage on he pin exceeds 4.5 V, laches OFF he IC and brings is consumpion o a lower value. The lach is cleared as he volage on he Vcc pin (5) goes below he UVLO hreshold, bu he HV generaor keeps he Vcc volage high (see pin 1 descripion). I is hen necessary o recycle he inpu power o resar he IC. For a quick resar, pull pin 16 (AC_OK) below he disable hreshold (see pin 16 descripion). Bypass he pin wih a capacior o GND (pin 3) o reduce noise pickup. Ground he pin if he funcion is no used. Conrol inpu for loop regulaion. The pin is driven by he phooransisor (emiergrounded) of an opocoupler o modulae is volage by modulaing he curren sunk. A capacior placed beween he pin and GND (3), as close o he IC as possible o reduce noise pick-up, ses a pole in he oupu-o-conrol ransfer funcion. The dynamics of he pin are in he 2.5 o 5 V range. A volage below an inernally defined hreshold acivaes burs-mode operaion. The volage a he pin is boom-clamped a abou 2 V. If he clamp is exernally overridden and he volage is pulled below 1.4 V, he IC shus down. An inernal generaor furnishes an accurae volage reference (5 V ± 2%) ha can be used o supply few ma o an exernal circui. A small film capacior (0.1 µf yp.), conneced beween his pin and GND (3), is recommended o ensure he sabiliy of he generaor and o preven noise from affecing he reference. This reference is inernally moniored by a separae auxiliary reference and any failure or drif causes he IC o lach OFF. Doc ID Rev 2 9/51

10 Pin seings Table 1. Pin funcions (coninued) N Pin Funcion 11 ZCD 12 MODE/SC 13 OSC 14 SS 15 VFF 16 AC_OK Transformer demagneizaion sensing inpu for quasi-resonan operaion and OVP inpu. The pin is exernally conneced o he ransformer s auxiliary winding hrough a resisor divider. A negaive-going edge riggers MOSFET urn-on if QR mode is seleced. A volage exceeding 5 V shus he IC down and brings is consumpion o a lower value (OVP). Lach OFF or auo-resar mode is selecable exernally. This funcion is srobed and digially filered o increase noise immuniy. Operaing mode selecion. If he pin is conneced o he VREF pin (7), quasiresonan operaion is seleced, he oscillaor (pin 13, OSC) deermines he maximum allowed operaing frequency. Fixed-frequency operaion is seleced if he pin is no ied o VREF, in which case he oscillaor deermines he acual operaing frequency, he maximum allowed duy cycle is se a 70% min. and he pin delivers a volage ramp synchronized o he oscillaor when he gae-drive oupu is high; he volage delivered is zero while he gae-drive oupu is low. The pin is o be conneced o pin CS (7) via a resisor for slope compensaion. Oscillaor pin. The pin is an accurae 1 V volage source, and a resisor conneced from he pin o GND (pin 3) defines a curren. This curren is inernally used o se he oscillaor frequency ha defines he maximum allowed swiching frequency of he, if working in QR mode, or he operaing swiching frequency if working in FF mode. Sof-sar curren source. A sarup, a capacior Css beween his pin and GND (pin 3) is charged wih an inernal curren generaor. During he ramp, he inernal reference clamp on he curren sense pin (7, CS) rises linearly saring from zero o is final value, herefore causing he duy cycle o increase progressively saring from zero as well. During sof-sar he adapive UVLO funcion and all funcions monioring he COMP pin are disabled. The sof-sar capacior is discharged whenever he supply volage of he IC falls below he UVLO hreshold. The same capacior is used o delay IC shudown (lach OFF or auo-resar mode selecable) afer deecing an overload condiion (OLP). Line volage feedforward inpu. The informaion on he converer s inpu volage is fed ino he pin hrough a resisor divider and is used o change he sepoin of he pulse-by-pulse curren limiaion (he higher he volage, he lower he sepoin). The linear dynamics of he pin ranges from 0 o 3 V. A volage higher han 3 V makes he IC sop swiching. If feedforward is no desired, ie he pin o GND (pin 3) direcly if a lach-mode OVP is no required (see pin 11, ZCD) or hrough a 10 kω min. resisor if a lach-mode OVP is required. Bypass he pin wih a capacior o GND (pin 3) o reduce noise pick-up. Brownou proecion inpu. A volage below 0.45 V shus down (no lached) he IC, lowers is consumpion and clears he lach se by lached proecion (DIS > 4.5 V, SS > 6.4 V, VFF > 6.4 V). IC operaion is re-enabled as he volage exceeds 0.45 V. The comparaor is provided wih curren hyseresis: an inernal 15 µa curren generaor is ON as long as he volage on he pin is below 0.45 V and is OFF if his value is exceeded. Bypass he pin wih a capacior o GND (pin 3) o reduce noise pick-up. Tie o Vcc wih a 220 o 680 kw resisor if he funcion is no used. 10/51 Doc ID Rev 2

11 Elecrical daa 3 Elecrical daa 3.1 Maximum raing Table 2. Absolue maximum raings Symbol Pin Parameer Value Uni V HVS 1 Volage range (referred o 25 C -0.3 o 840 V I HVS 1 Oupu curren Self-limied V CC 5 IC supply volage (Icc = 20 ma) Self-limied V FMOD 6 Volage range -0.3 o 2 V V max 7, 8, 10, 14 Analog inpus and oupus -0.3 o 7 V V max 9, 15, 16 Maximum pin volage (Ipin 1 ma) Self-limied I ZCD 11 Zero-curren deecor max. curren ±5 ma V MODE/SC 12 Volage range -0.3 o 5.3 V V OSC 13 Volage range -0.3 o 3.3 V P TOT Power T A = 50 C 0.75 W T STG Sorage emperaure -55 o 150 C T J Juncion operaing emperaure range -40 o 150 C 3.2 Thermal daa Table 3. Thermal daa Symbol Parameer Value Uni R hja Thermal resisance juncion o ambien 120 C/W Doc ID Rev 2 11/51

12 Elecrical characerisics 4 Elecrical characerisics Table 4. (T J = -25 o 125 C, V CC = 12, C O = 1 nf; MODE/SC = V REF, R T = 20 kω from OSC o GND, unless oherwise specified.) Elecrical characerisics Symbol Parameer Tes condiion Min. Typ. Max. Uni Supply volage Vcc Vcc On Vcc Off Operaing range afer urn-on Turn-on hreshold Turn-off hreshold V COMP > V COMPL V V COMP = V COMPO 8 23 (1) V (1) V COMP > V COMPL (1) V V COMP = V COMPO Hys Hyseresis V COMP > V COMPL 4 V V Z Zener volage Icc = 20 ma, IC disabled V Supply curren I sar-up Sarup curren Before urn-on, Vcc = 13 V µa I q Quiescen curren Afer urn-on, V ZCD = V CS = 1 V ma Icc Operaing supply curren MODE/SC open ma I qdis Quiescen curren IC disabled (2) IC lached OFF µa High volage sarup generaor V HV Breakdown volage (3) I HV < C 840 V V HVsar Sar volage I Vcc < 100 µa V I charge Vcc charge curren V HV > V Hvsar, Vcc > 3 V ma I HV, ON ON-sae curren V HV > V Hvsar, Vcc > 3 V 1.6 V HV > V Hvsar, Vcc = I HV, OFF OFF-sae leakage curren V HV = 400 V 40 µa V CCresar Reference volage Vcc resar volage Vcc falling (1) IC lached OFF (1) Disabled by V COMP < V COMPOFF V REF Oupu volage (1) T J = 25 C; I REF = 1 ma V V REF Toal variaion I REF = 1 o 5 ma, Vcc = 10.6 o 23 V V I REF Shor-circui curren V REF = ma ma V 12/51 Doc ID Rev 2

13 Elecrical characerisics Table 4. Elecrical characerisics (coninued) Symbol Parameer Tes condiion Min. Typ. Max. Uni Sink capabiliy in UVLO Vcc = 6 V; Isink = 0.5 ma V V OV Overvolage hreshold V Inernal oscillaor Operaing range f sw Oscillaion frequency T J = 25 C, V ZCD = 0, MODE/SC = open khz Vcc =12 o 23 V, V ZCD = 0, MODE/SC = open V OSC Volage reference (4) V D max Maximum duy cycle MODE/SC = open, V COMP = 5 V % Brownou proecion Vh Threshold volage Volage falling (urn-off) V Volage rising (urn-on) V I Hys Curren hyseresis Vcc > 5 V, V VFF = 0.3 V µa V AC_OK_CL Clamp level (1) I AC_OK = 100 µa V Line volage feedforward I VFF Inpu bias curren V VFF = 0 o 3 V, V ZCD < V ZCDh -1 µa V ZCD > V ZCDh ma V VFF Linear operaion range 0 o 3 V V OFF IC disable volage V V VFFlach Lach OFF/clamp level V ZCD > V ZCDh 6.4 V Kc Conrol volage gain (4) V VFF = 1 V, V COMP = 4 V 0.4 V/V K FF Feedforward gain (3) V VFF = 1 V, V COMP = 4 V 0.04 V/V Curren sense comparaor I CS Inpu bias curren V CS = 0-1 µa LEB Leading edge blanking ns d (H-L) Delay o oupu 100 ns V COMP = V COMPHI, V VFF = 0 V V CSx Overcurren sepoin V COMP = V COMPHI, V VFF = 1.5 V V V COMP = V COMPHI, V VFF = 3.0 V V CSdis Hiccup-mode OCP level (1) V PWM conrol V COMPHI Upper clamp volage I COMP = V Doc ID Rev 2 13/51

14 Elecrical characerisics Table 4. V COMPLO Lower clamp volage I SOURCE = -1 ma 2.0 V V COMPSH Linear dynamics upper limi (1) V VFF = 0 V V I COMP Max. source curren V COMP = 3.3 V µa R COMP Dynamic resisance V COMP = 2.6 o 4.8 V 25 kω (1) V COMPBM Burs-mode hreshold V (1) MODE/SC = open Hys Burs-mode hyseresis 20 mv I CLAMPL Lower clamp capabiliy V COMP = 2 V ma V COMPOFF Disable hreshold Volage falling 1.4 V V COMPO Elecrical characerisics (coninued) Symbol Parameer Tes condiion Min. Typ. Max. Uni Level for lower UVLO OFF hreshold (volage falling) (4) (4) MODE/SC = open V V COMPL Level for higher UVLO OFF hreshold (volage rising) (4) (4) MODE/SC = open V Zero-curren deecor/overvolage proecion V ZCDH Upper clamp volage I ZCD = 3 ma V V ZCDL Lower clamp volage I ZCD = - 3 ma -0.4 V V ZCDA Arming volage (1) Posiive-going edge mv V ZCDT Triggering volage (1) Negaive-going edge mv I ZCD Inernal pull-up V COMP < V COMPSH -1 V ZCD < 2 V, V COMP = V COMPHI µa I ZCDsrc Source curren capabiliy V ZCD = V ZCDL -3 ma I ZCDsnk Sink curren capabiliy V ZCD = V ZCDH 3 ma T BLANK1 Turn-on inhibi ime Afer gae-drive going low 2.5 µs V ZCDh OVP hreshold V T BLANK2 OVP srobe delay Afer gae-drive going low 2 µs Lached shudown funcion I OTP Inpu bias curren V DIS = 0 o V OTP -1 µa V OTP Disable hreshold (1) V Thermal shudown Vh Shudown hreshold 160 C Hys Hyseresis 50 C Exernal oscillaor (frequency modulaion) f FMOD Oscillaion frequency C MOD = 0.1 µf Hz --- Usable frequency range khz 14/51 Doc ID Rev 2

15 Elecrical characerisics Table 4. Elecrical characerisics (coninued) Symbol Parameer Tes condiion Min. Typ. Max. Uni V pk Peak volage (4) 1.5 V V vy Valley volage 0.5 V I FMOD Charge/discharge curren 150 µa Mode selecion / slope compensaion MODE h Threshold for QR operaion 3 V SC pk SC vy Sof-sar Ramp peak (MODE/SC = open) Ramp saring value (MODE/SC = open) Ramp volage (MODE/SC = open) Source capabiliy (MODE/SC = open) R S-COMP = 3 kω o GND, GD pin HIGH, V COMP = 5 V R S-COMP = 3 kω o GND, GD pin HIGH 1.7 V 0.3 V GD pin LOW 0 V V S-COMP = V S-COMPpk 0.8 ma T I J = 25 C, V SS < 2 V, SS V COMP = 4 V Charge curren µa T I J = 25 C, V SS > 2 V, SS V COMP = V COMPHi I SSdis Discharge curren V SS > 2 V µa V SSclamp High sauraion volage V COMP = 4 V 2 V V SSDIS Disable level (1) V COMP = V COMPHi V V SSLAT Lach OFF level V COMP = V COMPHi 6.4 V Gae driver V GDH Oupu high volage I GDsource = 5 ma, Vcc = 12 V V V GDL Oupu low volage I GDsink = 100 ma 0.75 V I sourcepk Oupu source peak curren -0.6 A I sinkpk Oupu sink peak curren 0.8 A f Fall ime 40 ns r Rise ime 50 ns V GDclamp Oupu clamp volage I GDsource = 5 ma; Vcc = 20 V V UVLO sauraion Vcc = 0 o Vccon, Isink = 1 ma V 1. Parameers racking one anoher. 2. See Table 6 on page 18 and Table 7 on page For he hermal behavior, refer o Figure The volage feedforward block oupu is given by: Doc ID Rev 2 15/51

16 Applicaion informaion 5 Applicaion informaion The is a versaile peak-curren-mode PWM conroller specific o offline flyback converers. The device allows eiher fixed-frequency (FF) or quasi-resonan (QR) operaion, selecable wih he MODE/SC pin (12): forcing he volage on he pin over 3 V (e.g. by ying i o he 5 V reference exernally available a he VREF pin, 10) acivaes QR operaion, oherwise he device is FF-operaed. Irrespecive of he operaing opion seleced by pin 12, he device is able o work in differen modes, depending on he converer s load condiions. If QR operaion is seleced (see Figure 4): 1. QR mode a heavy load. Quasi-resonan operaion lies in synchronizing MOSFET urnon o he ransformer s demagneizaion by deecing he resuling negaive-going edge of he volage across any winding of he ransformer. Then, he sysem works close o he boundary beween disconinuous (DCM) and coninuous conducion (CCM) of he ransformer. As a resul, he swiching frequency is differen for differen line/load condiions (see he hyperbolic-like porion of he curves in Figure 4). Minimum urn-on losses, low EMI emission and safe behavior in shor-circui are he main benefis of his kind of operaion. 2. Valley-skipping mode a medium/ ligh load. The exernally programmable oscillaor of he, synchronized o MOSFET urn-on, enables he user o define he maximum operaing frequency of he converer. As he load is reduced, MOSFET urnon no longer occurs on he firs valley bu on he second one, he hird one and so on. In his way he swiching frequency no longer increases (piecewise linear porion in Figure 4). 3. Burs-mode wih no or very ligh load. When he load is exremely ligh or disconneced, he converer eners a conrolled on/off operaion wih consan peak curren. Decreasing he load hen resuls in frequency reducion, which can go down even o few hundred herz, herefore minimizing all frequency-relaed losses and making i easier o comply wih energy saving regulaions or recommendaions. Wih he peak curren very low, no issue of audible noise arises. Figure 4. Mulimode operaion wih QR opion acive f osc Inpu volage f sw Valley-skipping mode Burs-mode Quasi-resonan mode 0 0 P in Pinmax AM11480v1 16/51 Doc ID Rev 2

17 Applicaion informaion If FF operaion is seleced: 1. FF mode from heavy o ligh load. The sysem operaes exacly like a sandard curren mode conrol, a a frequency f sw deermined by he exernally programmable oscillaor: boh DCM and CCM ransformer operaions are possible, depending on wheher he power ha i processes is greaer or less han: Equaion 1 where Vin is he inpu volage o he converer, V R he refleced volage (i.e. he regulaed oupu volage imes he primary-o-secondary urn raio) and Lp he inducance of he primary winding. Pin T is he power level ha marks he ransiion from coninuous o disconinuous operaion mode of he ransformer. 2. Burs-mode wih no or very ligh load. This kind of operaion is acivaed in he same way and resuls in he same behavior as previously described for QR operaion. The is specifically designed for applicaions wih no PFC fron-end; pin 6 (F MOD ) feaures an auxiliary oscillaor ha can modulae he swiching frequency (when FF operaion is seleced) in order o miigae EMI emissions by a spread-specrum acion. 5.1 High volage sarup generaor Figure 5 shows he inernal schemaic of he high volage sarup generaor (HV generaor). I is made up of a high volage N-channel FET, whose gae is biased by a 15 MΩ resisor, wih a emperaure-compensaed curren generaor conneced o is source. Figure 5. High volage sarup generaor: inernal schemaic 15 MW HV 1 Vcc_OK HV_EN IHV CONTROL 5 Vcc Icharge 3 GND AM11481v1 Wih reference o he iming diagram of Figure 6, when power is firs applied o he converer he volage on he bulk capacior (Vin) builds up and, a abou 80 V, he HV generaor is enabled o operae (HV_EN is pulled high) so ha i draws abou 1 ma. This curren, minus he device consumpion, charges he bypass capacior conneced from he Vcc pin (5) o ground and makes is volage rise almos linearly. Doc ID Rev 2 17/51

18 Applicaion informaion Figure 6. Timing diagram: normal power-up and power-down sequences Vin VHVsar Vcc (pin 5) VccON regulaion is los here VccOFF Vccresar GD (pin 4) HV_EN cc_ok Icharge 0.85 ma Power-on Normal operaion Power-off AM11482v1 As he Vcc volage reaches he urn-on hreshold (14 V yp.) he device sars operaing and he HV generaor is cu off by he Vcc_OK signal assered high. The device is powered by he energy sored in he Vcc capacior unil he self-supply circui (ypically an auxiliary winding of he ransformer and a seering diode) develops a volage high enough o susain he operaion. The residual consumpion of his circui is jus he one on he 15 MΩ resisor ( 10 mw a 400 Vdc), ypically imes lower, under he same condiions, as compared o a sandard sarup circui made wih exernal dropping resisors. A converer power-down he sysem loses regulaion as soon as he inpu volage is so low ha eiher peak curren or maximum duy cycle limiaion is ripped. Vcc hen drops and sops IC aciviy as i falls below he UVLO hreshold (10 V yp.). The V CC _OK signal is deassered as he Vcc volage goes below a hreshold V CCres locaed a abou 5 V. The HV generaor can now resar. However, if Vin < Vin sar, as illusraed in Figure 6, HV_EN is deassered oo and he HV generaor is disabled. This prevens converer resar aemps and ensures monoonic oupu volage decay a power-down in sysems where brownou proecion (see he relevan secion) is no used. The low resar hreshold V CCres ensures ha, during shor-circuis, he resar aemps of he device have a very low repeiion rae, as shown in he iming diagram of Figure 7, and ha he converer works safely wih exremely low power hroughpu. 18/51 Doc ID Rev 2

19 Applicaion informaion Figure 7. Timing diagram showing shor-circui behavior (SS pin clamped a 5 V) Vcc (pin 5) VccON Shor circui occurs here VccOFF Vccresar GD (pin 4) Trep < 0.03Trep Vcc_OK Icharge 0.85 ma AM11483v1 Figure 8. V HV raing vs. emperaure VHV 25 C) Tj ( C) AM11484v1 5.2 Zero-curren deecion and riggering block; oscillaor block The zero-curren deecion (ZCD) and riggering blocks swich on he exernal MOSFET if a negaive-going edge falling below 50 mv is applied o he inpu (pin 11, ZCD). To do so, he riggering block mus be previously armed by a posiive-going edge exceeding 100 mv. This feaure is ypically used o deec ransformer demagneizaion for QR operaion, where he signal for he ZCD inpu is obained from he ransformer s auxiliary winding used also o supply he. The riggering block is blanked for T BLANK = 2.5 µs afer MOSFET Doc ID Rev 2 19/51

20 Applicaion informaion urn-off o preven any negaive-going edge ha follows leakage inducance demagneizaion from riggering he ZCD circui erroneously. The volage a he pin is boh op and boom limied by a double clamp, as illusraed in he inernal diagram of he ZCD block of Figure 8. The upper clamp is ypically locaed a 5.7 V, while he lower clamp is locaed a -0.4 V. The inerface beween he pin and he auxiliary winding is a resisor divider. Is resisance raio is properly chosen (see Secion 5.11: OVP block) and he individual resisance values (R Z1, R Z2 ) are such ha he curren sourced and sunk by he pin is wihin he raed capabiliy of he inernal clamps (± 3 ma). A converer power-up, when no signal is coming from he ZCD pin, he oscillaor sars up he sysem. The oscillaor is programmed exernally by means of a resisor (R T ) conneced from he OSC pin (13) o ground. Wih good approximaion he oscillaion frequency f osc is: Equaion 2 f osc 2 10 R T 3 (wih f osc in khz and R T in kω). As he device is urned on, he oscillaor sars immediaely; a he end of he firs oscillaor cycle, he volage on he ZCD pin being zero, he MOSFET is urned on, herefore saring he firs swiching cycle righ a he beginning of he second oscillaor cycle. A any swiching cycle, he MOSFET is urned off as he volage on he curren sense pin (CS, 7) his an inernal reference se by he line feedforward block, and he ransformer sars demagneizaion. If his complees (so a negaive-going edge appears on he ZCD pin) afer a ime exceeding one oscillaion period T osc = 1/f osc from he previous urn-on, he MOSFET is urned on again wih some delay o ensure minimum volage a urn-on and he oscillaor ramp is rese. If, on he oher hand, he negaive-going edge appears before T osc has elapsed, i is ignored and only he firs negaive-going edge afer T osc urns on he MOSFET and synchronizes he oscillaor. In his way one or more drain ringing cycles are skipped ( valley-skipping mode, Figure 9) and he swiching frequency is prevened from exceeding f osc. Figure 9. Drain ringing cycle skipping as he load is gradually reduced VDS VDS VDS TON TFW TV Tosc Tosc Tosc Pin = Pin' (limi condiion) Pin = Pin'' < Pin' Pin = Pin''' < Pin'' AM11485v1 Noe: When he sysem operaes in valley skipping-mode, uneven swiching cycles may be observed under some line/load condiions, due o he fac ha he OFF-ime of he MOSFET is allowed o change wih discree seps of one ringing cycle, while he OFF-ime needed for cycle-by-cycle energy balance may fall in beween. Therefore, one or more longer swiching cycles is compensaed by one or more shorer cycles and vice versa. However, his mechanism is absoluely normal and here is no appreciable effec on he performance of he converer or on is oupu volage. 20/51 Doc ID Rev 2

21 Applicaion informaion If he MOSFET is enabled o urn on bu he ampliude of he signal on he ZCD pin is smaller han he arming hreshold for some reason (e.g. a heavy damping of drain oscillaions, like in some single-sage PFC opologies, or when a urn-off snubber is used), MOSFET urn-on canno be riggered. This is idenical o wha happens a sarup: a he end of he nex oscillaor cycle he MOSFET is urned on, and a new swiching cycle akes place afer skipping no more han one oscillaor cycle. The operaion described so far does no consider he blanking ime T BLANK afer MOSFET urn-off, and acually T BLANK does no come ino play as long as he following condiion is me: Equaion 3 where D is he MOSFET duy cycle. If his condiion is no me, here are no subsanial changes: he ime during which MOSFET urn-on is inhibied is exended beyond T osc by a fracion of T BLANK. As a consequence, he maximum swiching frequency is a lile lower han he programmed value f osc and valley-skipping mode may ake place slighly earlier han expeced. However his is quie unusual: seing f osc = 150 khz, he phenomenon can be observed a duy cycles higher han 60%. See Secion 5.11: OVP block for furher implicaions of T BLANK. If he volage on he COMP pin (9) sauraes high, which reveals an open conrol loop, an inernal pull-up keeps he ZCD pin close o 2 V during MOSFET OFF-ime o preven noise from false riggering he deecion block. When his pull-up is acive, he ZCD pin may no be able o go below he riggering hreshold, which would sop he converer. To allow auoresar operaion, however ensuring minimum operaing frequency in hese condiions, he oscillaor frequency ha reriggers MOSFET urn-on is ha of he exernal oscillaor divided by 128. Addiionally, o preven malfuncion a converer sarup, he pull-up is disabled during he iniial sof-sar (see he relevan secion). However, o ensure a correc sarup, a he end of he sof-sar phase he oupu volage of he converer mus mee he condiion: Equaion 4 T D 1 T Vou > Ns Naux BLANK where Ns is he urn number of he secondary winding, Naux he urn number of he auxiliary winding and I ZCD he maximum pull-up curren (130 µa). The operaion described so far under differen operaing condiions for he converer is illusraed in he iming diagrams of Figure 10. If he FF opion is seleced he operaion is exacly equal o ha of a sandard curren-mode PWM conroller. I works a a frequency fsw = fosc; boh DCM and CCM ransformer operaions are possible, depending on he operaing condiions (inpu volage and oupu load) and on he design of he power sage. The MOSFET is urned on a he beginning of each oscillaor cycle and is urned off as he volage on he curren sense pin reaches an inernal reference se by he line feedforward block. The maximum duy cycle is limied o 70% minimum. The signal on he ZCD pin in his case is used only for deecing feedback loop failures (see Secion 5.11: OVP block). osc R Z I 1 ZCD Doc ID Rev 2 21/51

22 Applicaion informaion Figure 10. Operaion of ZCD, riggering and oscillaor blocks (QR opion acive) ZCD (pin 11) 100 mv 50 mv Oscillaor ramp ZCD (pin 11) 100 mv 50 mv Oscillaor ramp ZCD (pin 11) 100 mv 50 mv Oscillaor ramp ZCD blanking ime ZCD blanking ime ZCD blanking ime Arm/Trigger armed rigger Arm/Trigger Arm/Trigger ON-enable ON-enable ON-enable PWM lach Se PWM lach Se PWM lach Se PWM lach Rese PWM lach Rese PWM lach Rese GD (pin 4) GD (pin 4) GD (pin 4) a) full load b) ligh load c) sar-up AM11486v1 5.3 Burs-mode operaion a no load or very ligh load When he volage a he COMP pin (9) falls 20 mv below a hreshold fixed inernally a a value, V COMPBM, depending on he seleced operaing mode, he is disabled wih he MOSFET kep in OFF-sae and is consumpion reduced o a lower value o minimize V CC capacior discharge. The conrol volage now increases as a resul of he feedback reacion o he energy delivery sop (he oupu volage is slowly decaying), he hreshold is exceeded and he device resars swiching again. In his way he converer works in burs-mode wih a nearly consan peak curren defined by he inernal disable level. A load decrease hen causes a frequency reducion, which can go down even o few hundred herz, herefore minimizing all frequency-relaed losses and making i easier o comply wih energy saving regulaions. This kind of operaion, shown in he iming diagrams of Figure 11 along wih he ohers previously described, is noise-free since he peak curren is low. If i is necessary o decrease he inervenion hreshold of he burs-mode operaion, his can be done by adding a small DC offse on he curren sense pin as shown in Figure 12. Noe: The offse reduces he available dynamics of he curren signal; hereby, he value of he sense resisor mus be deermined aking his offse ino accoun. 22/51 Doc ID Rev 2

23 Applicaion informaion Figure 11. Load-dependen operaing modes: iming diagrams COMP (pin 9) VCOMPBM 20 mv hyser. fosc fsw GD (pin 4) MODE/SC=Open MODE/SC=VREF MODE/SC=Open FF Mode Burs-mode FF Mode MODE/SC=VREF QR Mode Burs-mode QR Mode Valley-skipping Mode AM11487v1 Figure 12. Addiion of an offse o he curren sense lowers he burs-mode operaion hreshold Vcso = Vref R R + Rc Vref Rc R Rs AM11488v1 5.4 Adapive UVLO A major problem when opimizing a converer for minimum no-load consumpion is ha he volage generaed by he auxiliary winding under hese condiions falls considerably as compared even o a few ma load. This very ofen causes he supply volage Vcc of he conrol IC o drop and go below he UVLO hreshold so ha he operaion becomes inermien, which is undesired. Furhermore, his mus be raded off agains he need o generae a volage no exceeding he maximum allowed by he conrol IC a full load. To help he user overcome his problem, he device, besides reducing is own consumpion during burs-mode operaion, also feaures a proprieary adapive UVLO funcion. I consiss of shifing he UVLO hreshold downwards a ligh load, namely when he volage a he COMP pin falls below a hreshold V COMPO inernally fixed, so as o have more headroom. To Doc ID Rev 2 23/51

24 Applicaion informaion preven any malfuncion during ransiens from minimum o maximum load he normal (higher) UVLO hreshold is re-esablished when he volage a he COMP pin exceeds V COMPL and Vcc has exceeded he normal UVLO hreshold (see Figure 13). The normal UVLO hreshold ensures ha a full load he MOSFET is driven wih a proper gae-o-source volage. Figure 13. Adapive UVLO block Vc c VCOMP (pin 9) + 5 VCOMPL VCOMPO - COMP 9 V COMPL V COMPO - + R S Q SW + - UVLO Vcc (pin 5) VccOFF1 VccOFF2 Vcc OFF1 Vcc OFF2 (*) Q (*) VccOFF2< VccOFF1is seleced when Q is high AM11489v1 5.5 PWM conrol block The device is specific o secondary feedback. Typically, here is a TL431 on he secondary side and an opocoupler ha ransfers oupu volage informaion o he PWM conrol on he primary side, crossing he isolaion barrier. The PWM conrol inpu (pin 9, COMP) is driven direcly by he phooransisor s collecor (he emier is grounded o GND) o modulae he duy cycle (Figure 14, lef-hand side circui). In applicaions where a igh oupu regulaion is no required, i is possible o use a primarysensing feedback echnique. In his approach he volage generaed by he self-supply winding is sensed and regulaed. This soluion, shown in Figure 14, righ-hand side circui, is cheaper because no opocoupler or secondary reference is needed, bu oupu volage regulaion, especially as a resul of load changes, is quie poor. Figure 14. Possible feedback configuraions ha can be used wih he 9 Vou 5 Vcc COMP 9 Cs COMP Naux TL431 Secondary feedback Primary feedback AM11490v1 24/51 Doc ID Rev 2

25 Applicaion informaion Ideally, he volage generaed by he self-supply winding and he oupu volage should be given by he relaion beween he Naux/Ns urn raio only. Acually, numerous non-idealiies, mainly ransformer parasies, cause he acual raio o deviae from he ideal one. Line regulaion is quie good, in he range of ± 2%, whereas load regulaion is abou ± 5% and oupu volage olerance is in he range of ± 10%. The dynamics of he pin are in he 2.5 o 5 V range. The volage a he pin is clamped downwards a abou 2 V. If he clamp is exernally overridden and he volage on he pin is pulled below 1.4 V, he shus down. This condiion is lached as long as he device is supplied. While he device is disabled, however, no energy is coming from he self-supply circui, herefore he volage on he Vcc capacior decays and crosses he UVLO hreshold afer some ime, which clears he lach and les he HV generaor resar. This funcion is inended for an exernally conrolled burs-mode operaion a ligh load wih a reduced oupu volage, a echnique ypically used in muli-oupu SMPS, such as hose for TVs or moniors (see he iming diagram Figure 15). Figure 15. Exernally conrolled burs-mode operaion by driving he COMP pin: iming diagram Vcc (pin 5) VccON Sandby is commanded here VccOFF Vccresar COMP (pin 9) GD (pin 4) Vcc_OK Icharge 0.85 ma Vou AM11491v1 5.6 PWM comparaor, PWM lach and volage feedforward blocks The PWM comparaor senses he volage across he curren sense resisor Rs and, by comparing i o he programming signal delivered by he feedforward block, deermines he exac ime when he exernal MOSFET is o be swiched off. Is oupu reses he PWM lach, previously se by he oscillaor or he ZCD riggering block, which assers he gae driver oupu low. The use of PWM lach avoids spurious swiching of he MOSFET ha may resul from he noise generaed ( double-pulse suppression ). Doc ID Rev 2 25/51

26 Applicaion informaion Cycle-by-cycle curren limiaion is realized wih a second comparaor (OCP comparaor) ha senses he volage across he curren sense resisor Rs as well and compares his volage o a reference value V CSX. Is oupu is OR-ed wih ha of he PWM comparaor (see he circui schemaic in Figure 17). In his way, if he programming signal delivered by he feedforward block and sen o he PWM comparaor exceeds V CSX, i is he OCP comparaor o rese firs he PWM lach insead of he PWM comparaor. The value of Vcsx, hereby, deermines he overcurren sepoin along wih he sense resisor Rs. The power ha QR flyback converers wih a fixed overcurren sepoin (like fixed-frequency sysems) are able o deliver changes considerably wih he inpu volage. Wih wide-range mains, a maximum line i can be more han wice he value a minimum line, as shown by he upper curve in he diagram of Figure 16. The device has he line feedforward funcion available o solve his issue. I acs on he overcurren sepoin V CSX, so ha i is a funcion of he converer s inpu volage Vin sensed hrough a dedicaed pin (15, VFF): he higher he inpu volage, he lower he sepoin. This is illusraed in he diagram on he lef-hand side of Figure 17: i shows he relaionship beween he volage on he pin VFF and V CSX (wih he error amplifier sauraed high in he aemp o obain oupu volage regulaion): Equaion 5 V csx V = 1 3 VFF = 1 k 3 Vin Figure 16. Typical power capabiliy change vs. inpu volage in QR flyback converers sysem no compensaed k = k 1 sysem opimally compensaed k = kop AM11492v1 Noe: If he volage on he pin exceeds 3 V, swiching ceases bu he sof-sar capacior is no discharged. The schemaic in Figure 17 shows also how he funcion is included in he conrol loop. Wih a proper selecion of he exernal divider R1-R2, i.e. of he raio k = R2 / (R1+R2), i is possible o achieve he opimum compensaion described by he lower curve in he diagram of Figure 16. The opimum value of k, k op, which minimizes he power capabiliy variaion over he inpu volage range, is he one ha provides equal power capabiliy a he exremes of he range. The exac calculaion is complex, and non-idealiies shif he real-world opimum value from 26/51 Doc ID Rev 2

27 Applicaion informaion he heoreical one. I is herefore more pracical o provide a firs cu value, simple o calculae, and hen o fine une experimenally. Assuming ha he sysem operaes exacly a he boundary beween DCM and CCM, and neglecing propagaion delays, he following expression for k op can be found: Equaion 6 k op = 3 V inmin V inmax + V R ( Vinmin + Vinmax ) VR Experience shows ha his value is ypically lower han he real one. Once he maximum peak primary curren, I PKpmax, occurring a minimum inpu volage Vin min has been found, he value of Rs can be deermined from (5): Equaion 7 k 1 Rs = 3 I op V PKpmax inmin Figure 17. Lef: overcurren sepoin vs. VFF volage; righ: line feedforward funcion block Vcsx [V] VCOMP= Upper clamp Recified Line Volage R1 Opional for OVP seings 0.8 R2 Rs 0.6 VFF CS VVFF [V] COMP 9 15 VOLTAGE FEED FORWARD Vcsx V + PWM - + OCP - + Hiccup - R DRIVER S Q Clock/ZCD DISABLE 4 GD AM11493v1 The converer is hen esed on he bench o find he oupu power level Pou lim where regulaion is los (because overcurren is being ripped) boh a Vin = Vin min and Vin = Vin max. If Pou Vin max > Pou Vin min he sysem is sill undercompensaed and k needs o increase; if Pou Vin max < Pou Vin min he sysem is overcompensaed and k needs o decrease. This goes on unil he difference beween he wo values is accepably low. Once he rue k op is found in his way, i is possible ha Pou lim can urn ou slighly differen from he arge; o correc his, he sense resisor Rs needs o be adjused and he above uning process is repeaed wih he new Rs value. Typically, a saisfacory seing is achieved in no more han a couple of ieraions. Doc ID Rev 2 27/51

28 Applicaion informaion In applicaions where his funcion is no waned, e.g. because of a narrow inpu volage range, he VFF pin can be simply grounded, direcly or hrough a resisor, depending on wheher he user wans he OVP funcion o be auo-resar or lached mode (see Secion 5.11: OVP block ). The overcurren sepoin is hen fixed a he maximum value of 1 V. If a lower sepoin is desired o reduce he power dissipaion on Rs, he pin can be also biased a a fixed volage using a divider from VREF (pin 10). If he FF opion is seleced he line feedforward funcion can be sill used o compensae for he oal propagaion delay Td of he curren sense chain (inernal propagaion delay d (H-L) plus he urn-off delay of he exernal MOSFET), which in sandard curren mode PWM conrollers is done by adding an offse on he curren sense pin proporional o he inpu volage. In ha case he divider raio k, which is much smaller as compared o ha used wih he QR opion seleced, can be calculaed wih he following equaion: Equaion 8 Td k op = 3 Rs Lp where Lp is he inducance of he primary winding. In case a consan maximum power capabiliy vs. he inpu volage is no required, he VFF pin can be grounded, direcly or hrough a resisor (see Secion 5.11: OVP block), herefore fixing he overcurren sepoin a 1 V, or biased a a fixed volage hrough a divider from VREF o obain a lower sepoin. I is possible o bypass he pin o ground wih a small film capacior (e.g nf) o ensure a clean operaion of he IC even in a noisy environmen. The pin is inernally forced o ground during UVLO, afer acivaing any lached proecion and when he COMP pin is pulled below is low clamp volage (see Secion 5.5: PWM conrol block). 5.7 Hiccup-mode OCP A hird comparaor senses he volage on he curren sense inpu and shus down he device if he volage on he pin exceeds 1.5 V, a level well above ha of he maximum overcurren sepoin (1 V). Such an anomalous condiion is ypically generaed by eiher a shor-circui of he secondary recifier or a shored secondary winding or a hard-sauraed flyback ransformer. 28/51 Doc ID Rev 2

29 Applicaion informaion Figure 18. Hiccup-mode OCP: iming diagram Vcc (pin 5) VccON Secondary diode is shored here VccOFF Vccresar VCS (pin 7) 1.5 V GD (pin 4) OCP lach Vcc_OK AM11494v1 To disinguish an acual malfuncion from a disurbance (e.g. induced during ESD ess), he firs ime he comparaor is ripped he proecion circui eners a warning sae. If in he nex swiching cycle he comparaor is no ripped, a emporary disurbance is assumed and he proecion logic is rese in is idle sae; if he comparaor is again ripped, a real malfuncion is assumed and he is sopped. Depending on he ime relaionship beween he deeced even and he oscillaor, he device may occasionally sop afer he hird deecion. This condiion is lached as long as he device is supplied. While i is disabled, however, no energy comes from he self-supply circui; hence he volage on he V CC capacior decays and crosses he UVLO hreshold afer some ime, which clears he lach. The inernal sarup generaor is sill off, and he V CC volage sill needs o go below is resar volage before he V CC capacior is charged again and he device resared. Ulimaely, his resuls in a low-frequency inermien operaion (Hiccup-mode operaion), wih very low sress on he power circui. This special condiion is illusraed in he iming diagram of Figure Frequency modulaion To alleviae he converer s EMI emissions and reduce cos and size of he line filer, i is advanageous o modulae is swiching frequency, so ha he resuling spread-specrum acion disribues he energy of each harmonic of he swiching frequency over a number of side-band harmonics. Their overall energy is unchanged bu he individual ampliudes are smaller. This is wha naurally occurs wih QR operaion, due o he wice-mains-frequency ripple appearing on he inpu bulk capacior, which ranslaes ino differen DCM-CCM boundary frequencies. The is provided wih a dedicaed pin, F MOD (6), o perform his funcion if FF mode is seleced. Doc ID Rev 2 29/51