ACUTE Respiratory Distress Syndrome (ARDS) is a condition

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1 An Electrical Impedance Tomography Analog Front End for Lung Ventilation Monitoring Jaehoo Choi, Xiaoshan Wang and Daniel Zhang Electrical and Computer Engineering Georgia Institute of Technology GA, USA Abstract In this paper we present an electrical impedance tomography (EIT) analog front end implemented with the AMI 0.5um process for monitoring mechanically ventilated patients suffering from Acute Respiratory Distress Syndrome (ARDS). Current injection is accomplished using a digital-to-analog converter (DAC) to save on power and area consumption. The induced differential voltages across subsequent electrodes (controlled by a switching network) are amplified using a programmable gain amplifier (PGA) and digitized using an analog-to-digital converter (ADC) before being sent for further signal processing in a connected computer. Complex impedance mapping is achieved across the entire flow through the use and demodulation of in-phase and quadrature signals. Index Terms Bioimpedance, electrical impedance tomography (EIT), lung ventilation monitoring. Fig. 1: EIT system for lung ventilation monitoring. I. INTRODUCTION ACUTE Respiratory Distress Syndrome (ARDS) is a condition that affects nearly 200,000 patients per year with a mortality rates up to 50% in its most severe cases [1]. For those who suffer from the condition, mechanical ventilation is a common method of treating the symptoms. Inserted into a patient s mouth or neck, a ventilator aids in inhalation and exhalation through various forms of pressure control. In such applications the presence of a monitoring system is of utmost importance - early versions which lacked this feature posed a higher risk to users as the system themselves may cause ventilator-induced lung injury (VILI) [2]. A current tool in understanding the lungs pressure comes in the form of positive end-expiratory pressure (PEEP). However, while this information is useful for controlling the oxygenation of blood, various relationships between PEEP and gas levels remain unclear [3]. In a study using EIT to measure end-expiratory lung impedance changes ( EELI), [3] found that increases in EELI rather than PEEP measurements were linked to improved oxygenation. EIT presents a non-invasive method for medical imaging. Compared to CAT scans and MRIs, EIT imaging is portable, low cost, and can monitor in real time, making it especially relevant for monitoring patient ventilation. As further studies find links between lung impedance and ARDS, healthcare providers can better understand the patient s condition and make adjustments accordingly. Electrical impedance tomography is an imaging technique which maps the body s interior impedance distribution via electrode measurements on the skin. From a measurement standpoint, EIT follows the same principles as bioimpedance measurements. A low amplitude current is injected through the thorax across a series of electrodes and the corresponding surface potentials are measured. This information allows the extraction of the real and complex impedances of the surface measurements to be mapped into impedance fields using techniques such as finite element modeling (FEM) [4]. A. Digital Controller Considering the heavy computations involved with FEM models, it is necessary to do processing off chip. Benefits of interfacing to a computer rather than a microprocessor include faster deployment of new EIT algorithms and accessibility for healthcare providers to incorporate the system into their workflow. To bridge the transition from analog to digital signal processing, a digital controller is needed to interface the SoC to a computer through USB. Although the focus of this work is on the analog front end (AFE), it is important to consider what blocks should go into the digital controller. Shown in Figure 2, the controller needs to control the two DACs, ADC, PGA, and switching network. Two single-ended DACs are used to create a differential signal instead of using a differential DAC because the feedback will conflict with the voltage set by the capacitor array while in the single-ended setup the capacitor array is decoupled from the feedback. The proposed system is intended to receive power through the USB connection. Most ports are capable of supplying 5V up to 500 ma or more which is more than sufficient for this application.

2 Fig. 2: System block diagram of EIT front end The heart of the digital controller is the TUSB3210 which is a commercially available general-purpose USB device controller with built-in microcontroller (MCU). The device features its own 12 MHz crystal, 8kB of RAM for application development, and 32 general-purpose input output pins (GPIO). The on-chip memory can be used for storing a lookup table of digital values used as inputs to the DAC and the number of GPIO pins is sufficient for required number of control pins in our signal (8 for DAC since the complements are used to control the second DAC, 6 for electrode switching circuit, 5 for PGA, and 9 for ADC for a total of 28 pins required). Additionally the device supports data rates of up to 12 Mbits/s and will be primarily used to transfer the ADC s readings at a rate of 8 Mbits/s. B. Current stimulator The proposed system relies on using two out-of-phase DACs as opposed to a voltage-controlled oscillator (VCO) for generating the sinusoidal stimulus signal. In [5] it was shown that a system implementing a combination of a DAC and look-up table (LUT) provided a significant reduction in power consumption and layout area compared to an earlier system using an OTA-based sinusoidal generator [6]. Generating a sinusoidal output using a DAC, however, requires a sufficiently high resolution to avoid generating large frequency components outside of the fundamental frequency. From our MATLAB simulations sampling at 100 times the signal frequency, it was found that the power spectral density (PSD) of an ideal 8-bit DAC has a third harmonic at dbc. Next, the sinusoidal signal is sent to a current driver to convert the differential voltage into a current stimulus. That current passes through a switching network and applies the stimulus to the target electrode. The electrodes intended for use in this application are of the thin-film capacitive type and were chosen due to their ease of placement and preparation. At a given time, two switches will be enabled to send the Fig. 3: Schematic of electrode switching circuit. stimulus and the network will sweep through all other pairs of electrodes as shown in Figure 1 to sense the established voltages. The switching network involves two electrodes used at a given time in the stimulus path and two in the sensing path. Which electrodes are turned on are controlled by two 3-to-8 decoders as shown in Figure 3 with one decoder controlling switching for the stimulation path and the other controlling for the sensing path. Because the stimulator output current is symmetric biphasic, at any point in time one of the stimulator outputs is sourcing current and the other is sinking it. A high output impedance is desired to be able to keep virtually all of the current flowing through the electrodes and not into the ground of the system. C. Sensing Once the stimulus current is delivered, the system will read the voltages across pair combinations of the other electrode. In order to adequately read the input signal which may be on the order of microvolts, the potential difference is fed through a low-noise instrumentation amplifier (INA) with high common-mode rejection ratio (CMRR). Low-frequency nonidealities such as DC offset and 60 Hz ambient interference

3 Fig. 4: Schematic of segmented current-steering DAC. Fig. 5: Layout of amplifier. are rejected via high-pass filter. Since the original voltage may vary greatly in magnitude between µv to mv, the signal must also be delivered into a programmable-gain amplifier (PGA) with adaptive control to prevent saturation and ensure the signal is still detectable [7]. Since the value of the gain setting of the PGA is available to the digital controller, an 8-bit ADC will for sufficient to attain adequate resolution especially for applications of measuring relative lung impedance as opposed to absolute impedance. The digital output of the ADC are sent to the digital controller and eventually will be used as measurement values. This information is also used to determine if the PGA gain settings need to be adjusted and will be able to respond quickly since the ADC is sampling at a frequency much higher than the input signal. In digital domain, the data is at a relatively low speed where modern systems can use digital demodulation to extract the signal s in-phase and quadrature components. This information allows the calculation of real and complex impedances. II. D IGITAL TO A NALOG C ONVERTER The DAC used for waveform generation is presented in Figure 4. Since the sinusoid of interest is low-frequency, the architecture does not require fast response times. Therefore, Fig. 6: Layout of capacitor array. a charge redistribution model is used for minimal power consumption while providing adequate resolution for sine wave generation [8]. The capacitor array has a minimum capacitor value of 100 ff and total capacitance of 25.6 pf for 8-bit resolution. The amplifier in unity-gain feedback utilizes a cascode architecture to provide rail-to-rail ICMR and a class A output stage for improved linearity. However, since the amplifier cannot fully swing up to 3V, the DAC reference voltage is set to 2.7V to guarantee linearity. An off-chip RC low-pass filter with a 10 khz cutoff frequency is used to attenuate high-frequency components and ensure a smooth output signal. As noted previously, the DAC must produce a signal that is as close to a sine wave as possible for the system to function properly. Apart from the waveform being discretized, there are also errors that result from the switching circuitry. For such applications it is common to use a unit-cell approach since it guarantees monotonicity, low differential nonlinearity

4 Fig. 7: DNL of simulated DAC. Fig. 9: Sinusoid generated from DAC. Figure 9 shows a 10 khz sinusoid generated by the extracted DAC when provided an appropriate 1 MHz bit pattern from the LUT. An additional benefit to using a DAC to generate the stimulus signal is that it can be easily programmed to produce other frequencies by changing the period between each transition in the LUT. Although the intended application of this work uses a fixed frequency of 10 khz the system can be reprogrammed Fig. 8: INL of simulated DAC. (DNL), and small glitches. However, the topology must rely on a decoder which becomes rapidly complex and grows exponentially as the number of bits increases [9]. Therefore, there must be a compromise between the unit-cell topology and the binary weighted topology to make the design practical. The 4-4 segmented DAC used for this application combines elements from both topologies where the most significant bits (MSBs) are in unit-cell mode while the least significant bits (LSBs) are used in binary weighted mode. This scheme takes advantage of the phenomenon where maximum DNL occurs during MSB transitions in the binary weighted topology. This allows the DAC to achieve reasonable DNL and glitch performance while keeping the number of devices low. The segmented charge redistribution DAC is expected to have at least DNL < 0.5 LSB and INL < 0.5 LSB to ensure that the voltage waveform is not corrupted. Figures 5 and 6 show the layouts of the core building blocks. The capacitor array partially follows the common centroid technique, but was modified to allow for simpler routing. Postlayout simulations of the INL and DNL are shown in Figures 7 and 8, demonstrating full 8-bit functionality. Differences between schematic and post-layout are negligible - the maximum DNL errors are and LSB respectively; the maximum INL errors are and LSB respectively. TABLE I: DAC Performance Summary Resolution 8-bit Supply Voltage 3V Reference Voltage 2.7V Power Consumption mw Full Scale Range 0V to +2.7V Unity Gain Bandwidth 14 MHz DNL < 0.5 LSB INL < 0.5 LSB for other uses such as impedance spectroscopy which involves taking impedance measurements over a range of different frequencies. III. CURRENT DRIVER The current driver is a key device in EIT systems. In practice the load of the current driver, which is the electrode-tissue interface, can vary greatly in magnitude. Therefore, the current driver should be designed to have high output impedance to be able to deliver constant output current to the body regardless of the amount of contact impedance. The current driver is designed as shown in Figure 10. The current driver is composed of preamplifiers, transconductance stages, and voltage buffers. The preamplifiers and the transconductance stages are implemented with conventional rail to rail OTA as shown in Figure 11. In Figure 12, the voltage buffer is implemented with a differential difference amplifier (DDA) configured as a differential to single ended unity gain to avoid the requirement of tightly matched resistors for instrument amplifier [9]. The current through the electrode is sensed through the voltage across the resistor, Rs, and the established voltage across the resistor is fed back to the preamplifier by

5 Fig. 12: Schematic of DDA Fig. 10: Implementation of the current driver. Fig. 11: Schematic of OTA the voltage buffers for the negative feedback. This negative feedback provides the high output impedance as AGm ro Rs. In the simulation, the 250 kω output impedance is achieved. The two sine wave voltages generated from DAC are 180 degree phase shifted each other. It accomplishes symmetric biphasic stimulation, thus the injected current will not leak with the help of high output impedance. These two sine wave voltages are converted to the constant AC current that are each 250µApk in symmetrical biphasic manner, thus each one is either sourcing or sinking current relative to the other, which results in AC current of 500App to the load. IV. R EADOUT C IRCUIT A. Instrumentation amplifier The first stage of voltage sensor is an INA. As shown in Figure 13, the INA is designed to have low noise to maximize resolution and high input impedance to provide high CMRR with the voltage again by the ratio of capacitors. Since the minimum input voltage from electrodes is 10 µvpk and the common-mode voltage is 400 mvpk [9], the required minimum common mode rejection ratio (CMRR) of INA is over 92 db. Moreover, the gain of the INA is set to 34 db to achieve rail-to-rail output voltage as the expected maximum input voltage is around 50 mv [9]. Also, the INA contains a high pass filter (HPF) with the cut-off frequency of 6 khz to reject the DC offset from the input voltage to avoid saturation and reduce the 60 Hz noise by -40 db while passing the desired 10 khz signal. The conventional fully differential folded cascode OPA with continuous common mode feedback circuit is used in INA to handle rail to rail output as shown in Figure 14. TABLE II: Current Stimulator Summary Frequency khz Amplitude µapp Output Impedance 250 kω Input Referred Noise 5.5 µvrms Power 5.75 mw In the simulation, the readout circuit achieved total of 100 db CMRR. B. Programmable gain amplifier The second stage of the voltage sensor is PGA with programmable gain to cover large input voltage variation. Since the input voltage from electrode pair varies greatly from 10 µvpk to 50 mvpk [10], PGA with programmable gain is essential block in the voltage sensor. The PGA is designed to provide additional gain of 0 or 30 db in the first PGA and 0 to 30 db in steps of 6 db with a binary weighted capacitor bank in the second PGA as shown in Figure 15. If the amplitude of output voltage of ADC is too small, then the digital controller will determine the additional gain needed to achieve rail to rail output and the determined gain from digital controller is fed back to the PGA. The same OPAs used in the INA are used in PGA as shown in Figure 14. The bandwidth of total readout circuit is designed as 100 khz to handle 10 khz signal, but not exceeding too much to save power. Also, the input referred noise is measured as 5.5 µvrms over 100 khz which is the bandwidth of readout circuit as shown in Figure 16. Once the electrode pair is switched to the other one, the digital controller will evaluate the required gain again.

6 Fig. 15: Programmable gain amplifier with automatic gain control. Fig. 13: Instrumentation amplifier with high-pass filter. Fig. 14: Schematic of fully differential folded cascode OPA. TABLE III: Readout Circuit Summary Frequency khz Gain db (10 steps) CMRR 100 db Power 2.3 mw V. SAR ADC The ADC architecture used in this work is an 8-bit successive approximation register ADC and was chosen due to the desired signal s frequency being at relatively low speed and favoring low power consumption with high enough resolution. Shown in Figure 17 is a high-level overview of a standard SAR ADC. The ADC uses a charge-redistribution DAC following a switching scheme and architecture needing only one external control signal to control the sampling rate as proposed in [11]. Due to the bandpass response of the readout amplifiers, which has an upper -3dB frequency near 100 khz followed by a twopole rolloff, signals around the ADC s sampling frequency of 1 MHz will be attenuated by -40 db which should suffice as acting as an anti-aliasing filter for the ADC. Because the ADC is differential, it measures the difference of input voltages ranging from V ref to +V ref with V ref being 3V. Being an 8-bit ADC this gives us a LSB voltage of 23.4 mv. A. Bootstrap Switch Considering that the nominal threshold voltages of NMOS and PMOS devices used in the process are 0.67 V and 0.92 V respectively, using a transmission gate to pass the input signal to the ADC can have large variations in switching resistances Fig. 16: Input referred noise of readout circuit. during cases where only one of its transistors turns on. Shown in Figure 18, a bootstrap circuit drives the switch s gate to VDD above the input and allows a rail-to-rail swing [12]. This boosted V GS not only reduces the switch s R DSon but also lowers the variation of R DSon as the switch s source voltage changes, improving linearity. B. Charge Redistribution DAC Using a capacitive charge redistribution DAC has the benefit of also having the functionality of a sample and hold amplifier (SHA) which eliminates the need for designing a SHA in addition to a DAC [13]. A binary-weighted capacitor is array is used as opposed to a C-2C array in order to achieve better linearity [11]. Shown in Figure 17, the DAC involves a monotonic switching sequence of the capacitor array to obtain lower power consumption and avoids the need of an additional commonmode voltage compared to the conventional scheme [11]. Additionally, the scheme needs one less capacitor in each of the arrays which cuts down the number of required unit capacitors by a factor of two when compared to more conventional charge-redistribution DACs. During the hold phase, the SAR logic determines whether to connect the bottom plate of each capacitor to V ref or ground based on the output of the comparator. Each bottom plate that is connected to V ref will reduce the voltage at the the corresponding input of the comparator. This switching scheme has the benefit of requiring one switch change per cycle and

7 Fig. 17: General overview of SAR ADC. Fig. 18: Schematic of bootstrap switch. only involving downward switching which allows for being able to use the lower RDSon of NMOS switches compared to PMOS ones [11]. By the end of the ADC s conversion period, both input terminals to the comparator will approach zero charge and eliminates the need for a reset phase. Fig. 19: Dynamic Comparator C. Dynamic Comparator The dynamic comparator shown in Figure 19 consists of a differential input followed by a latch and push-pull amplifier. A PMOS transistor cascoded with the tail current transistor acts as a switch to enable the comparator such that it only consumes dynamic power. When the enable signal is high, both output voltages are high and are the only case to cause a NAND gate to go low. This attribute is used to ultimately generate the internal clock of the entire ADC [11]. D. SAR Logic Unlike many other SAR architectures, the one presented in [11] only has one external control signal and must generate the rest internally. The ADC uses an asynchronous clock generator shown in Figure 20 that uses the outputs of the comparator (the Fig. 20: Asynchronous Clock Generator VALID signal is the NAND of both comparator outputs) and the external control signal (which is at the sampling frequency) [11]. During each conversion period there is one clock signal generated for each bit for a total of 8 internal clocks signals. The control logic shown in Figure 21 takes in the clock of the current step in the conversion as well as the comparator output controls the switches of the capacitor array using inverters as switch buffers. During each step of the SAR algorithm, the comparator output determines what to set the

8 Fig. 21: DAC Control Logic for this SAR ADC Fig. 23: INL of Simulated ADC Fig. 22: DNL of Simulated ADC next switch to. Only one switch decision needs to be made per step due to the monotonic nature of the switching scheme. E. ADC Performance Simulations were conducted in Cadence Spectre to characterize the DNL and INL of the SAR ADC. Shown in Figures 22 and 23 we see the max DNL and INL are both 0.5 LSB and occur in cases where this architecture s SAR algorithm theoretically causes both comparator inputs to approach 0V, so the effect of non-idealities such as parasitic capacitances have a much larger impact at these specific input sets. TABLE IV: SAR ADC Performance Summary Resolution 8-bit Supply Voltage 3V Power Consumption 374 µw Full Scale Range -3V to +3V Differential Sampling Frequency 1 MHz DNL < 0.5 LSB INL < 0.5 LSB VI. POWER SUPPLY To ensure the integrity of the supply voltage, the analog front end will rely on a beta multiplier reference (BMR) and a non-inverting operational amplifier, as shown in Figure 24. The BMR reference voltage is fed into the amplifier, boosting the value to 3V which will then act as the supply for the rest of the system. Fig. 24: Beta-multiplier and LDO for voltage regulation. TABLE V: Power Supply Performance Summary Supply voltage range 4V to 6V Temperature range 0 C to 70 C Reference voltage 2.99V to 3.03V Reference current (10 µa) 9.57 µa to µa Voltage drop when powering system < 1 mv VII. PERFORMANCE SUMMARY Shown in Table VI is a breakdown of power consumption of the different blocks in the system. As one would expect, the stimulator has the largest power consumption as it needs to be capable of driving upwards of 500µA pp. Additionally the readout amplifiers are the next biggest contributor since they need to be able amplify signals on the order of microvolts with upwards of 90 db of differential gain. Figure 25 shows the floorplan of the proposed system which is used to determine where to lay out each block. In Figure 26, a chart shows the relative distribution of these power consumptions. TABLE VI: System Power Consumption Summary DAC 1.45 mw ADC 0.37 mw Readout Amplifiers 2.30 mw Stimulator 5.75 mw Biasing 0.15 mw

9 Fig. 25: Floor plan of proposed SOIC VIII. DIVISION OF LABOR Fig. 26: Power Consumption Relative Contributions TABLE VII: Comparison with State of the Art This work Lee [6] Supply Voltage 3V 1.8V Power Consumed 10 mw 4.84 mw Frequency khz khz Current drive µa p p µa p p Resolution 8-bit ADC/DAC Not specified INL < 0.5 LSB Not specified DNL < 0.5 LSB Not specified Clock 1 MHz Not specified TABLE VIII: Projected Responsibilities Team Member Tasks Jaehoo Choi Current Driver, INA, HPF, PGA Xiaoshan Wang DAC, Voltage Regulator, BMR Daniel Zhang SAR ADC, DAC and ADC Characterization IX. CONCLUSION In this work, a system for electrical impedance tomography was proposed using a 10 khz stimulus signal to produce currents of 500 µa pp and detect peak voltages between 10 µv to 50 mv. Through simulation, we were able to to demonstrate that our system was capable doing so while keeping power consumption comparable to other state of the art systems. REFERENCES [1] C. Mason, N. Dooley, and M. Griffiths, Acute respiratory distress syndrome, Clin Med, vol. 16, no. Suppl 6, pp. s66 s70, Dec [2] N. Rittayamai and L. Brochard, Recent advances in mechanical ventilation in patients with acute respiratory distress syndrome, European Respiratory Review, vol. 24, no. 135, pp , Mar [3] C.-F. Hsu et al., Electrical impedance tomography monitoring in acute respiratory distress syndrome patients with mechanical ventilation during prolonged positive end-expiratory pressure adjustments, Journal of the Formosan Medical Association, vol. 115, no. 3, pp , Mar [4] T. Murai and Y. Kagawa, Electrical Impedance Computed Tomography Based on a Finite Element Model, IEEE Transactions on Biomedical Engineering, vol. BME-32, no. 3, pp , Mar

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