A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury

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1 1 A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury Garren Boggs, Student, IEEE, Hua Chen, Student, IEEE, Sridhar Sivapurapu, Student, IEEE Abstract This work proposes an improved analog front end (AFE) that will utilize a MEMS microphone to listen to a user s knee movements and predict injury or the onset thereof. The improvements this work presents are for everyday applications. This AFE includes two amplifying stages with gains of approximately 26dB and 37dB respectively, a twelfth-order bandpass filter with 15Hz and 21kHz cutoff frequencies, and a SAR ADC for processing the analog data. A linear regulator was used in conjunction with a beta multiplier biasing circuit to create stable voltages for the IC when battery powered. The proposed system also includes a wireless transceiver mircocontroller to transmit data to a host computer or phone. Index Terms System-on-a-chip, SoC, MEMS, knee injury, Analog-to-Digital converter, ADC A I. INTRODUCTION THLETES who participate in sports and activities that involve increased stress on the lower body as well as high exposure to physical contact, are at higher risk for musculoskeletal injuries, and in particular, injuries of the knee [1]. These injuries can be severe and lead to inhibited or no ability to participate in practice or competition [1]. Therefore, athletes must be aware when prolonged stress and impact to these joints could lead to severe damage. In an attempt to either detect knee injuries or the onset thereof, athletes would benefit from a device that can non-invasively monitor the health of their knees. This is the focus of study for Dr. Omer T. Inan and his research group. They proposed a design for a wearable technology that utilizes microphones to detect acoustic anomalies that may indicate injury [2]. Their design incorporates only a microphone and an analog front end to amplify the detected signal. The signal is transmitted off-chip to a third-party analog-to-digital converter (ADC) to later be processed. This paper describes an alternative design of the system-on-a-chip (SoC) that will provide users with a way to acoustically assess injuries of the joints in their knees. Ultimately, the objective of this design is to optimize the preexisting technology for the wearable device, not only improving the accuracy of injury detection, but also improving the battery life by reducing the power consumption. Additionally, the peripherals associated with the SoC are included to show a top level diagram of how to interface with the SoC. More details about each of the main blocks are below. A. Amplifier Fig. 1. Block diagram of the SoC and its peripherals. The analog front end of this device begins with an amplifier stage to boost the signals received by the microphone. On average, the largest acoustic input to the microphone is 60 mpa [2], which is equivalent to a sound pressure level of 69.5dB SPL. Knowing this value the maximum input voltage was determined to be 1mV peak [3]. There are two stages at which the signal will be amplified: pre- and post-filtering. The initial amplification stage provides 26dB of gain. This number was selected large enough to effectively reduce the input referred noise from the following stages, however small as to stay within the 40mV pp linear range of the filters. Additionally, to scale the filtered signal to the full scale 3V pp, the second amplification stage should provide a gain of approximately 37.5dB, however to account for possible unexpected jumps in the microphone voltage, the gain was selected to be 37dB. A cumulative list of the target specifications for the amplifier can be found in Table 1. II. SYSTEM ARCHITECTURE AND DESIGN CONSIDERATIONS Figure 1 is a block diagram for the SoC and its necessary peripherals. Inside of the SoC block diagram features the major blocks that will be designed for its operation.

2 2 TABLE II OPERATIONAL AMPLIFIER - TRANSISTOR SIZES Transistor W/L (μm) Multiplicity Fig. 2. Schematic of the proposed operational amplifier. TABLE I OPERATIONAL AMPLIFIER TARGET SPECIFICATIONS Specification Target Value Supply Voltage +3V ICMR Rail-to-Rail Output Swing Rail-to-Rail A 0 80dB Bandwidth 21kHz ϕ M > 60 Max Current Drive 36μA Power Consumption < 200μW Figure 2 shows the circuit level schematic of the proposed op-amp. The amplifier s input stage consists of dual PMOS and NMOS differential pairs to allow a full rail-to-rail input swing [4]. This extended input common mode range (ICMR) is utilized to ensure that the input biasing transistors do not go out of saturation under any conditions such as additional noise on the microphone from environmental factors. To ensure that the op-amp could accurately achieve a closedloop gain of 37dB, the desired open-loop gain was set to be a minimum of 80dB. Thus, the differential pair will feed into a folded cascode stage. This is especially important to ensure the op-amp can drive the full-scale voltage range to the ADC. The output transconductance stage provides another boost in the gain and the sizes of these transistors were chosen to such that the op-amp can drive at minimum 36μA. This value is a pessimistic estimate of the current required by SAR logic block s large capacitive load such that the accuracy of the ADC is not degraded. Finally, a compensation circuit is placed between the folded cascode stage and output stage to increase the phase margin and improve stability. The value of the compensation capacitor is 1pF. Table 2 shows the sizes for each transistor in the proposed op-amp. The two tail currents for the amplifier are biased using voltages provided by the Beta Multiplier Reference (BMR) described in section C, while the folded cascode is biased from voltages generated from diode connected transistors. Additionally, since the acoustic signals recorded from the knee can vary in frequency over a bandwidth of approximately 20kHz [2], a minimum bandwidth of 21 khz was required. A full characterization of the op-amp and a benchmarking against other designs is listed in Table 3. Additionally, any feedback components used for the op-amp will be off-chip to provide variable gain for varying microphone inputs. N 1, N 2 7.5/1.2 1 N 3, N 4, N 5, N 6 3/3 1 N 7, N 8, N 9, N 10 12/1.2 1 N /1.2 1 P 1, P 2 15/1.2 1 P 3, P 4 18/1.2 1 P 5, P 6 6/1.2 1 P 7 5.4/1.2 1 N Tail 3.6/3 1 P Tail 9.3/3 1 N B1, N B2 1.5/3 1 P B1 4.5/2.4 1 P B2, P B3, P B4 18/1.2 1 P Res 9/1.2 1 TABLE III COMPARISON OF PROPOSED OPERATIONAL AMPLIFIER WITH OTHER DESIGNS Parameter Proposed [5] [6] Supply Voltage +3V +5V ±5V ICMR Rail-to-Rail Rail-to-Rail - Output Swing 2.9mV / 2.998V 100mV / 4.87V -4V / 3V V OS 94μV 1mV 10μV CMRR 132dB 85dB 91dB PSRR+ 66dB 85dB 73dB PSRR- 56dB 95dB 72dB A 0 108dB 66dB 66dB f 0dB 12.7MHz 1.5MHz 17.2MHz ϕ M Max Current Drive 223μA ±22mA - R out 248kΩ - 344Ω Slew Rate 5.829V/μs 1.7V/μs 16V/μs V n,input (1MHz BW) 10.89μV rms - - Power Consumption 149μW 1.75mW 12mW Fig. 3. Open loop frequency response of the op-amp. B. Linear Regulator The linear regulator is designed to generate a stable supply voltage for the microphone, input amplifier, bandpass filter, biasing and reference circuits, and the ADC. The linear regulator needs to maintain a constant voltage while the battery voltage varies as well as variations of the load impedance. The constant voltage is maintained by using

3 3 negative feedback to compare a reference voltage with the output voltage. Possible circuits to use to act as the reference voltage are a BMR or a Bandgap Reference (BGR). In this case, a BMR is used. simulated results of both the LDO and the V CM generator and Table 4 summarizes the results. Fig 6. Circuit to implement V CM. Fig 4. Linear regulator schematic. Figure 4 is the transistor schematic of a low dropout voltage regulator. This voltage regulator has two major components, a BMR that generates a 1.8V reference and an LDO. The LDO has an error amplifier, which compares the reference voltage from the BMR to the output voltage and uses negative feedback to prevent the output voltage from dropping. A large PMOS is used to drive a large output current and designed to minimize VDS [7]. In this case, VDS is set to 0.2V, allowing the battery to drop to close to 3.2V while maintaining a constant 3V output. Additionally, this PMOS is capable of driving 10 ma at 3V. These results can be seen in Figure 5. Fig 7. DC sweep of the input battery voltage to determine drop-out voltage. Fig 5. V DD and V CM maximum current output. Additionally, the amplifier, filter, and ADC need a common voltage, which should be set to V DD/2. This voltage, like the output of the LDO should be constant regardless of the load. However, in this case, the requirements are not as strict because this voltage is used to drive mostly gates of transistors for biasing. The major requirement for this voltage is that it must track V DD because it needs to be a common voltage. Like the LDO, there is an error amplifier used to maintain the common voltage. However, to generate the reference voltage, two equally sized diode-connected transistors are used to ensure that V DD is tracked. This circuit is capable of driving.8 ma of current and can be seen in Figure 6. Figures 7-10 show Fig 8. The start-up delay for both V DD and V CM.

4 4 Fig. 9. Line regulation of the linear regulator. Fig. 11. Cascode BMR for battery voltage = 3.7V. Fig. 10. Load regulation of the linear regulator. TABLE IV SUMMARY OF LINEAR REGULATOR SPECIFICATIONS Specification V DD V CM V out 3.02 V 1.51 V Dropout Voltage.2 V N/A Output Current ma 800 μa V Battery sensitivity 188 ppm 225 ppm Temperature sensitivity 437 ppm 689 ppm Power Supply Gain db db Power Supply Gain db db C. Biasing The system requires both a battery and temperature insensitive BMR to act as the reference voltage for the LDO. The total number of circuit branches and current size determine the power consumption of the BMR, meaning that more power is consumed when more devices are using the reference. This particular BMR creates a reference voltage of 1.8V. This BMR has a V Battery sensitivity of 381ppm and has an input current of 3.78uA with the V Battery sensitivity at 3100 ppm. The circuit topology is seen in Figure 11 and the resulting outputs are seen in Figure 12. Fig. 12. BMR Outputs: Iref=3.78uA, Vref=1.77V. The sensitivity is 381 and 3100ppm respectively. A second BMR was created to bias the input amplifier, filter, and ADC. This BMR uses the output of the LDO as its supply. The schematic for this BMR can be seen in Figure 13. This topology is common and is used in many general applications. The output of this BMR can be seen in Figure 14.

5 5 Fig. 13. Schematic of the BMR used to bias the amplifier, filter, and ADC [8]. Desirably, the filter stage should consume a very minimal amount of power. A well-known topology for low-power filtering is the G m-c filter, which as the name suggests requires an operational transconductance amplifier (OTA) and a capacitor. There were multiple factors that went into ensuring that the specifications for the filter were met. First, in order to achieve the very low cutoff frequencies while keeping the sizes of the capacitors small, a very low transconductance (g m) was required. Therefore, a specific OTA topology was used, and can be seen in Figure 15. Like the op-amp, the OTA utilizes a dual PMOS and NMOS differential pairs to achieve a rail-to-rail ICMR. The current passing through each differential pair is mirrored to the output. To significantly reduce the g m, a current stealing method was employed by adding additional differential pairs in parallel with the original, and respectively tying the input signals to them [9]. By doing so, a fraction of the bias current is stolen from the input differential pairs, and consequently the overall output current, thus effectively reducing the g m. The fraction of current that is stolen can be adjusted by increasing the number of these transistors in parallel with the input pairs. A multiplicity of 8 was chosen for this design for two reasons: diminishing returns on decreased g m, and limited chip space. Fig. 14. The Vref=0.8Vand Iref =6uA. The sensitivity is 32 and 485ppm respectively. D. Filtering To reduce the environmental noise and noise generated from the op-amp, a bandpass filtering stage will succeed the first amplification stage. As with the op-amp, this filter was designed to have an upper cutoff frequency of 21kHz, with an additional 15Hz lower cutoff frequency. This lower cutoff frequency is selected to minimize the attenuation of the desired signal band, while significantly reducing DC offsets and flicker noise components. Additionally, the filter was designed have a maximally flat passband to prevent distortion of the signal. The targeted specifications for the filtering stage are listed in Table 5. TABLE V BANDPASS FILTER TARGET SPECIFICATIONS Specification Bandwidth Passband Attenuation Gain at f c ± 0.2 decades Power Consumption Target Value 15Hz 21kHz < 1dB < -20dB < 50μW Fig 15. Schematic of the proposed OTA. An additional method for reducing the g m used in this design was to add parallel transistors on the input end of the current mirrors [9]. Similar to decreasing the ratio of transistor sizes of a current mirror, adding these extra parallel transistors will produce a smaller output current than the input. Once again, this additional decrease in current will reduce the overall g m. With the use of these two methods, the proposed OTA achieved an extremely low transconductance of approximately 640nS. However, as the g m decreased, linearity and noise performance were compromised which placed a lower bound on the transconductance. Because of this, the capacitance required to achieve the lower 15Hz cutoff was too large, and thus will be moved off-chip. Table 6 lists the dimensions for each transistor in the proposed OTA, while Table 7 characterization of the op-amp and a benchmarking against other designs.

6 6 TABLE VI OTA - TRANSISTOR SIZES Transistor W/L (μm) Multiplicity N 1, N 2 1.5/1.8 1 N 3, N 5, N 6 1.5/3 1 N 4 1.5/3 4 P 1, P 2, 1.5/1.8 1 P 3, P 5, P 6 1.5/3 1 P 4 1.5/3 4 N Tail 1.5/2.4 1 P Tail 1.8/2.4 1 N M1, N M2 1.5/1.8 8 P M1, P M2 1.5/1.8 8 TABLE VII COMPARISON OF PROPOSED OTA WITH OTHER DESIGNS Parameter Proposed [9] [10] Supply Voltage +3V ±2.5V +0.5V G m 297nS 39.5nS 31.1nS A 0 41dB 52.3dB 49.6dB V n,input (1MHz BW) 96.18μV rms 332μV rms 496μV rms Power Consumption 149μW 1.75mW 107nW Fig 18. Overall frequency response of the bandpass filter. Another specification that had an impact on design choices was the desired attenuation at ±0.2 decades of the cutoff frequencies. To achieve -20dB at 0.2 decades away, the filter must provide a dropoff of at least -100dB/decade. Thus, the type of filter was determined to be a 12 th order Butterworth bandpass to achieve both the desired attenuation and passband response. To realize the bandpass filter, 6 th order low pass and high pass filters were cascaded. The individual topologies consisted of taking three, second-order filters. After calculating the required capacitance at each stage from the normalized Butterworth polynomials, the filters were put together using the topology given in [11]. The schematics for the two filters can be seen in Figures 16 and 17. The values for the capacitors used in each filter are listed in Table 8. Since the high pass filter stages connected through input capacitances, each subsequent stage loaded the previous ones, and thus it was necessary to buffer each stage. Using the low- TABLE VIII BANDPASS FILTER CAPACITORS Capacitor Value (High Pass) Value (Low Pass) C 1 6.2nF 4.2pF C 2 1.7nF 1.1pF C 3 4.5nF 3pF C 4 2.3nF 1.5pF C 5 1.7nF 1.1pF C 6 6.3nF 4.2pF Fig 16. Schematic of the proposed high pass filter. Fig 17. Schematic of the proposed low pass filter.

7 7 power unity gain buffer topology described in [12], isolation between stages was achieved, and the frequency response remained unloaded. The overall frequency response for the bandpass filter can be seen in Figure 18. E. Analog-to-Digital Converter Since the maximum frequency signals that the ADC will receive is 21 khz based on the bandwidth of the filter, a highspeed ADC is not necessary. Additionally, high accuracy is required to analyze different audio signals from the knee. Thus, to achieve the precision found in [1], a 16-bit ADC would be required, however this is outside of the scope of the project as this ADC would require too much space on the SoC. Thus, an 8-bit SAR ADC was proposed because of the relative simplicity of designing one compared to a ΔΣ ADC to have an accuracy improvement [13]. A sampling rate of 50 khz was chosen since the highest frequency signal that the ADC will receive will be 21 khz. The simplified architecture of the SAR ADC can be seen in Figure 18. The SAR ADC consists of the SAR logic block, a charge redistribution DAC, and a comparator. The SAR Logic Block can be seen in Figure 19. This logic block consists of two shift registers, each of which contains nine D-Flip Flops. These D-Flip Flops were made using a NAND SR Latch and an inverter. The top shift register in Figure 19 acts as a sequencer that is controlled by the input clock, while second stores the value from the sample. An additional advantage is that it has low power consumption. The outputs of the SAR logic are fed to the DAC to complete the binary search algorithm. kickback noise and large offset voltages are minimized since this is not a clocked comparator. Therefore, many offset reduction techniques like Correlated Double Sampling, larger differential pair inputs, and clocked NMOS and PMOS capacitors [16] do not need to be considered. Without these inclusions, area is saved, which is crucial for the SAR ADC because the charge redistribution DAC consumed most the area. Additionally, input offset was reduced by the charge redistribution DAC resulting from the reset switch to clear the voltage to the common voltage, as seen in Figure 21. This DAC is low power and straightforward to implement. However, the drawback to this design is area since a large array of capacitors need be used. Specifically, 256 capacitors at minimum are required for an 8-bit ADC. The large area is susceptible to process variations to change the desired ratio of capacitance values at each bit compared to a unit cell. To decrease this, a common centroid layout technique was implemented. This layout can be seen in Figure 22. In this implementation, a 100 ff capacitor is used as the unit cell as it is small to help reduce area consumption, but not too small to be altered by the parasitic capacitance of the input differential pair. Fig 20. Comparator. Topology of comparator used for ADC. Fig 18. Simplified SAR ADC Top Level Schematic [14]. Fig 21. Charge redistribution DAC [13]. This example uses three bits, whereas the design proposed here will use eight. Fig 19. An example of the SAR Logic Block [15]. This example uses nine bits, whereas the design proposed here will use eight. The architecture of the comparator for this SoC was a low power general purpose comparator, like the one found in [8]. The schematic for this comparator can be found in Figure 20. The biggest advantage of this comparator is that it is low power compared to other circuits in the SoC. Additionally, Fig 22. Layout of Capacitor array using Common Centroid technique.

8 8 To reduce the RC time constant associated with the switches and capacitor bank, three sets of transmission gates with ratios of 40/1 and 20/1 for the PMOS and NMOS respectively, were used. Increasing the size of the transistors decreased the on resistance, but there was an upper bound on the size due to area constraints. The three sets of switches were used to behave as single pole triple throw switches. The network of switches, and logic to control them, can be seen in Figure 23. This network is adopted from [15]. TABLE X COMPARISON OF PROPOSED ADC WITH OTHER DESIGNS Specification Proposed [15] [17] Supply Voltage 3V 3V 3.3V INL (Worst).5 LSB 72dB -.33 LSB DNL (Worst).3 LSB 66dB -.4 LSB f sampling 1 MHz 1 khz 1 MHz ENOB 7.45 bits 9.72 bits bits SFDR db - Power μw 12.4 nw 1.8 mw Cosumption FOM 657 fj/conversion -step 14.7 fj/conversion -step 1.26 pj/conversion -step Fig. 23. Schematic of network of switches and associated logic to control the switches to behave like a single pole triple throw switch. The target specifications for this ADC can be seen in Table 9. The FOM that will be used for this ADC can be seen in (1). A good target for this design is 5.1 pj/conversion step. Table 10 shows the proposed design and comparison to two other ADCs found in [15] and [17]. In order to determine the INL and DNL, the worst case is taken to be around the point where the ADC output switches from to and vice versa. Since this is theoretical worst case scenario, it is assumed to be the worst case INL and DNL situations. For this case, the center value is 128 in decimal (or only the MSB high). Plots of both DNL and INL can be seen in Figures 24 and 25. Additionally, the layouts of the individual components of the ADC (comparator, DAC featuring the capacitor bank and switches, and the SAR logic block) and the entire ADC can be seen Figures Fig. 24. DNL Plot of ADC around the theoretical worst case scenario. TABLE IX TABLE OF TARGET SPECIFICATIONS FOR ADC Supply Voltage INL DNL f sampling Specificaiton ENOB Power Consumption FOM Target 3V.5 LSB.5 LSB 400 khz 7.2 bits 300 uw 5.1 pj/conversion-step Fig. 25. INL Plot of ADC around the theoretical worst case scenario. FOM = Power 2 ENOB f s (1) Fig. 26. Layout of comparator seen in Comparator Figure.

9 9 highlights some of the specifications for the microphone that are valuable for the design. TABLE XI MEMS MICROPHONE SPECIFICATIONS Specification Typical Value Fig. 27. Layout of capacitor switch schematic seen in associated figure. Fig. 28. Complete DAC layout featuring capacitor bank and associated switches. Supply Voltage (Low Power Mode) 1.8 V I S 55 µa V out 129dB SPL V RMS Bandwidth 50 Hz 20 khz Sensitivity -328 dbv PSRR 85 db SNR (A-weighted) 67 dba Output Impedance 5.5 kω A typical MEMS microphone s output will be DC biased at a point between its supply voltage and ground to prevent any clipping of the signal. In the case of this design, the microphone output will be biased ideally at 1.65V. The signal will then be AC coupled with the amplifier stage using an offchip series capacitor [20]. The value of this capacitor must be selected such that the lower frequencies of the microphones output are not attenuated. Using (2), the require input capacitance to the amplifier stage, based on a cutoff frequency of 15 Hz and the microphone output impedance of 5.5 kω, was determined to be approximately 1.93 µf. C = 1 2πf C R (2) Fig. 29. Full ADC Layout featuring complete DAC, comparator and SAR logic. F. Microcontroller The microcontroller is utilized as a peripheral to transmit the converted analog signal to a main processing unit, whether it be a phone or a computer. Considerations are made to minimize the power consumption from the entire system (microphone, SoC, and microcontroller) since all components of the system will be operating using the same battery. Thus, the low power TI CC2650 is selected because for its low power requirement for operation and is capability of using Bluetooth to connect to either a phone or computer [18]. G. Microphone In order to obtain the acoustic signals produced by the knee, a MEMS microphone will be used. MEMS microphones can have mechanical resonances within frequency ranges such as 40 khz, well beyond the 20 khz bandwidth of interest [19]. This removes the concern for any distortion caused by the mechanical properties of the microphone. Additionally, MEMS devices can be fabricated at impressively small sizes, from microns to hundreds of microns [19]. Since one of the objectives for this design is to minimize occupied area on the user s leg, this is a desirable quality. The microphone selected for this design is the InvenSense ICS This device offers a low-noise, low-power method for obtaining acoustic signals from the user. The specifications for this microphone are provided in Table 3. More importantly, this microphone provides an extended frequency response over the desired acoustic range for detecting knee injuries. The following table For simplicity, a standard capacitance of 2 µf will be used. H. Battery Lithium coin cell batteries are typically small, cheap, and commercially available. Every cell is lightweight but has a limited capacity. Putting two in parallel will double the capacity. Additionally, these batteries are rechargeable. Thus, the RJD3555 is chosen because of its output voltage (3.7 V), capacity (500 mah), and size (weight of 14 g, diameter of 35 mm, and height of 5.7 mm) [21]. I. Timing/Clock For the initial design, the clock will be a signal that comes externally from the SoC. This clock will be running on a clock provided by the microcontroller. The microcontroller can provide different clocking frequencies needed for the different parts of the SoC. Additionally, clock dividers, which would just be a D Flip-Flop will be implemented if needed. The clock on the microcontroller is controlled by external crystal oscillators [18]. III. DISTRIBUTION OF WORK Table 12 shows the work distribution among the group members. If the goal is to ensure that every group member has an equal amount of work. If there are any group members that do not have as much work compared another member, the work will be distributed accordingly.

10 10 Name of Group Member Garren Boggs Hua Chen Sridhar Sivapurapu TABLE XII DISTRIBUTION OF WORK IV. CONCLUSION Task Amplifier, Filters Biasing, Linear Regulator ADC This paper proposed an analog front end that would be used to convert the acoustic signals recorded from a MEMS microphone to a digital output. The applications of this SoC could range from high performance athletes to everyday users. However, more testing needs to be done to determine the proper microphone and gain settings to have consistent data. Additionally, more time is needed to get a full system level and post layout simulation to determine the effect of parasitic capacitances on the ADC for example, as well as improve the floor planning of this device. Future work for this device could include introducing logic to control a variable gain amplifier, as well as variable gain/cutoff frequency filters. This type of functionality would be useful for compensating for variance in maximum input amplitudes due to environmental factors. Additionally, eliminating the need for a microcontroller would significantly improve the users comfort during use. This would mean the need for an antenna and to produce a clock signal on-chip. [13] O. 02, "Understanding SAR ADCs: Their architecture and comparison with other ADCs - Tutorial - maxim," [Online]. Available: Accessed: Feb. 3, [14] W. Kester, "MT-021 TUTORIAL ADC architectures II: Successive approximation ADCs," [Online]. Available: Accessed: Mar. 6, 2017 [15] R. Hedayati, "A Study of Successive Approximation Registers and Implementation of an Ultra- Low Power 10-bit SAR ADC in 65nm CMOS Technology," [Online]. Available: Accessed: Mar. 6, [16] K.-M. Lei, P.-I. Mak, and R. P. Martins, "Systematic analysis and cancellation of kickback noise in a dynamic latched comparator," Analog Integrated Circuits and Signal Processing, vol. 77, no. 2, pp , [Online]. Available: pers/57.pdf. Accessed: Mar. 6, [17] Y. Jiang, J. Xi, L. He and K. Sun, "A 16-channel 12-bit rail-to-rail successive approxmation register ADC for AFEs", 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), [18] Texas Instruments, SimpleLink Multistandard Wireless MCU, CC2650 datasheet, Feb [Revised Aug. 2016]. [19] S. B. Lee and P. V. Loeppert, "An impedance spectroscopic study of MEMS microphones," Proceedings of IEEE Sensors, [20] J. Lewis, "Analog and Digital MEMS Microphone Design Considerations," in Analog Devices, [Online]. Available: articles/analog-and-digital-mems-microphone-design-considerations-ms pdf. [21] "Rechargeable LI-ION Batteries," in [Online]. Available: Accessed: Feb. 2, REFERENCES [1] A. P. Nicolini, R. T. de Carvalho, M. M. Matsuda, J. Sayum Filho, and M. Cohen, "Common injuries in athletes knee: Experience of a specialized center," Acta Ortopédica Brasileira, vol. 22, no. 3, pp , [2] C. N. Teague et al., "Novel Methods for Sensing Acoustical Emissions From the Knee for Wearable Joint Health Assessment," in IEEE Transactions on Biomedical Engineering, vol. 63, no. 8, pp , Aug doi: /TBME [3] InvenSense, High Dynamic Range Microphone with Differential Output and Low Power ICS datasheet, Mar [4] "MT-035 TUTORIAL Op Amp Inputs, Outputs, Single-Supply, and Railto-Rail Issues," [Online]. Available: Accessed: Mar. 6, 2017 [5] D. Monticelli, "A quad CMOS single-supply op amp with rail-to-rail output swing", IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp , [6] S. Sakurai, S. Zarabadi and M. Ismail, "Folded-cascode CMOS operational amplifier with slew rate enhancement circuit", IEEE International Symposium on Circuits and Systems. [7] Edgar Sanchez-Sinencio, Low Drop-Out (LDO) Linear Regulators: Design considerations and trends for high Power-Supply Rejection (PSR), 2010 IEEE Santa Clara Valley (SCV), 2010.[Online]. Available: Accessed: April. 30,2017 [8] Baker, R. Jacob. CMOS. 1st ed. Piscataway, NJ: IEEE Press, Print. [9] C. Soares, G. de Moraes and A. Petraglia, "A low-transconductance OTA with improved linearity suitable for low-frequency Gm-C filters", Microelectronics Journal, vol. 45, no. 11, pp , [10] T. Kulej, "Low voltage low transconductance OTA in 50 nm CMOS," ICSES 2010 International Conference on Signals and Electronic Circuits, Gliwice, 2010, pp [11] R. Geiger and E. Sanchez-Sinencio, "Active filter design using operational transconductance amplifiers: A tutorial", IEEE Circuits and Devices Magazine, vol. 1, no. 2, pp , [12] M. Jimenez, A. Torralba, R. Carvajal and J. Ramirez-Angulo, "A new low-voltage CMOS unity-gain buffer", 2006 IEEE International Symposium on Circuits and Systems.