TEMPERATURE COMPENSATED CMOS AND MEMS-CMOS OSCILLATORS FOR CLOCK GENERATORS AND FREQUENCY REFERENCES

Transcription

1 TEMPERATURE COMPENSATED CMOS AND MEMS-CMOS OSCILLATORS FOR CLOCK GENERATORS AND FREQUENCY REFERENCES A Dissertation Presented to The Academic Faculty by Krishnakumar Sundaresan In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in the School of Electrical and Computer Engineering Georgia Institute of Technology December 2006.

2 TEMPERATURE COMPENSATED CMOS AND MEMS-CMOS OSCILLATORS FOR CLOCK GENERATORS AND FREQUENCY REFERENCES Approved by: Dr. Farrokh Ayazi, Advisor School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Paul E. Hasler School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Phillip E. Allen School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Ioannis Papapolymerou School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Levent Degertekin School of Mechanical Engineering Georgia Institute of Technology Dr. Hamid Garmestani School of Materials Science and Engineering Georgia Institute of Technology Date Approved: July 24, 2006.

3 To Amma, Appa, Paatti and Athai

4 ACKNOWLEDGMENTS First and foremost, I would like to express my sincerest gratitude to my advisor Prof. Farrokh Ayazi for providing me with the opportunity, the resources and all the valuable guidance throughout the course of this work. Working under his supervision has been a privilege and a great learning experience, one that I shall forever be grateful for. I would also like to thank my dissertation committee members: Prof. Phillip E. Allen, Prof. Paul E. Hasler, Prof. Ioannis Papapolymerou, Prof. Levent Degertekin and Prof. Hamid Garmestani for their valuable time and input in shaping this dissertation and enabling its successful completion. Special thanks are due to Prof. Phillip Allen for his time and input during the first phase of this work. The successful completion of this dissertation would not have been possible without the help of many of my colleagues. I wish to thank all members of the Integrated MEMS laboratory, past and present, for their support and cooperation throughout the past five years, and in general for the great atmosphere in the group. The past five years have been an invaluable experience, both academic and outside, and I wish to thank the entire group for this. Special thanks are due to Siavash Pourkamali and Reza Abdolvand for their support with the MEMS fabrication. Special thanks are also due to Gavin Ho, who has been my closest research partner for the past 2 years and helped me understand working with MEMS resonators and without whose contributions, this work would not be possible. I also wish to thank Amber Lesher and Janet Myrick for providing timely and iv

5 able administrative support during the course of this work. Special thanks are due to Venkatesh Srinivasan and Ajit Sharma for useful discussions on circuit design, work and pretty much everything under the sky and beyond. Finally, I wish to thank my family for their constant support and encouragement throughout the course of this work, and especially through the harder times. v

6 Table of Contents ACKNOWLEDGMENTS... iv LIST OF TABLES... x LIST OF FIGURES... xi SUMMARY... xiv CHAPTER 1. INTRODUCTION Origin and History Oscillator Requirements and Trade-offs CMOS vs. MEMS vs. Quartz Oscillators Organization CHAPTER 2. CMOS CLOCK OSCILLATOR Introduction System Architecture Circuit Schematics Oscillator and Bias Generator Temperature and Process Compensation for the Ring Oscillator Supporting circuits A. Comparator Voltage Regulator Measurement Results Conclusion CHAPTER 3. MEMS RESONATOR OSCILLATORS Introduction MEMS Resonators Introduction to Capacitive Resonators (Beams) The IBAR The SiBAR Circuits for MEMS Resonator Oscillators System Block Diagram vi

7 3.3.2 CMOS Electronics Sustaining Amplifier Level Control Resonator Biasing Conclusions CHAPTER 4. TUNING AND TEMPERATURE COMPENSATION OF MEMS RESONATOR OSCILLATORS Introduction Electrostatic Tuning for Temperature Compensation Concept Linear Compensation Circuitry Measured Results Parabolic Compensation Introduction System Block Diagram Circuitry Band-gap and PTAT Generator Square-root generation Circuit Measured Results Error Sources Band-gap and PTAT Generator Error Effect of Slope Adjustment Amplifier Offset Square-root Generator Error Charge Pump Error Translation of Voltage Error to Frequency Error Estimate of Worst-Case Error Voltage Scaling Process Compensation and Trimming Comparison of Linear and Parabolic Compensation Micro-Oven Control vii

8 4.4.1 Introduction Concept Circuitry Measured Data Sources of Error Capacitive tuning Concept Limitations Electronics for Resonator Arrays Introduction System Block Diagram Resonator Array Design and Offset IC Electronics Flash ADC structure Frequency Fine Control Measured Results Conclusions CHAPTER 5. PHASE NOISE IN CAPACITIVE MEMS RESONATOR OSCILLATORS Introduction Fundamental theory of phase noise Hajimiri s Model Estimation of 1/f 3 Corner Frequency Effect of amplifier Q-loading Resistive Q-loading Effect of resonator non-linearity Sources of resonator non-linearity Effect on amplifier noise Thermal Noise Flicker Noise Effect of Automatic Level Control Circuit Other sources viii

9 5.7.1 Bias Voltage Noise Random vibrations Temperature gradients Particle adsorption and desorption Summary of Phase Noise Sources Design Optimization Data and Analysis CHAPTER 6. CONCLUSIONS AND FUTURE WORK Technical Contributions Future Work MEMS resonator based VCO for clock jitter clean-up PLLs Introduction and Challenges System Block Diagram Loop Components MEMS resonator based VCO and Buffer Divider PFD, Charge pump and loop filter Tuning and Compensation Charge Biasing Closed loop oven control system REFERENCES ix

10 LIST OF TABLES Table 1.1: Comparison of CMOS, MEMS-based and Crystal-based Oscillators Table 2.1: Summary of results and comparison Table 4.1: Switching Temperature and Frequency Error Table 4.2: Effect of Hysteresis on Switching Temperature Table 5.1: Summary of Phase Noise Sources in Capacitive Silicon Micromechanical Resonator Oscillators Table 6.1: Comparison of specifications of MEMS resonator based oscillators Table 6.2: Required phase noise and harmonic rejection specifications for clock jitter cleaner with 500MHz output Table 6.3: Comparison of phase noise requirements w/ that of the 100MHz oscillator. 122 x

11 LIST OF FIGURES Figure 1.1: Quartz crystals and packaged crystal oscillators typical size ~ 5mm x 5mm 2 Figure 1.2: STMicroelectronics Zeropower NVRAM Product with integrated Real-Time Clock [9]... 4 Figure 1.3: Packaged 60MHz oscillator (Discera) featuring package height of 0.45mm... 4 Figure 1.4: Packaged programmable MEMS resonator based oscillator from SiTime... 6 Figure 1.5: Jitter requirements for ADC clocks [7]... 8 Figure 2.1: Block Diagram of Clock Generator Figure 2.2: Schematic of the differential ring oscillator Figure 2.3: Differential buffer delay circuit Figure 2.4: Replica feedback current source bias circuit Figure 2.5: Schematic of the compensation circuit Figure 2.6: The enhanced compensation scheme Figure 2.7: V CTRL vs. Temperature plot for basic and enhanced schemes compared to the value required to maintain a constant frequency of 7 MHz Figure 2.9: Schematic of the voltage regulator circuit Figure 2.10: Variation of the reference voltage with supply Figure 2.11: Variation of reference voltage with temperature Figure 2.12: Die picture of the oscillator circuit Figure 2.13: Output waveform from oscillator Figure 2.14: Distribution of frequency 25 ºC compensated and uncompensated oscillator curve normalized to the number of samples and expressed in percentage Figure 2.15: Variation of frequency with temperature in compensated samples Figure 3.1: SEM Picture of a typical beam resonator Figure 3.2: Electrical equivalent circuit of the capacitive series resonator Figure 3.3: Mode shape of a typical IBAR Figure 3.4: SEM Picture of the I 2 -BAR Figure 3.5: Open loop frequency response of the resonator at 3V bias xi

12 Figure 3.6: Electrical equivalent circuit of the 5.5MHz I 2 -BAR at 10V bias (L 0 = 15.4H, C 0 =52.8aF, R 0 = 10kΩ, C d0 =C s0 =100fF and C par =2pF) Figure 3.7: Impedance and tuning characteristic of the 5.5MHz I 2 BAR. R 0 = 10kΩ at 10V bias. Tuning = 4600ppm from 2V-25V Figure 3.8: Mode-shape of a typical SiBAR Figure 3.9: SEM Picture of typical SiBAR Figure 3.10: Open loop frequency response of 103MHz SiBAR Figure 3.11: System block diagram of MEMS Resonator Oscillator Figure 3.12: Schematic diagram of sustaining amplifier Figure 3.13: Block Diagram of Automatic Level Control Circuit Figure 3.14: Charge pump used in the bias cell Figure 3.15: Clock generator for the charge pump Figure 4.1: Block Diagram of the linear TC Bias Generator Figure 4.2: Frequency variation of linearly compensated and uncompensated resonatoroscillator with temperature Figure 4.3: Block Diagram of Parabolic Temperature Compensating Bias (TCB) Generator for the IBAR Figure 4.4: Schematic of Band-gap and PTAT generator. BG and PTAT voltages are obtained by choosing different values for the diode sizes (ratio n ) and different resistor sizes (R4/R3) Figure 4.5: Generated BG and PTAT voltages Figure 4.6: Square-root generation circuit Figure 4.7: Comparison of temperature stability of the oscillator with linear and parabolic compensation circuits and with an uncompensated oscillator Figure 4.8: Block Diagram of the Slope Adjustment Amplifier Figure 4.9: Tuning characteristic of 10MHz, 65nm IBAR; Electrostatic Tuning coefficient = 242ppm/V Figure 4.10: Low voltage TC block diagram Figure 4.11: Frequency error due to PTAT and square-root generator inaccuracy Figure 4.12: Total frequency error with low voltage TC bias xii

13 Figure 4.13: Polarization voltage generated by linear and parabolic compensation circuits Figure 4.14: Block Diagram of Micro-oven control for oscillators Figure 4.15: Required and achieved tuning voltage for compensation Figure 4.16: Temperature drift of SiBAR oscillator w/ and w/o compensation Data w/ compensation also shown as inset Figure 4.17: Concept of capacitive tuning for resonator oscillators Figure 4.18: Tuning range of capacitively tuned MEMS resonator oscillator w/ 400aF motional capacitance Figure 4.19: Block Diagram for tuning array of resonators Figure 4.20: Systematic frequency offset for flexural beam resonators and IBARs using lithographic variations Figure 4.21: Frequency error in IBARs with process compensation Figure 4.22: Schematic of single stage of 2-step flash-type ADC with offset null capability Figure 4.23: Simulated tuning characteristic of VCO tuning array Figure 4.24: Measured temperature sensor output Figure 4.25: Fine control voltage and frequency error vs. temperature Figure 5.1: Typical Oscillator Phase Noise spectrum Figure 5.2: Noise Aliasing in an oscillator Figure 5.3: Equivalent circuit of TZ Amplifier and resonator Figure 5.4: Thermal equivalent circuit Figure 5.5: Simulated phase noise of 1GHz differential and single-ended oscillators Figure 5.8: Die micrograph of 1P6M 0.18µm CMOS IC used for the SiBAR oscillator113 Figure 5.9: Die micrograph of 2P3M 0.6µm CMOS IC used for the IBAR oscillator Figure 6.1: Block Diagram of MEMS resonator VCO based clock jitter cleaner Figure 6.2: Block Diagram of MEMS resonator VCO Figure 6.3: Block Diagram of programmable divider Figure 6.4: Schematic of low dead-zone PFD Figure 6.5: Schematic of fully differential charge pump for the PLL Figure 6.6: Closed-loop oven control mechanism for highly stable TCXOs xiii

14 SUMMARY The purpose of this dissertation is to explore alternatives to quartz crystal based solutions to system clocking. While quartz has inherent advantages in terms of stability and cost, the inability to manufacture quartz in a standard silicon process impedes goals of miniaturization and system integration. A closer look at clocking requirements reveals widely different specifications for various applications. In addition to traditional CMOS oscillators such as ring and LC oscillators, the recent advent of micromachining technologies and MEMS resonators has provided a miniaturized, silicon alternative to quartz with potentially comparable performance levels. This provides the system designer with an option to make a clocking solution that most suits the system needs. This work focuses on two aspects: the design of a stable CMOS ring oscillator for microcontroller type applications; and the design of electronics for an ultra-stable MEMS resonator based oscillator for reference oscillator applications. With the former approach, the focus of the research was the design of a process and temperature compensated oscillator to be stable to within 5%. The design, completed in a 0.25µm CMOS process, was stable to within 5.2% over 165 C and 4 different runs. With the MEMS oscillator, the aim of the research was to implement low phase noise, temperature stable oscillators over a wide frequency range. A novel temperature compensation technique was designed to reduce the temperature variation from 2800ppm to 39ppm over 100 C. The sources of phase noise in MEMS oscillators are analyzed and a 100MHz oscillator with sub-100ppm integrated jitter is demonstrated without the use of phase-locking techniques. xiv

15 CHAPTER 1 INTRODUCTION The aim of this research is to investigate the implementation of high accuracy and high stability integrated clock oscillators and frequency references using MEMS and CMOS processes. Specifically, on-chip clock generation schemes in CMOS and frequency references using MEMS resonators are explored. Frequency variation of a typical ring oscillator with temperature and manufacturing tolerances is analyzed and techniques for compensating this variation are proposed. Based on these results, an on-chip clock oscillator for microcontroller-like applications is demonstrated. Oscillators based on MEMS-resonators are investigated as an alternative to quartz crystal based reference oscillators. The drive loop amplifier is optimized to minimize the phasenoise of the oscillator. Temperature stability of MEMS-resonator oscillators is studied and techniques to compensate for temperature variations are proposed. The sources of short term instability of the resonator-oscillator are studied and methods to minimize this instability are suggested. The final goal of the project is to demonstrate feasibility of a temperature stabilized, Q-optimized oscillator based on a MEMS-resonator as a first step towards realization of MEMS-resonator based reference oscillators. 1

16 1.1 Origin and History Clock generation is an important part of any electronic system. Historically, the most common clock references are typically based on quartz crystal oscillators. Crystal oscillators provide excellent stability with variations in supply voltage, temperature and process, but their incompatibility with on-chip integration increases the overall size and the cost of the system. In low cost applications, such as microcontrollers, where nearcrystal accuracy may not be required, on-chip i.e. fully CMOS clock generation can be a useful alternative [1]. Although Bi-CMOS multi-vibrators [2, 3] have been proven to offer excellent temperature stability, the inability to fabricate them in a standard digital CMOS process remains a constraint. The challenge in creating on-chip clocks in CMOS is to achieve frequency stability despite variations in process, temperature, and power supply. Figure 1.1: Quartz crystals and packaged crystal oscillators typical size ~ 5mm x 5mm The problem of achieving a stable clock with temperature and process variation has been addressed previously [3-5]. Temperature compensation requires accurate analysis of variation of several parameters in the fabrication process and design of a stable 2

17 compensating scheme. Process compensation is still an intriguing problem, not only in oscillator design, but in any general circuit design. This is usually accounted for by simulations across multiple process corners to predict the worst-case performance of the system. The study of process compensation of analog circuits is an active topic of research by itself. In [6], the focus is on achieving a process variation tolerant op-amp. As a part of this work, the variation of a popular VCO topology (ring oscillator) temperature is analyzed and a novel compensation circuit is proposed. Further, a compensated clock oscillator based on this topology is also demonstrated. While the clock oscillator scheme is suitable for applications such as microcontrollers, reference oscillators used in high-end applications such as test equipment and most communication systems, have more demanding specifications in terms of stability and spectral purity [7, 8]. In [7], Goldberg discusses the effects of clock jitter on data converter performance and outlines typical jitter requirements. These requirements are typically met only by quartz crystals. Reference [8] is a datasheet from Corning Frequency Control, listing typical quartz crystal accuracies for telecommunication circuit references. The data shows stability in the range of +20 to +50ppm over a temperature range of -55ºC to 100ºC. Recent research has focused on integrating real-time clocks especially for applications such as memories [9]. In [9], ST Microelectronics includes the crystal in the same package as the rest of the circuitry (Figure 1.2). 3

18 Figure 1.2: STMicroelectronics Zeropower NVRAM Product with integrated Real-Time Clock [9] However, with the advent of MEMS, micromechanical resonators have been proven to offer similar performance over a wide range of frequencies [10, 11]. The wide range of frequencies is particularly useful since this eliminates the need for complex frequency synthesizers, which add to system complexity, power consumption and cost. The field of micromechanical signal processors (filters and resonators) is still an active area of research [10-13]. Specific to this work, oscillators based on micromechanical resonators have been proven to offer near-crystal oscillator performance [13, 16-17]. In [16], Nguyen reports a fully integrated CMOS-MEMS oscillator at 400 khz and in [17], a 60 MHz 2-chip oscillator is reported (Figure 1.3 and 1.4). Figure 1.3: Packaged 60MHz oscillator (Discera) featuring package height of 0.45mm 4

19 Much of the research towards the implementation of resonator-oscillators has focused on the characterization and improvement of the quality factor and phase-noise of the resonators [10-12]. While quality factor is one of the most important characteristics of the device, the temperature stability of the oscillators is also an important criterion for reference oscillators. The temperature variation of the micromechanical resonator-based oscillator is inherently better than most CMOS implementations, but still largely inferior to crystals with specific cuts. Efforts toward compensating for the temperature variation have been reported earlier [14, 15], but they are typically based on using mechanical properties of the resonator such as stress compensation or heating. Specifically, Nguyen s group has reported on geometric stress compensation in [14] and Kenny has reported compensation based on filament heating of the electrodes [15]. Electrostatic compensation of resonators remains a topic that has yet to be researched seriously. Although the resonators are manufactured on silicon wafers, the fabrication process is different from the standard CMOS process. Nguyen demonstrated feasibility of singlechip integration in [16], but this remains restricted to lower frequencies. Further, this would still require changes to the CMOS process which would be very expensive for an established foundry. Recent research [17] has instead focused on a two-chip solution that can be integrated at a package level. 5

20 Figure 1.4: Packaged programmable MEMS resonator based oscillator from SiTime Phase noise in oscillators has also been an active field of study over the years [18, 19]. While extensive studies have been carried out on the sources of phase noise in CMOS oscillators, research on resonator oscillator phase noise is still under active research. Apart from the electronic sources of noise, a number of additional sources including device non-linearity, the effect of the amplifier loading and resonator bias voltage noise contribute to phase noise in capacitive MEMS resonators. While studies have investigated some of these sources [20-22] a comprehensive study of the sources of phase noise source is still lacking. 1.2 Oscillator Requirements and Trade-offs The fundamental properties of an oscillator are: 1. Absolute frequency: The frequency of oscillation 2. Wave-shape: The waveform generated by the oscillator (sinusoidal, square etc.) 3. Tuning range: The extent to which the frequency can be varied by a controller 6

21 4. Short-term stability: A measure of frequency instability in real-time under typical operating conditions (cycle to cycle variation) 5. Long-term stability: A measure of frequency instability over time and environmental factors 6. Output power Apart from these fundamental properties, size and power consumption are important from a system perspective. An ideal oscillator is of course, infinitely tunable and has infinitesimal short-term and long-term variation. This can theoretically be achieved, if we make an oscillator that varies with one control signal and that control signal is error-free. Since this is impractical, we have a fundamental trade-off between tuning range and stability. Addressing this trade-off requires tailoring the oscillator to the system it serves. For example, a typical micro-controller requires a frequency accuracy of 2-5% (both short-term and long-term). Low cost and power are of utmost importance and the tuning range required is dependent on the flexibility required in the system. Hence, a microcontroller clock should ideally be implemented on-chip to be commercially viable. Variation of typical on-chip oscillators (RC and ring oscillators) is in the range of 10-30% and the oscillators are widely tunable with a control voltage. Hence, a control circuit should also be integrated with the oscillator to meet the accuracy specification and the tuning range requirement. 7

22 The clocking requirements for a high resolution and/or high speed data-converter, on the other hand, are far more stringent. Fig. 1.5 below shows the clock timing jitter required for high frequency and high resolution ADCs. This poses stringent demands on shortterm stability of the reference clock. The relationship between clock jitter and the SNR of an ADC is given by (1-1). The clock jitter can be related to the phase noise and the quality factor (Q) of the resonator through (1-2) and (1-3). For example, to achieve 14-bit accuracy, an ADC clock would require a resonator loaded-q of or higher [1]. Figure 1.5: Jitter requirements for ADC clocks [7] 1 σ RMS = (1-1) 2πf * SNR σ t = α( f m )sin ( πfτ ) df (1-2) 2 ω 0 8

23 2 1 1 f off FkT 0 f + α α( f = + m) 1 1 (1-3) 2 2 f m 2QL P o fm The stringent Q requirements for such applications rules out using purely electronic oscillators since the quality factor of on-chip tanks is restricted to a few tens. However, with the advent of micromachining and MEMS resonators, these requirements can still be met while miniaturizing the system and lowering cost. 1.3 CMOS vs. MEMS vs. Quartz Oscillators Table 1.1 compares typical characteristics of CMOS, MEMS resonator and crystal based oscillators based on typical datasheet specifications. The table clearly shows an increase in stability as we move from electronic oscillators to quartz oscillators along with an increase in size and power and decrease in tuning and frequency range of applicability. The table also clearly delineates the range of applications for which CMOS and crystal oscillators are most suited. The demarcation for a MEMS-based oscillator is less clear since the design of the resonator can be optimized for larger tuning or better stability. However, since MEMS-CMOS oscillators cannot compete with fully integrated CMOS oscillators on cost, it is prudent to optimize the design of the MEMS resonator to be able to compete with the quartz on the applications that require better stability. 9

24 TABLE 1.1: COMPARISON OF CMOS, MEMS-BASED AND CRYSTAL-BASED OSCILLATORS Property CMOS Oscillators MEMS-CMOS Oscillators Crystal Oscillators Frequency range khz-ghz khz-ghz khz~100mhz Tuning range >10% 100ppm 10% <1000ppm Temperature Variation ~200 ppm/ºc (after compensation) 5-20 ppm/ºc ppm/ºc Quality factor <20 >10 4 >10 4 Overall accuracy (without correction) Power (including controller) ~20 % ~2000ppm ppm ~1mW ~10mW ~100mW Area ~0.1mm 2 ~1mm 2 >10mm Organization The dissertation is organized into six chapters: Chapter 1 provides an introduction to the problem and identifies potential solutions and provides a comparison of the different clock generation techniques. Chapter 2 is focused on the discussions related to the fully integrated CMOS oscillator. The stability limit of a widely tunable CMOS based ring oscillator is analyzed and a control circuit is designed to improve the stability to process, temperature and supply variations so that the stability of the ring oscillator after compensation can meet the requirements of a micro-controller clock. Chapter 3 provides an introduction to capacitive MEMS-resonator based oscillators. Different resonator designs and their salient features that can be exploited in the design of the oscillator are presented. The block diagram of a capacitive MEMS resonator 10

25 oscillator is introduced. Sustaining amplifiers for the implementation of the oscillators are discussed. Other circuit blocks for level control and resonator biasing are discussed briefly. Chapter 4 presents a detailed look at the tuning, biasing and temperature compensation of capacitive MEMS resonators. The idea of electrostatic tuning, which is unique to MEMS resonators, is introduced and circuits to exploit this property for temperature compensation are designed. The improvement in temperature stability based on this biasing technique is reported. Sources of error and limitations in the circuit blocks are identified and techniques for voltage scaling, trimming and design in a manufacturing environment are identified. Controllers are designed for tuning MEMS resonators for meeting the stability and tuning range requirements. The sources of short-term variation in a MEMS resonator oscillator are studied and the design of the electronics is optimized for low phase noise oscillators. Other tuning techniques such as resonator oven control and capacitive tuning are also explored. Chapter 5 discusses the details of phase noise and short-term frequency variation in capacitive MEMS resonators. The effect of electronic thermal noise and 1/f noise on phase noise has been discussed extensively in literature. Based on a high-q assumption, a closed-form expression is derived for the phase noise 1/f 3 corner frequency. The effect of resonator non-linearity on phase is discussed as is the influence of automatic level control. Other sources of noise such as the effect of resonator bias voltage noise and effect of particle adsorption and desorption are also discussed. Experiments have been 11

26 conducted to identify the effect of the major sources of phase noise and techniques to optimize the design of the resonator and the amplifier are suggested. Chapter 6 provides an overview of the contributions of this work to the field and identifies future directions of research in the field of integrated clocking references. 12

27 CHAPTER 2 CMOS CLOCK OSCILLATOR 2.1 Introduction As established in Chapter 1, clock generation is an important component of any digital circuit. For cost-critical applications such as microcontrollers, accuracy of 1-5% is sufficient. However, chip level integration is essential to maintain small form factor and cost. Although Bi-CMOS multi-vibrators [2, 3] have been proven to offer excellent temperature stability, the inability to include them in a standard digital CMOS process remains a constraint. CMOS LC and ring oscillators offer ready solutions to integrated clocking. The biggest challenge with these, of course, is the problem of achieving a stable clock with temperature and process variation. This issue has been addressed previously [4-6]. While some techniques [5, 23] use external references in the tuning scheme, a fully integrated solution is essential to minimize board area and cost. Process compensation is an intriguing problem and is usually accounted for by simulations across multiple process corners to predict the worst-case performance of the system. Process corners are usually defined based on variations in oxide thickness, threshold voltage and the deviation in the transistor width and length (dw D and dl D ) [24]. However, this approach cannot account for the adjustments made to in-line parameters (such as oxide thickness and doping 13

28 concentrations) to maintain certain end-of-line parameters (like threshold voltage) fixed. This could mean that the simulation results across multiple process corners may not be accurate. In this chapter the compensation of a ring-oscillator-based clock generator designed in a 0.25µm CMOS process is discussed. The design incorporates a unique combined temperature and process compensation circuit. The temperature and process variation for the oscillator has been analyzed and an adaptive biasing circuit that provides a control voltage to maintain a constant frequency with temperature and process variation is designed. Two variants of this circuit are identified and the performance of each of these is analyzed in providing an accurate biasing voltage to maintain a constant oscillation frequency with temperature and process variation. Results measured from 4 different runs are compiled and results are compared with simulation and with results from an uncompensated oscillator. Some of the support circuitry including a band-gap reference based voltage regulator and a rail-to-rail comparator are also discussed. 2.2 System Architecture Figure 2.1 represents the block diagram of the clock oscillator system [25], which is based on a ring oscillator structure. A band-gap referenced voltage regulator is used to generate a supply and temperature independent reference voltage, V REF. This serves as a stable temperature independent supply voltage for the oscillator and the supporting 14

29 circuits. The system uses a voltage controlled differential ring oscillator to generate a reference frequency. In the frequency compensation circuit, a threshold voltage sensing circuit generates a process-dependent reference voltage from V REF, which is supplied to the temperature compensating circuit. The output of the compensation circuit is a control voltage, V CTRL, which stabilizes the frequency of oscillation by varying a reference current, I REF. The output of the oscillator is converted to a full swing rail-to-rail clock signal by a process independent voltage comparator [26] to make it compatible with standard digital logic and increase noise immunity. The comparator also ensures that the clock duty cycle stays at 50%. Figure 2.1: Block Diagram of Clock Generator 2.3 Circuit Schematics Oscillator and Bias Generator The reference frequency is created using a ring oscillator configuration with three differential delay stages as shown in Fig Since a rail-to-rail output was sought, a 15

30 comparator was included at the output of the final stage. To eliminate the asymmetric loading of the delay stages caused by the comparator, buffer and dummy delay stages were used. The individual delay stages consist of a source coupled pair and a symmetric load as shown in Fig. 2.3 [27]. The time delay produced by the circuit is given by: t d C ( V V ) I o H L (2-1) ref where C o is the total capacitance seen at the output of each stage. I ref is the bias current of the circuit and V H -V L is the output voltage swing. V H and V L are equal to V REF and V CTRL respectively. The time delay can be adjusted by changing the bias current and/or the output voltage swing, which can be accomplished by changing V CTRL. Figure 2.2: Schematic of the differential ring oscillator 16

31 Figure 2.3: Differential buffer delay circuit The bias generator for the oscillator is the replica feedback current source bias circuit [27] shown in Fig The circuit changes the lower rail voltage by changing V CTRL to maintain the correct delay time under all conditions. Figure 2.4: Replica feedback current source bias circuit 17

32 Assuming large transistor lengths (for the square-law approximation) and under conditions of a symmetric load, the currents in the two branches of the load are identical. Under these conditions, the total bias current of delay stages is given by: I ref 4 2 ( Vref VT 4 Vctrl 4 W K ' 4 ) (2-2). L The frequency of oscillation is: f 1 = (2-3). Nt d where N is the number of delay stages and t d the time delay of each element. By combining equations (2-1) and (2-3), the frequency of oscillation can be expressed as a function of V CTRL : f = 1 N. t d = K ' 4 W4 L 4 N C ( V V V ) o ref ( V V ) ref T 4 ctrl ctrl 2 (2-4) Temperature and Process Compensation for the Ring Oscillator To compensate for temperature and process variations, we change V CTRL so as to maintain the frequency constant. The critical parameters that vary with temperature are the mobility of the charge carriers and the threshold voltage. The relationship governing the variation can be approximately written as [28, 29]: 2.2 µ p T (2-5). 18

33 V T ( T 0 0 TO V T T ) = V K ( T T ) = V (1 + α ) (2-6). T where the temperature coefficient α V T is negative. The junction capacitance model in BSIM is usually modeled in the form [30]: C x = C ( 1+ α T) (2-7). xo Cxo A similar linear dependence with a negative temperature coefficient can also be used for the oxide capacitance [31]. Process variation is mainly due to variations in gate oxide thickness and doping concentrations. These change the threshold voltage and the K of the MOS transistor. As a result, the oscillation frequency shifts with process even if the system is compensated for temperature variations. By rearranging (2-4), one can get the following relationship between V CTRL and f (the oscillator frequency): V ctrl = V ref V TP 1. 2 f. N. C0 K ( W / L) ' V TP f. N. C0 K ( W / L) ' 4 4 f. N. C0 + ' K 4 ( W / L) 4 2 (2-8). The second term inside the square root is at least 10 times smaller than the first term for the given conditions of f, N and C 0 (f=7mhz, N=3 and C 0 is approximately 220fF) and hence can be neglected. The first goal is to keep the oscillation frequency constant with temperature. By using (2-5) and (2-7) in (2-8), the term under the square-root can be expressed as a function of temperature. The expression can be further approximated using Taylor series as: 19

34 V TP V T 0 f. N. C ' 4 (1 + α 0 K ( W / L) VT 4 T ). f. N. C µ p0 = T V 2.2 T 0 µ p0 xo C (1 + α T ). f. N. C T ox0 2.2 C (1 + α VT ox0 C xo ( W / L) (1 + α T )(1 α 4 xo Cox 0 Cox 0 (1 + α T )( W / L) T ) Cxo T ) 4 (2-9). In (2-9), since the temperature coefficients ( α Cx0, α V andα T Cox ) are quite small, the contribution of higher order terms are small and hence can be neglected. With this approximation, we can use (2-6) and (2-9) in (2-8) and simplify the expression as: V ctrl A BT 2 CT (2-10). where A, B, and C are parameters that vary with process corners and given by (2-11) as a function of frequency, voltages and device parameters. A V ref V Tp0 1 f. N. C x0 B. 2 µ p0cox0 ( W / L) C α VTV T 0 + µ V p0 T 0 C 4 ox0 f. N. C xo ( W / L) 4 (2-11). For the choice of f, N and C 0, B is at least 10 times smaller than C, and (2-11) can be further simplified as: V ctrl A C. T (2-12). Therefore, in order to compensate for temperature variations, the slope of the control voltage with respect to temperature is negative; this can be supplied by V BE of a BJT. However, in order to simultaneously achieve process compensation, (2-10) or the linear approximation (2-12), must be satisfied for all process conditions. 20

35 Compensating for these variations can be thought of intuitively as tracking the threshold voltage and the mobility of the transistors. The threshold voltage is easily tracked using a diode connected MOS transistor supplied by a reference voltage. The mobility variation can be tracked with the resistivity of the layer. Hence, the bias voltage should comprise of an appropriate resistor to track mobility variations. The simultaneous compensation of process and temperature variations is achieved by detecting the process corner using a threshold voltage sensing circuit and using that information to create a process-dependent voltage reference for the temperature compensation circuit. Figure 2.5 shows the schematic of the complete compensation circuit. The part of the circuit to the left is a self-biased reference circuit that provides a temperature independent current source, limited only by the matching of the resistors. The op-amp buffer stage boosts this reference level to V TREF, 2.2V under typical conditions, but sensitive to the threshold voltage drift of M6. The control voltage generator (shown as a part of Fig. 2.5) is implemented using a diode connected PNP transistor Q3 that provides a negative temperature coefficient. The temperature slope of V CTRL can be adjusted through the W/L ratio of M9. The temperature shift caused by the R3-R4 feedback in the amplifier is ignored, since the effects cancel out to the first order. 21

36 Figure 2.5: Schematic of the compensation circuit The sizes of transistor M9 and the resistor R5 are chosen so that the expression for V CTRL satisfies (2-12) across multiple process corners. From Fig. 2.5, the control voltage is given by: V CTRL 2I = VTREF VT 9 (2-13). µ C ( W / L) p ox 9 Writing an expression for the current I and eliminating I to solve for V CTRL, we get: V CTRL ( V = ( V TREF TREF V T 9 V Tp 1/ R µ C 1/ R µ C 5 p ox 5 p ox ( W / L) ) + 2 ( W / L) ) ( V 9 9 TREF V T 9 + 2V BE / R µ C 5 p ox ( W / L) 9 ) (2-14). The V BE term gives rise to a negative temperature coefficient, the slope of which can be changed by varying R 5 or (W/L) 9 of the PMOS. This circuit can be designed to give the 22

37 required temperature slope across multiple process corners by designing (W/L) 9 and R 5, such that (2-12) is satisfied across multiple process corners. For the optimization to be robust, it is essential to account for the temperature and process variations in the resistor. This is modeled as a +10% variation in the value of resistance with process and a linear temperature coefficient, both of which are typical for poly-silicon resistors in CMOS. While designing the compensation circuit, it was determined that better compensation can be achieved by obtaining a larger change in V CTRL with process (to obtain a better curve fit across multiple process corners). This was implemented by a modified cascade of two of the existing stages. The V CTRL generator was hence modified to that of Fig In this section, the resistors R1 and R2 and the transistors M2 and M3 are designed to satisfy equation (2-12) across multiple process corners. In either case, the coefficients for (2-10) were computed and found to match measured data to within 20%. This indicates that the approximate expressions used for hand-calculation were reasonable. V TREF V X M1 M3 I R1 R2 V CTRL M2 Q1 Figure 2.6: The enhanced compensation scheme 23

38 For the circuit of Fig. 2.6, it may be seen that the second part of the circuit is the same as the basic circuit and the expression for V CTRL will be the same as (13) except that V TREF will be replaced by a voltage say V X. Now, V X can be solved in a similar fashion as in the former case. V X is given by: V X 2I = VTREF VON1 = VTREF (2-15). µ C ( W / L) p ox 1 Now the current in the first branch can be written and simplified. Further, assuming that the transistors M1 and M2 are sized large and such that there ON voltages are approximately equal an expression for V X can be written as: V X 2( V V ) TREF T 2 VTREF (2-16). R1µ pcox ( W / L) 1 Now, V X can be adjusted to fit the required slope for various temperature and process conditions by changing the size of M2 and R1. V CTRL has two additional control parameters in M3 and R2. The enhanced compensation scheme thus has four parameters to fit the required V CTRL profile as compared to two in the simple scheme. Further, notice that the V CTRL expression for the basic scheme does not have a dependency on NMOS process parameters whereas for the enhanced scheme V X does have a dependency on V T2. Hence, the basic circuit may not be able to generate the required V CTRL profile across all process corners (unless PMOS and NMOS process variations are 100% correlated). Figure 2.7 shows the required and curve-fit implemented plots of V CTRL versus temperature for various process conditions for both the basic (shown in dashed lines) and 24

39 the enhanced compensations scheme (shown in solid lines) and compares these with the theoretical value required for maintaining a constant frequency (shown as discrete points). It can be seen that the enhanced compensation circuit (figure 2.6) does provide an excellent fit to V CTRL for all process conditions, whereas the basic scheme does not do a great job at the slow process corner. We can infer that the basic scheme can be used to generate the V CTRL slope fairly accurately, but the required process dependent level-shift may not be attained across all process corners. The enhanced compensation scheme addresses this problem by introducing an additional process dependent term through V T2, thus making the compensation technique more effective. The compensation technique used here can be implemented in any CMOS process in which resistors are available. The substrate PNP transistor in the compensation scheme can be replaced by a simple p-n junction diode. The results for mixed process corners have not been provided here, since they are highly unlikely to occur [24] and even if they do occur, the frequency variation is less than that of the extreme conditions. 25

40 1.4 Vctrl vs Temp Vctrl [V] Temperature [ºC] Reqd_fast Reqd_typ Reqd_slow Enhanced_fast Enhanced_typ Enhanced_slow Basic_fast Basic_typ Basic_slow Figure 2.7: V CTRL vs. Temperature plot for basic and enhanced schemes compared to the value required to maintain a constant frequency of 7 MHz Supporting circuits A. Comparator The comparator shown in Fig. 2.8 is used to convert the differential input signal of the ring oscillator to a single-ended, digital logic compatible output voltage with a full ground to supply swing. We used a process-independent threshold voltage invertercomparator [26] in this architecture. The first stage comprises of a common drain input buffer (M11-M14) to minimize the loading capacitance seen by the ring oscillator and a source coupled pair configuration (M15-M19) to amplify and convert the differential 26

41 voltage input to single-ended output. The bias voltage V CS for this circuit is generated from the replica bias circuit used for the oscillator (figure 2.4). In the inverter-comparator circuit, the M6-M7 inverter acts as a logic switch with the transistors M5 and M8 serving as triode MOS resistors to compensate for changes in the threshold voltage due to process and temperature drift. The bias resistors R1 and R2 set the threshold voltage of the comparator to mid-rail. An increase in the threshold voltage due to drift, decreases M8 and increases M5, thus serving as a negative feedback to bring the threshold voltage back to the desired value. The systematic offset of the comparator, and consequently the duty cycle of the oscillator, is set by the matching accuracy of R1- R2 and the offset in the amplifier. Transistors M1, M2, M3 and M4 are designed to be the same sizes as M5, M6, M7 and M8 respectively and they follow the action of the latter. The threshold voltage of the comparator is thus set at mid-rail independent of process and temperature variation. Inverter M9-M10 is used to buffer the signal out. Figure 2.8: Schematic of process-independent inverter-comparator 27

42 Voltage Regulator The voltage regulator provides the system a temperature and supply independent reference voltage and power supply. The circuit, which is shown in Fig. 2.9, is primarily divided into two sub-circuits: A band-gap reference with a stacked CMOS topology [32] and a feedback transconductance amplifier that raises the output of the band-gap circuit from 1.25V to 2.2V (through the R 5 -R 6 feedback loop). The supply voltage and temperature variation characteristics of the reference voltage are shown in Fig and Fig for different runs. The data collected represents an average from 10 different samples from a run. No trimming was performed on the resistors. The variation in absolute value of the reference voltage and the Zero- Temperature Coefficient (ZTC) point is apparent in the curves. The measured variation of V REF with temperature is an average of 0.2% and the variation across multiple runs is about 0.5%. While this value can be improved, the lack of trimming in the band-gap would limit the ultimate accuracy of this voltage with process variations. This value, while being quite small, will affect the accuracy of the compensation scheme. 28

43 Figure 2.9: Schematic of the voltage regulator circuit Variation of Vref with Supply Vref [V] Vcc [V] Simulation Measured_average_set1 Measured_average_set2 Figure 2.10: Variation of the reference voltage with supply 29

44 2.224 Regulator Voltage Temp. variation Vref [V] Temp drift = 1820ppm Temperature [ºC] Simulation Measured_ave_set1 Measured_ave_set2 Figure 2.11: Variation of reference voltage with temperature 2.4 Measurement Results The oscillator system was implemented in a 0.25µm CMOS process provided by National Semiconductor Corporation. The enhanced compensation scheme was incorporated in the design due to the advantages. A total of 94 die samples of the designed oscillator system collected from 4 different runs have been tested for performance over a temperature range of 40ºC to 125ºC. In addition, 57 samples of the oscillator without the V T -sensor scheme were also tested from 2 distinct runs. The compensated clock oscillator demonstrated a worst-case variation of +2.64% in its output frequency (7.03MHz) over the 165ºC temperature range and across the 94 die samples. Table 2.1 provides a summary of the measurement results from the oscillator system and a comparison of the results with simulation for both compensated and uncompensated systems. The overall 30

45 area of the circuit (including the pads) is about 1.6mm 2. Though the system is designed to work with supply voltages in the range of V, the process limits the normal supply voltage to about 2.75V. Hence, measurements were not made for supply voltages beyond 2.75V for most chips. (The bandgap circuit alone was tested up to 3.5V in a few chips). The overall power consumption of the circuit was about 1.5mW, largely because of the op-amp in the voltage regulator, which was designed to drive large loads. Fig shows a typical die picture. Figure 2.12: Die picture of the oscillator circuit Figure 2.13 shows a typical output waveform of the clock generator with a supply voltage of 2.4V. It can be seen that the signal swing is almost rail-to-rail and the frequency is at the target value. Further, the rise and fall times are quite small and the duty cycle is close to the target value of 50%. 31

46 Figure 2.13: Output waveform from oscillator Figure 2.14 gives the distribution of the measured frequencies at room temperature for both the compensated and the uncompensated systems on a normalized scale. It may be noticed that for the compensated system, 95% of the samples measured to within + 0.5% of the mean, as compared to + 2.5% for the uncompensated version. The standard deviation improved from khz to 9.3 khz. Also, more than 72% of the compensated samples fell within +0.25% of the mean value, as compared to 27% for the uncompensated samples. 32

47 Frequency distribution among compensated and uncompensated oscillator samples Percentage of samples [%] Deviation from mean [%] Uncompensated Compensated Figure 2.14: Distribution of frequency 25 ºC compensated and uncompensated oscillator curve normalized to the number of samples and expressed in percentage Figure 2.15 shows the variation of the output frequency with temperature (averaged over the 94 samples). It is noticed that the behavior is very similar to what is predicted by simulation except for a small offset. This is most likely because the correlation between the process parameters of the different runs is likely to be different from what is available in the corner models. For instance, it is likely that in order to maintain the threshold voltage constant, a small variation in the oxide thickness may have been offset by a change in doping concentration during an actual fabrication run and this effect may not be captured by the simulator unless simulations are carried out with different models 33

48 representing each run. However, we can see that even with the current models, the temperature variation characteristic matches reasonably well Freq vs. temp (Simulation and Measured) Frequency [MHz] Measured_ave Simulation_typ Temperature [ºC] Figure 2.15: Variation of frequency with temperature in compensated samples We also tested a version of the oscillator scheme without the process compensation scheme (V T sensor) to evaluate the effect of the same on the compensation scheme. While the V T sensor scheme was omitted from the design, the band-gap and the temperature dependent V CTRL generator were still included. Table 2.1 summarizes the results obtained from the compensated and uncompensated systems and provides a comparison of the data with simulation. The supply voltage performance of the design is eventually dependent on two factors: the accuracy and PSRR of the band-gap circuit and the control voltage generation block. Since the same band-gap is used for both compensated and uncompensated versions of the design, the supply voltage variation is quite similar for both cases. Figure 2.16 shows a plot of the temperature variation of frequency for the 34

49 compensated and uncompensated systems (both measured). It may be observed that in the uncompensated scheme, the frequency variation with temperature is much larger even though only the V T -sensing circuit is absent. The absence of the V T sensing circuit means that the supply to the V CTRL generator is V REF and not V TREF and this would changes the temperature slope of the control voltage from what is described by (2-12). This affects the temperature compensation circuit and hence the shift in frequency. TABLE 2.1: SUMMARY OF RESULTS AND COMPARISON Property Compensated simulation Number of samples tested Frequency achieved (MHz) Variation with supply (2.4V-2.75V) Average Variation with temp (typical 2.5V, 40ºC to 125ºC) Variation w/ process (25ºC, intra run) Variation w/ process (25ºC, inter run) Standard deviation (ΜΗz) Worst case variation (process & temperature intrarun) Worst case variation (process & temperature interrun) Compensated test Uncompensated simulation Uncompensatedtest % 0.31% 0.3% 0.45% % % +2.7% +4.9% % % Run % Run % Run % Run % % +24.7% Run % Run % N/A Run % Run % Run % Run % % +31.6% Run % Run % +11.8% Duty cycle 49.8% 49.6% 49.8% 49.5% Variation in duty cycle + 2.2% + 2.4% + 2.9% + 3.2% 35

50 7.2 Freq. vs Temp (Compensated and Uncompensated) Frequency [MHz] Measured_ave Uncompensated Temperature [ºC] Figure 2.16: Comparison of measured results - Compensated vs. Uncompensated An important characteristic observed in measurement was the large difference between the process variation predicted by simulation and measurement in the uncompensated samples. This is largely a result of the fact that the samples come out of only two distinct runs and the process variation across these two runs may not have been significantly large. However, for the compensated samples, the simulated process variation is quite similar to the intra-run variation. While trying to explain the apparent discrepancy, it is useful to mention that the simulation data does not include results from Monte Carlo simulations (due to lack of correlation data). This means that these random process effects are unaccounted. Also, the accuracy of the measurement system is about 0.3%, which adds to measurement error. These errors are not significant for the uncompensated case where the variation is already quite large (predicted variation of +31.6%). However, 36

51 for the compensated case, the lack of Monte Carlo simulation data would add a significant error in the predicted variation (+1.7%). For instance the doping concentration and oxide thickness may not be correlated as predicted by the corner models resulting in a threshold voltage value close to typical but with different C ox. This is the most likely reason for the discrepancy in simulated and measured variation for the compensated and uncompensated samples. It may be noted that the supply voltage compensation remains consistent since the bandgap reference regulator was used as a supply in either case. The frequency stability is improved by more than 4.5X with the introduction of the compensation scheme. The average process variation within a single run at room temperature is +1.1% with compensation whereas it is almost +8% without it, a 7X improvement. The frequencytemperature curve follows the trend predicted by simulation fairly closely, except that the value is slightly higher (about 0.02 MHz), which can be explained as an effect of uncorrelated process parameter variation that cannot be predicted by simulation. 2.5 Conclusion On-chip integration of precision clock generators is an important task for reducing cost and size of a digital circuit. In this chapter, a 7-MHz ring-oscillator-based clock generator compensated for variations in supply voltage, temperature and process conditions without the use of trimming techniques has been demonstrated. The oscillator has been implemented in a standard 0.25µm CMOS process and the output is compatible with standard digital logic. 95% of the measured samples (94 samples across 4 runs) were 37

52 within +0.5% of the mean as compared to less than 50% for the uncompensated samples. The overall measured variation was +2.6% of the mean across the samples over a temperature range of -40ºC to 125 ºC. As we can observe, CMOS based oscillators can provide reasonable stability with respect to PVT variations and are suited toward the implementation of low power, fully integrated clocks for micro-controller type applications. However, the stability of these oscillators remains far inferior to quartz and hence we need a different solution for high performance time bases. 38

53 CHAPTER 3 MEMS RESONATOR OSCILLATORS 3.1 Introduction As established in the previous chapters, CMOS oscillators cannot achieve the stability and accuracy required for high precision time bases. However, the advent of silicon micro-mechanical resonators provided a feasible alternative to quartz for such applications. This is because, micro-mechanical resonators inherently offer twin advantages of batch processing on standard silicon wafers and miniaturization. Further, the design of these devices can be optimized for specific frequency ranges thus ensuring optimal designs for a wide frequency range on the same chip. This is a convenient alternative to using multiple crystals and power hungry synthesizers for complex systems with multiple references. In this chapter, different resonator designs developed in this work are discussed briefly and their suitability to specific frequency ranges identified. The circuit requirements for a basic MEMS resonator oscillator are identified based on these discussions. 3.2 MEMS Resonators Introduction to Capacitive Resonators (Beams) Micro-electro-mechanical resonators are typically classified based on the physical principle used for sensing and actuating the devices. The devices are most commonly 39

54 capacitive or piezoelectric and the ones that are discussed in the following sections are largely capacitive meaning that the force is applied to the resonator by a voltage that is coupled capacitively and the output is sensed as a change in charge. The characteristics of the resonator are dictated by the system-level requirements: to achieve low phase noise, low power consumption, and reduced frequency-temperature drift, the micromechanical resonator must have high quality factor, low motional impedance, and high tunability. The simplest micro-resonator is a vibrating beam, which can be thought of as a miniaturized guitar string [10]. These devices have been modeled extensively, and the frequency of vibration is given by (3-1). W E = 1.03 (3-1) L ρ f 2 where W and L are the resonator width and length, E is the Young s modulus of the material and ρ is its density. A typical beam resonator is shown in Fig Figure 3.1: SEM Picture of a typical beam resonator 40

55 The equivalent circuit for this device (and for all series resonators) is as shown in Fig The approximate expressions for the electrical equivalent parameters are given by (3-2), (3-3) and (3-4). 2 K1d d 2 2 d 0 V p L = (3-2) C ω 2 m 2 2 Cd 0 V p C = (3-3) 2 2 V p Cdo K1d d ( 1 ) 2 K d 1 d 2 do 2 d 2 p m 2 d 2 do KM d Kd R i = = = QC V Qω C V C 2 p 2 Dd d 2 2 do V p (3-4) Figure 3.2: Electrical equivalent circuit of the capacitive series resonator. It can clearly be seen that as frequency increases, the length necessarily shrinks and the impedance increases. This limits the frequency range of applicability of these devices to a few MHz. Further, the amount of energy stored in the flexural mode is quite small and the quality factor of the resonator is lower than typical quartz resonators. Hence, to 41

56 simultaneously meet higher Q and tuning requirements, we need to look at alternative resonators The IBAR The three requirements: low impedance, high quality factor and wide tuning are typically difficult to achieve simultaneously with a micromechanical resonator. While flexural mode capacitive beam resonators are highly tunable, they have high impedances and low Q. Conventional extensional mode capacitive resonators can have high Q and lower impedances, but suffer from low tunability. Piezoelectric resonators are another alternative; they have lower impedances, but no effective tuning technique has been demonstrated for these resonators. The I-shaped Bulk Acoustic Resonator (IBAR) is designed to meet all the above requirements simultaneously [33]. The structure resonates predominantly in a lateral extensional mode. Large flanges are placed at the ends of the extensional beams for increasing the capacitive transduction area (Fig. 3.3). The device can hence be described as a hybrid mode resonator. The design of the resonator can hence be optimized to enhance tuning or quality factor, thus providing the designer an additional degree of freedom to meet system requirements. The resonator fabricated using the HARPSS-on-SOI process [11] is shown in Fig The resonator in Fig. 3.4 had a resonant frequency of 5.58MHz with a Q of The 42

57 frequency response is shown in Fig The electrical equivalent parameters of the IBAR are shown in Fig. 3.6 [34]. Figure 3.7 provides the impedance and tuning characteristic of the device as a function of the bias voltage and the relationships are shown in (3-5) and (3-6) respectively. Clearly, the characteristics deteriorate as we scale up in frequency. Hence, there exists a specific window of frequencies for which the IBAR is an ideal solution. k d R = x ϖ QV A (3-5) n 4 n Pε 2 o f f 0 εaf = ( V V ) k P d 3 n o P0 (3-6) Extensional Mode L e L w m L e = electrode/flange length w e = flange width L = rod length w m = rod width h = thickness w e Figure 3.3: Mode shape of a typical IBAR 43

58 Figure 3.4: SEM Picture of the I 2 -BAR f = 5.59MHz; V P = 3V; Q = Figure 3.5: Open loop frequency response of the resonator at 3V bias 44

59 Figure 3.6: Electrical equivalent circuit of the 5.5MHz I 2 -BAR at 10V bias (L 0 = 15.4H, C 0 =52.8aF, R 0 = 10kΩ, C d0 =C s0 =100fF and C par =2pF) Figure 3.7: Impedance and tuning characteristic of the 5.5MHz I 2 BAR. R 0 = 10kΩ at 10V bias. Tuning = 4600ppm from 2V-25V The SiBAR 45

60 As we scale to higher frequencies, we notice that both flexural and hybrid mode devices deteriorate in performance, in terms of quality factor and impedance. This necessitates the move towards purely extensional mode resonators. Although, this comes at the additional cost of smaller tuning range, alternative tuning architectures such as thermal tuning can be adopted for these devices, since the power overhead for tuning is no longer exorbitant. Bulk extensional mode devices typically originated with disk resonators [35, 36]. The Silicon Bulk Acoustic Resonator (SiBAR) discussed here, is a monolithic single crystal silicon extensional mode resonator that vibrates in the plane of the substrate [37] (Figure 3.8). It can be shown that the signal transduction obtained from the SiBAR is larger than that of the disk. The extensional mode resonance is a strong function of only the width of the device. Thus, an increase in transduction area is easily achieved by increasing the length of the resonator without affecting the frequency significantly. A study of the mode-shapes of the SiBAR yielded optimal dimensions and orientations for optimal coupling [38]. Figure 3.8: Mode-shape of a typical SiBAR 46

61 Figure 3.9: SEM Picture of typical SiBAR As with the IBAR, the three-mask HARPSS-on-SOI fabrication process [11] is used in this work to implement vertical capacitive SiBARs. The SEM picture of a fabricated device is shown in Fig The frequency response and the electrical parameters of the SiBAR are shown in Fig f = 103.4MHz; R m = 5kΩ Qmax= VP = 5V; 47

62 Figure 3.10: Open loop frequency response of 103MHz SiBAR 3.3 Circuits for MEMS Resonator Oscillators System Block Diagram Implementing a MEMS resonator oscillator requires two circuits in its most simple form: an amplifier that can provide sufficient gain at the frequency of resonance and a bias circuit that generates the polarization voltage for the resonator [39, 40]. Since the resonator is a voltage to current (change of charge) converter, the forward loop amplifier is a current to voltage converter. Further, the bias voltages required typically exceed normal CMOS levels necessitating the use of charge pumps for biasing these devices. In some cases, a level control circuit may also be incorporated to control power input to the resonator in order to prevent resonator saturation. Figure 3.11 shows the complete system block diagram of the implemented resonator oscillator system. The oscillation frequency is determined by a high-q micromechanical resonator. Oscillations are started up and sustained with the amplifier and inverting buffer that maintain unity loop gain and zero phase shift. The gain of the amplifier is varied with a voltage controlled MOS resistor to minimize resonator saturation due to large drive amplitudes. The resonator is biased with a voltage in the range of 25V generated from a charge pump based biasing circuit. The clock ripple on the bias voltage is minimized by using a low pass ripple filter at the output of the charge pump. 48

63 Figure 3.11: System block diagram of MEMS Resonator Oscillator CMOS Electronics Sustaining Amplifier A number of configurations can be considered suitable for the front-end amplifier. Switched-capacitor amplifiers and integrators are commonly used as front-end amplifiers for low frequency MEMS sensors [41], but switched-capacitor configurations are suited in applicability to low frequency sensors. A trans-impedance amplifier with shunt-shunt feedback is more suited for this application for the following reasons: 1. The frequency range of applicability is much higher than switched-capacitor amplifiers. 2. The use of shunt-shunt feedback minimizes Q-loading of the resonator [42]. 3. The use of a MOS resistor feedback resistor allows for simple analog level control and improves the range of impedance that can be tolerated. 49

64 Due to the aforementioned considerations, the sustaining amplifier for the oscillator is based on a CMOS trans-impedance amplifier with a self-biased folded-cascode OTA as the core. The schematic of the sustaining amplifier is shown in Fig An inverting buffer is used at the output of the amplifier to drive an off-chip load and also to maintain zero loop phase shift. Figure 3.12: Schematic diagram of sustaining amplifier Although, direct CMOS current to voltage converters may also be used [43], the transimpedance amplifier architecture discussed here provides for easier gain control, thus making it suitable for resonators with a wider range of impedances Level Control 50

65 To maintain optimal phase-noise performance, it is essential to control the drive amplitude of the resonator to minimize non-linearity in the resonator [44]. In crystal oscillators, amplitude limiting typically occurs due to the non-linearity of the transistors in the amplifier. However, quite often with micromechanical resonators, the resonator is driven into the non-linear region at smaller signal amplitudes, when the circuit is still within its linear operating region. This can occur as a result of geometric, material or transduction non-linearities in the resonator. Hence, it is essential to limit oscillation amplitude to values smaller than the distortion limit set by the amplifier. This is achieved with an automatic level control (ALC) circuit shown in Fig Level control is achieved by detecting the output signal amplitude using a peak detector, comparing the amplitude to a threshold value V REF (that depends on the type of resonator used), and generating an error voltage to control the gate of the MOS resistor M15. This varies the trans-impedance gain of the sustaining amplifier (Figure 3.12), thus limiting the oscillation amplitude within the linear limit of the resonator. M15 PEAK DETECTOR V PK SUSTAINING AMPLIFIER V REF LEVEL COMPARATOR V CTRL = A.V REF B.V PK Figure 3.13: Block Diagram of Automatic Level Control Circuit 51

66 Resonator Biasing Since the resonator bias voltage often exceeds the supply voltage, a charge pump is used for biasing the resonator. A standard Dickson pump architecture [45] is used for the charge pump since the voltage across the diodes is never greater than V DD in this scheme. Although, voltage doubler type schemes offer higher pumping efficiency [46], they require high voltage devices available only in DMOS type technologies. The circuit diagram is shown in Fig The diodes were made using the p+-n-well junction in the process. The maximum voltage that can be generated is determined by two factors: the leakage and ultimate breakdown of the n-well substrate junction and the breakdown of the poly-poly capacitor. This limits the safe operating voltages to about 15V in the process used. Figure 3.14: Charge pump used in the bias cell The clocks for the charge pump are realized on the chip using an inverter delay ring oscillator and a logic circuit to generate non-overlapping clocks. The circuit diagram for the clock generator is given in Fig

67 Figure 3.15: Clock generator for the charge pump 3.4 Conclusions Micromechanical resonator designs can be optimized for specific frequency ranges and for desirable properties such as low impedance, high-q and large tuning range. In addition to a sustaining amplifier, the resonator-oscillator also requires a bias generator (typically larger than V DD ) for operation and in most cases an amplitude limiting circuit to optimize phase noise. The following chapters discuss the two most important characteristics of the oscillator: tuning (for temperature compensation) and phase noise, in relation to resonator based oscillators and techniques for improving the same 53

68 CHAPTER 4 TUNING AND TEMPERATURE COMPENSATION OF MEMS RESONATOR OSCILLATORS 4.1 Introduction A number of techniques can be used to tune the resonant frequency. The most straightforward techniques include capacitive tuning (analog), digital control with a register and oven control (typically microprocessor-based). One mode of tuning unique to capacitive MEMS resonators is electrostatic tuning with the bias voltage. Although the additional source of tuning also implies an additional source of noise, the fact that the resonator bias voltage noise is not always the dominant source of instability in the oscillator partially decouples the problems of stability and tuning. For this reason, most of the effort in this work is focused on exploiting the electrostatic tuning technique. Oven control and capacitive tuning are also discussed as are issues pertaining to process variation and trimming techniques for manufacturability. 4.2 Electrostatic Tuning for Temperature Compensation Concept 54

69 The temperature variation of the resonant frequency follows a linear relation as expressed in (4-1), as a result of the temperature coefficient of the Young s modulus of silicon and that of thermal expansion. f f0 T α ( T T ) (4-1) 0 T The frequency tuning characteristic with V P is proportional to V P 2 and is given by (4-2) [40]. f f 0 εaf = ( V V ) P 3 k n d o P0 (4-2) where A is the area of the electrode, d 0 the electrode gap, f 0 is the natural frequency (with zero V P ), f the difference between f 0 and the operating frequency and k n is the stiffness of the resonator. Thus, a change in frequency due to temperature can be canceled out by changing the bias voltage appropriately with temperature. Clearly, the polarization voltage has a negative temperature coefficient with a parabolic temperature variation. Also, since typical polarization voltages exceed V DD, a charge pump type circuit is essential to boost the voltage to the required value. In the following sections, two architectures are demonstrated for temperature compensation: the first is a straight-forward charge pump based bias generator with a diode chain circuit that provides a linear approximation of the bias voltage variation. The 55

70 second is a more accurate, albeit complicated, second order approximation for the bias voltage. Measured results on frequency accuracy using both the techniques are presented and the sources of error are analyzed Linear Compensation Circuitry The block diagram of the temperature compensating bias circuitry is shown in Fig A large voltage is first generated by the charge pump, which is based on the Dickson charge pump architecture shown in Fig [39]. Figure 4.1: Block Diagram of the linear TC Bias Generator The diode chain circuit of Fig creates a negative temperature coefficient of 2.5mV/ºC for each diode due to the temperature variation of V BE. Stacking a set of 25 diodes, we can get a slope of 62.5mV/ºC. The resistors (R1 and R2) set the voltage range and the MOS transistor (M1) is used to trim the output voltage and the temperature coefficient for process variations. Although the generated voltage is large (24V), the voltage across each of the diodes and the transistor is much smaller. Hence, there is no 56

71 risk of break down in any of the diodes. The circuit after voltage trimming, gives a variation of 16-22V for a 100ºC change in temperature. An important consideration in the biasing of the resonator is the elimination of clock ripple on the bias voltage. The charge pump output voltage can contain significant clock ripple which can modulate the signal and add spurs to the spectrum. The ripple is minimized by using a low pass filter with a small cut-off frequency (typically 1kHz as compared to a clock frequency of 1MHz) Measured Results After open-loop characterization, the resonator and the IC were interfaced with bond wires and tested under a Desert Cryogenics vacuum probe station with temperature control. The functionality of the oscillator was verified. The temperature coefficient of the compensated oscillator was measured to be 4.2ppm/ºC, a 6X improvement over the uncompensated case. Figure 4.2 shows the temperature variation of frequency for both compensated and uncompensated cases. 57

72 Figure 4.2: Frequency variation of linearly compensated and uncompensated resonatoroscillator with temperature Parabolic Compensation Introduction The above-mentioned technique is limited in applicability to resonators within a narrow tuning range, due to the fairly constant temperature coefficient of V BE. Further, it may be observed from (4-1) and (4-2) that the frequency tuning is a parabolic function of V P and a linear function of temperature. Hence, to achieve a zero temperature coefficient oscillator, one should have: f f0 T f = f0 V (4-3) 58

73 Hence, the polarization voltage should vary with temperature as a parabolic function given by (4-4). V 2 P αtknd = εaf ( T T ) + V = A B. T ) (4-4) 0 2 P0 ( T 0 Thus, a circuit with a linear temperature coefficient is limited in providing temperature stability to the order of a few hundred parts-per-million over 100ºC. Although, this is still a significant improvement over an uncompensated oscillator (about 2600ppm over 100ºC), this number is still at least 4-5X poorer than typical AT-cut quartz System Block Diagram The block diagram of a circuit that can generate a voltage of the form of (4-4) for accurate temperature compensation is shown in Fig Figure 4.3: Block Diagram of Parabolic Temperature Compensating Bias (TCB) Generator for the IBAR 59

74 The band-gap and the PTAT reference circuit generate a constant voltage and a linear temperature slope respectively. These voltages are scaled using amplifiers to generate a voltage function of the form of (4-5). The gain coefficients A 1 and B 1 are chosen by using an appropriate resistance ratio based on the tuning and the temperature coefficients of the resonator. V X 1 1 = A B T (4-5) V X is used to generate a PTAT current I PTAT, the square-root of which is taken and used as a power supply for a clock generator. The generated clock thus swings between 0 and V CLK, where V CLK is of the form of (4-6). V CLK 1 1 = K A BT (4-6) This voltage is multiplied by a charge pump to yield a large dc voltage of the form of (4-7). The diode loss term in (4-7) has a temperature gradient which also affects the exact value and the temperature slope of the generated voltage. This can be offset by adding an offset voltage equal to the loss term at the last stage. V ( A BT ) P N 1 1 V diode. (4-7) The circuits used for each of the blocks above are described in the following section. 60

75 Circuitry Band-gap and PTAT Generator The band-gap circuit used in the implementation is shown in Fig The circuit is based on a textbook V BE - V BE architecture [32]. The PTAT circuit is generated by a similar architecture by simply changing the resistor ratio. The measured temperature behavior of the bandgap and the PTAT circuits is shown in Fig. 11. The temperature coefficient of the bandgap cell is approximately 40ppm/ºC. The temperature slope of the PTAT circuit is about 3mV/ºC. The curvature of the band-gap and the PTAT voltage is evident from Fig. 4.5; the curvature sets a limit on the accuracy of the generated clock voltage and hence the compensating bias voltage. Figure 4.4: Schematic of Band-gap and PTAT generator. BG and PTAT voltages are obtained by choosing different values for the diode sizes (ratio n ) and different resistor sizes (R4/R3). 61

76 Figure 4.5: Generated BG and PTAT voltages Square-root generation Circuit The circuit schematic of the square-root generation circuit is shown in Fig. 4.6 and is a derivative of the circuit discussed in [47]. Figure 4.6: Square-root generation circuit 62

77 The analysis of the circuit is found in [46]. Writing the current equations for M1 and M2 and simplifying we get: V OUT [ ( 1/ K ) + ( 1/ K ) ( 1 )] 2I K (4-8) REF 1 2 / 2 If the transistors are sized equal, then, K 2 =K 1 =K and the expression for V OUT can be simplified as: V ( 2 2) = (4-9) K OUT I REF Thus, the output voltage of the circuit is proportional to the square-root of the reference current. In (4-8), the body effect of M1 cannot be ignored and will affect the linearity of the circuit. However, this effect can be minimized by sizing the transistors appropriately. Now, if the reference current is generated as a function of the bandgap and PTAT voltages, then we can get an output voltage that is of the form of (4-6). Hence, the amplifier used to generate the function (A 1 -B 1.T) from the band-gap and the PTAT generators is a trans-conductance stage rather than a voltage amplifier. The square-root generator has a gain error because of the change in mobility with temperature. However, the gain of the trans-conductance stage used to generate I REF is also made proportional to g m. Thus, as long as the gain of the trans-conductance stage and the gain of the square-root generator depend on the g m of the same type of device biased appropriately, the temperature effects will cancel out to the first order. In this case 63

78 the transistors were similarly sized NMOS devices biased above threshold and in saturation. The clock generator and the charge pump used in the last two stages of the compensation circuit are the same as the ones used for the linear compensation circuit [6]. In the parabolic compensation technique, the charge pump temperature coefficient adds a linear temperature dependency to the parabolic function represented by (4-7) and needs to be accounted for. This is accomplished by adjusting the coefficients A 1 and B 1 to account for the dependency or by adding the loss term equal to N.V diode to the final stage capacitor. In this case, the former approach is chosen Measured Results To evaluate the temperature stability of the oscillator, the sample was placed in a vacuum chamber with temperature control. The results obtained from the linear temperature compensation circuit have been reported earlier for a 4MHz oscillator [39]. After characterizing the functionality of the band-gap and PTAT generators (temperature behavior shown in Fig. 4.5) and the square-root generator, the temperature coefficient of the charge pumps was characterized. A temperature sweep was performed on the uncompensated device biased at a constant V P of 15V (temperature behavior shown in Fig. 4.7). Based on these results and the tuning and characteristic of the device (shown in Fig. 3.7), appropriate values were chosen for the scaling coefficients A 1 and B 1 and the circuits were connected with bond wires. The output of the square-root generator was 64

79 used as the supply to the charge pump clock generator and the oscillator was biased with the polarization voltage generated from the bias generator. Two test runs were performed: one with linear compensation circuit and another with the parabolic compensation circuit. The temperature variation of the compensated oscillator was measured to be 332ppm and 38.7ppm over a temperature range of 25ºC to 125ºC with the linear and parabolic compensation circuits respectively. This represents an improvement of 8.5X and 72X over the linearly compensated and uncompensated oscillator respectively and even compares quite well with AT-cut quartz (variation of approximately 400ppm from 25ºC to 125ºC with 8º cut). All temperature stability plots are shown in Fig It is interesting to note that for the parabolic compensation case, the point of zero temperature coefficient (ZTC) is closer to 25 ºC than 125 ºC. This indicates that the compensation is sub-optimal (over this temperature range). This can be a result of an inaccurate choice of the coefficients in generating the V CLK or the non-linearity of the square-root generation block. The former is quite likely since the choice of the coefficients is based on the exact tuning slope and the temperature coefficient extracted from resonator characterization. The choice of coefficients also needs to account for the temperature slope of the charge pump diodes. For the 5.5MHz resonator, the temperature coefficient was about -28.3ppm/ºC and the tuning slope was estimated as -7.3ppm/V 2. A small error in either of these values would result in a wrong choice for the voltage scaling coefficients A 1 and B 1, thus leading to sub-optimal temperature compensation. 65

80 Figure 4.7: Comparison of temperature stability of the oscillator with linear and parabolic compensation circuits and with an uncompensated oscillator Error Sources The accuracy of the parabolic TC scheme is limited by the inaccuracy of the band-gap reference and the PTAT generator, mismatches in the scaling amplifiers (including feedback resistors), and the inaccuracy of the square-root generator. Simulation predicted an overall variation of about 18ppm over the temperature range of 25ºC to 125ºC with the parabolic compensation circuit. The measured variation was about 2 times larger. This is most likely because the effect of the op-amp mismatch and resistor mismatch was unaccounted in the simulation. By introducing a mismatch in the op-amps, the overall simulated variation was increased to ~25ppm, a number that is closer to the measured variation. To estimate the worst-case error analytically, one should account for each of the error sources. 66

81 Band-gap and PTAT Generator Error The temperature coefficient of the band-gap is about 40ppm/ºC, indicating that the worstcase variation is about 8mV. The worst-case error of the PTAT generator is also about 8mV. Since the band-gap and PTAT voltages are multiplied by factors of A 1 and B 1 respectively, and the difference is taken, the worst-case voltage error due to the band-gap and PTAT generator is given by (4-10). ( B A1 ) Verr BG VBG PTAT 1. (4-10) where, V err-bg is the maximum error in the band-gap voltage (=8mV) Effect of Slope Adjustment Amplifier Offset Figure 4.8 below shows the block diagram of the slope adjustment amplifier of Fig. 4.3 in greater detail. As it can be observed, the circuit comprises of three amplifiers two for scaling the coefficients of the band-gap and PTAT generator and a trans-conductance stage that generates I PTAT to drive the square-root generator. If V off is the equivalent input offset voltage of each of the above amplifiers; A 1, B 1 are the scaling factors; and G 1 is the trans-conductance gain of the succeeding stage, then the equivalent error voltage in generating the V DIFF (=I PTAT /G 1 ) is given by (4-11). DIFF ( 1+ B1 A ) V off V B. (4-11) 1 A1. V off + V off = 1 67

82 Here, the term (B 1 -A 1 ).V off arises from taking the difference of the two voltages and the last term represents the input equivalent offset of the trans-conductance amplifier. Figure 4.8: Block Diagram of the Slope Adjustment Amplifier Square-root Generator Error The error due to the square-root generator is dominated by the offset of the succeeding amplifier and the square-root generation itself does not contribute significantly to the voltage error since the gain error is cancelled out to the first order. Hence, the total error in generating the clock voltage including the offset of the amplifier following the squareroot generator is given by (4-12). ( B1 A1 ). Verr BG + Voff.( + B1 A ) Voff CLK G1 Rsq 1 1 V. + (4-12) where R sq is the gain of the square-root generator (in Ohm). In this particular case, the product G 1.R sq is chosen to be unity so that (4-12) can be simplified to (4-13) ( B A ). V + V.( + B A ) V (4-13) CLK 1 1 err BG off

83 Charge Pump Error The error voltage at the output of the charge pump is N times the error in the clock voltage, where N is the charge pump multiplication factor. Further, the effect of charge pump ripple should be added to the error voltage. Thus, the error voltage in generating V P can be approximated as (4-14): [( B1 A1 ) Verr BG + Voff.( 2 + B1 A )] Vripple P N 1 V. + (4-14) With a 5V supply and a 60dB ripple rejection because of the filter, the worst-case ripple is approximately 5mV Translation of Voltage Error to Frequency Error The error in generating the bias voltage can be translated to a frequency error by using the electrostatic tuning coefficient. We know that the frequency tuning is proportional to the square of the polarization voltage. Hence, the error in frequency due to V P is given by: elec V 2 2 [ V ( V + V ) ] f = η (4-15) P. P0 P0 P where, η vp is the tuning coefficient of the resonator and V P0 is the nominal polarization voltage. 69

84 Estimate of Worst-Case Error In the particular case of the 5.5MHz oscillator, the typical offset voltage in the amplifiers is 2.8mV. The values chosen for A 1 and B 1 are 3.5 and 4.4 respectively and a 7-stage charge pump is used. With these values, V P is computed to be about 93mV including charge pump ripple. The tuning coefficient is 7.34ppm/V 2. Using (4-15), the worst-case frequency error due to the electronics was estimated to be about 34ppm (assuming the highest required V P0 = 25V). It may be noted that this error does not include errors due to resistor mismatch, non-linearity and other errors in the square-root generator and resonator non-idealities. The purpose of the analysis is to identify the dominant error sources. It is clearly seen that the op-amp offset and the band-gap V BE curvature contribute most to the total error since the total frequency error measured is almost equal to the error arising from these two sources. Hence, in order to achieve further performance gains, the accuracy of the bandgap and the PTAT circuits should be improved by the use of curvature compensation techniques [47] and the offset in the amplifiers should be minimized using standard offset cancellation techniques [48]. Using these techniques, the temperature stability can potentially be improved to sub-10ppm, albeit at the cost of increased power consumption Voltage Scaling One advantage of the modular compensation technique discussed is that it is easily modified for voltage scaling for narrow gap devices with larger tuning coefficients. For 70

85 instance, a 10MHz IBAR with 65nm gaps provides an electrostatic tuning coefficient of approximately -250ppm/V 2 as seen in Fig Hence, a tuning voltage range of 2-4V provides a tuning range of 3000ppm, thus obviating the need for high voltages. In such a case, the charge pump (and the clock generator) at the last stage of the compensation circuit can be omitted. This simplifies the compensation scheme as shown in Fig Figure 4.9: Tuning characteristic of 10MHz, 65nm IBAR; Electrostatic Tuning coefficient = 242ppm/V 2 Figure 4.10: Low voltage TC block diagram 71

86 However, one of the problems with the low voltage implementation is that the errors due to the electronics (curve fit errors, process drift and mismatch) contribute to larger frequency drift. This places more stringent accuracy requirements on the circuit blocks of the compensation circuit. For this reason, the TC blocks were re-designed for improved accuracy. The temperature slope is now generated using purely V BE, thus eliminating V BE curvature as a source of error. The scaling of this voltage includes trimming steps to preset the voltage in order to establish the absolute frequency and exact temperature slope. This can reduce the effect of offset and temperature slope errors to a few hundred micro-volts limited only by the low-frequency noise. With 1mV temperature slope error and 2mV op-amp offsets, both quite liberal for circuits with trimming, the overall frequency error is less than 15ppm. At this stage, the effect of square-root generator non-linearity and the curve fit errors also predominate. Figure 4.11 below shows the plots of frequency error due to the PTAT and offset errors and the square-root generation errors. Figure 4.12 shows a plot of the total error due to these blocks. These numbers cannot be verified easily through measurement, since the measurement error of our system is approximately 5ppm (due to temperature controller error, frequency resolution and short-term drift of the resonator itself) and can significantly skew the data. 72

87 df/f [ppm] BG + PTAT Error Sq-rt Error Temperature [ºC] Figure 4.11: Frequency error due to PTAT and square-root generator inaccuracy 0-2 df/f [ppm] Temperature [ºC] Figure 4.12: Total frequency error with low voltage TC bias 73

88 4.2.6 Process Compensation and Trimming Another advantage of the modular TC scheme is the suitability toward trimming for high precision, high volume manufacturing. The technique naturally lends itself to both resistor trimming for the gain coefficients A and B [49, 50]and to floating gate trimming for the band-gap and the op-amp [51, 52]. An additional process control parameter is also available in the form of the resonator gap that can be modified in-line to target a predetermined tuning coefficient. The exact trimming procedure would depend on the hardware available with a manufacturer and identification of an optimal trimming algorithm that can fit both the cost structure and the target precision and is beyond the scope of this work. 4.3 Comparison of Linear and Parabolic Compensation The voltage generated (measured) from the linear and parabolic compensation circuits is shown in Fig as a function of temperature. A linear fit is also shown for the parabolic voltage case to highlight the curvature arising from the quadratic term. It may be noted the values of V P shown in Fig for the parabolic compensation circuit are slightly different from the values used while performing temperature compensation since the coefficients A 1 and B 1 were adjusted to account for the temperature coefficient of the charge pump diodes after characterization. The difference between the linear and parabolic compensation voltages is evident from Fig. 4.13, although the curvature of the parabolic voltage is quite small. In fact, a linear 74

89 approximation of the same results in less than 5% error (200mV over 25V). However, the 200mV error still degrades temperature stability to the extent of 250ppm. Figure 4.13: Polarization voltage generated by linear and parabolic compensation circuits It may be observed that the parabolic compensation circuit adds significantly to circuit complexity due to the inclusion of the band-gap and PTAT generators, the square-root generators and a number of scaling amplifiers. However, this does not result in significantly higher power consumption. This is because the band-gap and the PTAT generators and the associated amplifiers can be operated at very low current levels (less than 2µA for all the blocks). The amplifier at the last stage of the square-root generation block is used to generate the supply voltage for the clock generator and hence has to drive a large current. Hence, this block consumes about 170µA of current. But generating an internal clock supply voltage also means that the clock generator does not draw current directly from the supply. Hence, the increase in power consumption resulting from the added circuitry is less than 100µW. 75

90 4.4 Micro-Oven Control Introduction While the electrostatic tuning technique is the most attractive tuning mode for tuning the resonator center frequency, the tuning coefficient of the resonator decreases as we increase frequency. Further, the need for high quality factor devices in the high VHF to UHF range to extract the maximum advantage offered by silicon resonators over quartz, the employment of purely extensional mode resonators is necessitated, further lowering electrostatic tuning. Hence, it is essential to move away from electrostatic tuning towards other tuning techniques. Micro-oven control offers a promising alternative, especially for ultra-stable high frequency devices. This is because, at such high frequencies, the power budget for temperature compensation may not be exorbitant as compared to the power consumption of the oscillator itself. Also, the technique is inherently independent of the frequency of oscillation. In the following sections, the concept of micro-oven control for a capacitive micro-mechanical resonator is discussed along with the circuitry and the measured results from a prototype implementation Concept The idea of micro-oven control is fairly straight-forward and has its origins in crystal oscillators. With crystal oscillators, the crystal is typically mounted on a platform and the temperature of the entire platform is maintained constant with a heating current [53, 54]. However, with a silicon resonator, (especially with the highly doped single crystalline 76

91 wafers discussed here) the heating current can be applied directly to the resonator. In this implementation temperature compensation is achieved by running a heating current through the body of the resonator to maintain its operating temperature constant. The heating current can either be a direct current or alternating. The advantage of the direct current heating adopted here over the ac heating technique discussed by Hopcroft [15] is the absence of a phase noise spur arising from the heating current frequency. However, the ac current heating technique can be applied even when the device is mounted on a thermally isolated substrate, thus proving to be the lower power solution Circuitry Temperature compensation is achieved by running a direct current through the resonator by maintaining a potential difference across the body of the resonator and controlling the current (potential difference) with variations in ambient temperature to maintain the resonator at a constant operating temperature. The block diagram of the temperature compensation circuit is shown in Fig AV BE - V BE CTAT generator and a squaring circuit are used to generate a 2 nd order CTAT voltage [46, 55]. The slope of the CTAT voltage is adjusted with a scaling amplifier to match the required tuning voltage temperature slope, which is determined by a prior characterization step. The sum and difference of a reference voltage and the CTAT voltage are applied to the two bias voltage electrodes, thus controlling the current flow through the resonator to maintain the operating temperature constant. 77

92 The circuit blocks used to generate the temperature slope are the same as the ones discussed in the electrostatic temperature compensation circuit. It may be noted that since the resonator is not thermally isolated, most of the heating power may actually be dissipated in the substrate of the resonator chip and in the interconnections. A power gain stage is used at the output of the amplifiers to supply the large current. However, this may be omitted if the device is thermally isolated [56]. Figure 4.14: Block Diagram of Micro-oven control for oscillators Measured Data To test for the temperature drift, the uncompensated variation was first measured. The thermal tuning characteristic of the resonator (required tuning voltage as a function of 78

93 temperature to maintain frequency constant Fig. 4.15) is also characterized. A second order approximation of the tuning voltage is used for compensation (achieved tuning voltage Fig. 4.15) It may be noted that the DC voltage V REF was set externally and the tuning voltage was generated on-chip. The sum and difference voltages are buffered through off-chip power gain stages (to drive the small resistive load). The temperature stability of the oscillator (Fig. 4.16) was improved from 2980ppm to 56ppm over 100 C. Figure 4.15: Required and achieved tuning voltage for compensation Sources of Error The largest source of error in the scheme arises from the 2 nd order curve fit. As with the electrostatic tuning, the offsets in the amplifiers and the errors in the slope generators contribute to about 10ppm error, and the measurement accuracy due to the temperature controller and frequency measurement is estimated to be about 3-5ppm. Hence, the remainder of the error is attributed to the inaccuracy of the curve-fit. Since, a large part of the power is lost in the test board and the wires; the exact nature of the tuning voltage 79

94 curve is a strong function of the setup, the modeling of which is non-trivial. An empirical least squares curve fit resulted in a 3 rd order equation for the tuning voltage, which is curve fit with a second order voltage. Further, since the measurement setup with the compensation circuit is slightly different from the one used for the prior characterization step, this introduces an additional uncertainty in the exact tuning voltage slope. Figure 4.16: Temperature drift of SiBAR oscillator w/ and w/o compensation Data w/ compensation also shown as inset Closed loop oven control techniques that can take advantage of micro-oven control are discussed in Chapter Capacitive tuning Concept 80

95 The idea of capacitive tuning is also fairly straight-forward and traces roots to varactor based tuning of parallel resonant tanks [57, 58]. Both series and shunt tuning diodes may be used for this purpose. For series resonant tanks discussed here, the scheme is somewhat modified. The idea is to add a series (as shown in Fig. 4.17) or a load capacitor to the tank and tune the capacitor to shift oscillation frequency. The advantage of this technique is that it is applicable to both piezoelectrically and capacitively transduced resonators. Figure 4.17: Concept of capacitive tuning for resonator oscillators Limitations A number of issues arise when attempting series capacitor tuning for resonators: 1. The tuning range of the tank is a strong function of the ratio of the tuning capacitance to the series motional capacitance. Clearly, a larger motional capacitance implies larger tuning. However, this also means that the energy stored in the tuning capacitor is large and the effective Q of the tank is deteriorated significantly by the Q of the tuning capacitor. 2. The effect of the parasitic capacitance at the input and output and the feedthrough capacitance reduces the effective tuning available. Figure 4.18 shows 81

96 the tuning characteristic of with a device with 400aF motional capacitor after LC cancellation. Without cancellation, the tuning is reduced to about 300ppm. 3. The technique actually depends very strongly on the resonator type, frequency and the bias voltage. For example, the 100MHz resonator discussed earlier exhibits a motional capacitance of only 4aF. This reduces the effective capacitive tuning to only about 40ppm with the circuit above! Increasing the motional capacitance entails increasing the bias voltage by 10X (to 50V!), using a lower quality factor device or decreasing the gap by 10X, all of which are unsuitable. Piezoelectric resonators, however, exhibit much larger motional capacitances and are more suited to capacitive tuning. Figure 4.18: Tuning range of capacitively tuned MEMS resonator oscillator w/ 400aF motional capacitance 82

97 4.6 Electronics for Resonator Arrays Introduction Due to the small form factor, an array of lithographically offset resonators can be integrated on the same die to serve a number of purposes: the devices in the array can be used to extend the tuning range of the oscillator for a VCO; or the devices can be operated in a narrow temperature range to improve temperature stability over a wider range; or one of the devices can be picked from the array to account for process variation in the frequency. In all of these cases, the electronics will have to switch across an array of devices to select the correct device for the operating region. This concept can be easily extended to multi-band communication systems. In this section the electronics required for the operation of resonators in an array are discussed System Block Diagram The block diagram of the oscillator system is shown in Fig The system comprises of two inputs an external VCO control voltage and a PTAT voltage from an integrated temperature sensor. The system can thus operate in two possible modes reference oscillator mode, wherein, the purpose of the electronics is to compensate for temperature drift of the resonator; or VCO mode, wherein, the electronics pull the frequency to the required value. In either case, we switch across an array of resonators with lithographically defined frequency offset, to widen the tuning range. 83

98 In the reference oscillator mode, the resonators are designed to have high quality factors (> 10 5 ). The tuning of these resonators is typically around 1000ppm. However, the temperature drift of a silicon resonator (about -25ppm/ºC) needs to be compensated for. This is achieved electronically, by digitizing a PTAT voltage from a temperature sensor using a flash ADC [59, 60] and using this information to select one of four resonators that are offset in frequency lithographically. Once a device is selected from the array, the fine control unit uses the PTAT voltage to generate an accurate bias voltage for the resonator to maintain a constant frequency. In the VCO mode, the resonators are designed to have large tuning (in the range of 1-5% depending on PLL pulling range) while maintaining the highest possible quality factors. The VCO control input is used to choose the appropriate resonator in the array. The flash ADC enables fast switching, thus enabling faster settling times when used in a PLL. The fine control unit then adjusts the frequency to the required value as in the previous mode. Figure 4.19: Block Diagram for tuning array of resonators 84

99 4.6.3 Resonator Array Design and Offset An array of resonators with offset center frequencies is used to provide a wider tuning range. Lithographic variations in resonator dimensions can provide systematic variations in center frequency (Fig. 4.20). The required accuracy in center frequency and the offset (1000ppm) can be achieved by providing process compensation features in the design of the structure. Such features have led to resonator designs with process variation of less than 100ppm as shown in Fig Figure 4.20: Systematic frequency offset for flexural beam resonators and IBARs using lithographic variations 85

100 Center Frequency Deviation [ppm] STR1_EXTN_FEA-19 Rev3 2:09:03 AM 03-Oct Processing Bias [µm] Figure 4.21: Frequency error in IBARs with process compensation MHz IBAR MHz IBAR IC Electronics Flash ADC structure A flash type ADC is used to digitize the PTAT or the VCO control voltage. The circuit schematic is shown in Fig A 6-bit, 2-stage flash ADC is used due to its faster speed, which enables faster switching when used in a PLL. Two 3-bit flash ADCs and a resistor string DAC was used for this purpose. The bottom resistor in the chain is connected to an offset adjust voltage to account for resistor mismatch in the LSB. The comparator systematic offset is cancelled using an offset null voltage. Standard digital logic is used to convert the digitized voltage to switch between resonators in the array. Since the frequency error is only of the order of 25ppm/ºC, ½ LSB error results in about 10ppm error in frequency. 86

101 V REF 40k B 7 40k V IN B 6 V OFF-NUL B 1 40k B 0 40k V OFFSET Figure 4.22: Schematic of single stage of 2-step flash-type ADC with offset null capability Frequency Fine Control The frequency fine control circuit takes the VCO control or the PTAT voltage as an input and generates a square-root function of the input. This is necessary since the tuning characteristic of the resonator with bias voltage is parabolic and generating the squareroot linearizes the control input [5] to ensure a linear control of frequency as seen in Fig However, as a result of the switching between resonators, the tuning is piece-wise linear and a small jump in the tuning slope can be observed while switching between resonators. A charge pump voltage multiplier is used to step up the bias voltage to the range of 15-25V. 87

102 Figure 4.23: Simulated tuning characteristic of VCO tuning array The loop amplifier used to sustain oscillations is based on the trans-impedance architecture discussed earlier in Chapter Measured Results While operating in the reference oscillator mode, the frequency accuracy is determined by the accuracy of the fine control voltage, and hence, the accuracy of the temperature sensor. The output of the temperature sensor is shown in Fig The fine control voltage generated by the charge pump is plotted in Fig along with the frequency error due to the fine control circuit. The frequency error due to the fine control circuit, including the PTAT generator, the linearization circuit and the charge pump voltage multiplier is approximately 54ppm from -25ºC to 125ºC. 88

103 The measured and expected switching temperature in the reference oscillator mode is shown in Table 4.1. As it can be observed, the worst-case frequency error due to switching is about 35ppm. Hence, the total frequency error due to the electronics (switching and fine control) is about 90ppm. However, due to the effect of temperature hysteresis, the number is expected to be closer to 100ppm (Table 4.2). When operating the array in the VCO mode, the absolute accuracy can be trimmed with the control voltage and is not of significance. The resolution of the fine control circuit as a result of amplifier noise and offset and non-linearity in the square-root generator is about 10mV. This limits the frequency resolution to approximately 80ppm for VCO applications. However, the effect of switching is likely to result in jumps that can limit the frequency resolution in the VCO mode. The total time for switching between devices and oscillator start-up is smaller than 1ms even at a frequency of 10MHz. Hence, PLL lock times are unlikely to be affected adversely. The CMOS IC was fabricated in a 2P3M 0.6µm process with fabrication support provided by MOSIS. The die picture is shown in Fig The overall power consumption of the circuit is about 5mW. 89

104 Figure 4.24: Measured temperature sensor output Figure 4.25: Fine control voltage and frequency error vs. temperature 90

105 TABLE 4.1: SWITCHING TEMPERATURE AND FREQUENCY ERROR Expected T switch [ºC] Measured T Switch [ºC] Error [ºC] Frequency error [ppm] TABLE 4.2: EFFECT OF HYSTERESIS ON SWITCHING TEMPERATURE Expected T switch [ºC] Up-ramp Temp [ºC] Downramp Temp Freq Errorup-ramp [ppm] Freq Error down-ramp [ppm] Conclusions A number of tuning techniques are available for fine control of micro-mechanical resonator oscillators. Electrostatic tuning with the bias voltage is unique to devices discussed here and is most advantageous at lower frequencies since the tuning does not significantly deteriorate phase noise. While oven control might be applicable regardless of frequency, the relatively large power consumption of this technique restricts suitability to higher frequency oscillators. Closed-loop oven controlled techniques with thermally isolated platforms [56] could be ideal for oscillators that require sub-part-per-million stablility along with a few hundred parts-per-million tuning. Capacitive tuning, while being most attractive for low power applications, is suited to piezoelectric devices since the equivalent motional capacitance for the capacitively transduced resonators are significantly lower. 91

106 CHAPTER 5 PHASE NOISE IN CAPACITIVE MEMS RESONATOR OSCILLATORS 5.1 Introduction Theoretical studies on phase noise of MEMS resonator oscillators are quite recent and largely focused on fitting the classical Leeson s equation [18] to the observed phase noise characteristic [21, 61]. Recent literature has focused on modeling capacitive resonator non-linearity [44] and effect of the bias voltage [20] on the phase noise, but either model focuses on a singular aspect affecting phase noise. While the classical phase noise theory [18, 62], which focuses on a linear time invariant (LTI) approach, provides reasonable phase noise estimates for crystal type oscillators, Hajimiri s time varying model [19, 63] offers an IC designer much needed insight into the factors affecting some of the so-called empirical parameters in the classical theory. Hajimiri s theory has been demonstrated for low-q tanks such as CMOS LC tanks (and ring oscillators) where 1/f 3 and 1/f 2 noise are predominant, but very little work exists on the application of the LTV technique to high-q tanks such as quartz crystals and MEMS resonator tanks. In this chapter, the different sources of phase noise in a capacitive MEMS resonator oscillator are considered to arrive at an inclusive expression for phase noise. In addition to the time varying nature of the noise modulation, the capacitive MEMS resonator is 92

107 inherently a non-linear transducer and the effect of this non-linearity should be accounted for. Starting from the classical model and assuming a high-q oscillator, the effect of impulse sensitivity is factored in the expression in a fashion similar to [63]. The effect of the non-linear transducer is then factored in. To arrive at a final phase noise expression additional influences such as the effect of bias voltage noise and particle adsorption on the near-carrier noise are also accounted. The validity of the expression is verified for a few test cases to identify the dominant noise sources: a CMOS-MEMS oscillator with an external low noise bias and automatic level control that limits the resonator to operate in its linear regime, and a slightly non-linear resonator-oscillator with on chip biasing for the resonator. 5.2 Fundamental theory of phase noise Figure 5.1 shows the typical phase noise spectrum of an oscillator with the most common sources. For a typical low-q oscillator, the dominant regions are the 1/f 2 region and the noise floor. For a high-q oscillator, the 1/f and 1/f 3 regions are dominant along with the noise floor. The 1/f 4 region is observed very close to carrier in micromechanical resonator based oscillators. 93

108 1 f 4 1 f 3 1 f 2 1 f Figure 5.1: Typical Oscillator Phase Noise spectrum The most general representation of an oscillator is given by (5-1). v ( t) = A( t)cos( ω 0t + φ( t) ) (5-1) where A(t) describes the amplitude of oscillation including amplitude noise, ω 0 is the oscillation frequency and φ (t) represents the phase noise of the oscillator. Figure 5.2: Noise Aliasing in an oscillator 94

109 Figure 5.2 shows the typical aliasing of the amplifier noise (both thermal and 1/f) around the oscillator carrier frequency. This noise results in non-zero spectral power density around the carrier frequency. The classical phase noise theory first discussed by Leeson [18] describes the phase modulation of thermal noise by the resonator transfer function. The expression for single side-band phase noise over a 1Hz band-width around the offset frequency f m as described by Leeson is given by (5-2): 2 FkT f 0 L ( f = + m ) 1 (5-2) Ps 2QL f m where F is the effective noise figure of the amplifier, k is the Boltzmann s constant, T is the absolute temperature, Q L is the loaded quality factor of the resonator, f 0 is the oscillation frequency and P s is the output power of the oscillator. The aforementioned expression accounts for the contribution of thermal noise. If the 1/f noise in the amplifier is accounted for, the expression for noise is modified as described by (5-3): 2 FkT f 0 L( f m ) = Ps 2QL f m f f c m (5-3) where f c is defined as the 1/f 3 corner frequency. Although the term f c is quite clearly related to the 1/f corner frequency of the amplifier, and the two are often assumed to be equal, measurements indicate otherwise and f c is often determined empirically. 95

110 5.3 Hajimiri s Model Hajimiri proposed a Linear Time Variant (LTV) [63] model to account for the timevarying nature of the sensitivity of an amplitude noise impulse on the waveform. He further proceeds to define the Impulse Sensitivity Function (ISF) as a periodic function that estimates the time varying impact of the noise on the signal and computes the excess phase added. In this process, an important relationship between the 1/f 3 corner frequency f c and the amplifier 1/f-corner frequency f 1/f is described as given by (5-4) [63]: c = (5-4) 2 0 f c f 2 1/ f 4Γrms where c 0 and Γ rms are the dc and rms values of the ISF. Hence, the f c is indeed directly related to f 1/f corner frequency of the amplifier through the first Fourier coefficient of the ISF and the rms value of the ISF. He then proceeds to derive expressions for these terms for CMOS ring oscillators and LC oscillators using the concept of effective ISF, wherein the cyclo-stationary nature of drain current noise is accounted for using a periodic function α(t) that is normalized to unity. The drain current noise injected is given by (5-5). i n ( n0 0t t) = i ( t). α( ω ) (5-5) Now the cyclo-stationary noise is modeled as a stationary noise with an effective ISF given by (5-6). 96

111 Γ ( x) = Γ( x). α ( x) (5-6) eff The expressions for the Γ(x), Γ eff (x) and α(x) are derived from the device noise characteristics and operating point. 5.4 Estimation of 1/f 3 Corner Frequency Hajimiri continues with the development of the theory of impulse sensitivity and defines an expression for the ISF based on the oscillation waveshape, related to the first and second derivatives of the waveform as described by (5-7). For a high-q MEMS based oscillator, since the effective band-width of the resonator is extremely small, the waveform can be assumed to be near-sinusoidal (v(t) = Acos(ω 0 t)). In this case the ISF is given by (5-7). ( f ' sin x Γ x) = = = sin x (5-7) f ' + f " cos x + sin 2 x To find a suitable expression for α(x), let us assume that the transistor injects noise only when there is a surge of current. Although not entirely accurate, this approximation is reasonable, since the amount of noise injected when the current is zero is quite small as compared to when a surge of current occurs. The function α(x) can hence be defined as shown in (5-8). 5π 7π sin x x α ( x) = 4 4 (5-8) 0 else 97

112 In (8), the negative sign accounts for the fact that α(x) is a probabilistic function and hence is bounded by [0, 1]. Thus, the effective ISF is given by (5-9). Γ eff sin ( x) = 0 x 5π 7 x 4 4 else 2 π (5-9) To find the relationship between f c and f 1/f, we solve for the coefficients c 0 and Γ rms noting that c 0 is twice the dc value and Γ rms is the rms value of Γ eff (x). Now, c 0 and Γ rms are given by given by (5-10) and (5-11) respectively. 2π 7π / c0 = Γeff ( x) dx = sin x dx = (5-10) π π 0 2π 5π / 4 7π / Γrms = Γ ( ) = sin = eff x dx π 2π x dx (5-11) 0 5π / 4 Thus, the ratio f c /f 1/f is approximately for the case of a high-q MEMS-resonator CMOS oscillator. 5.5 Effect of amplifier Q-loading Resistive Q-loading An important factor to be considered in the phase noise expression is the estimation of loaded Q. The unloaded Q of the resonator is easily determined by a simple two-port analysis on a network analyzer. However, to accurately estimate Q loading as a result of 98

113 the amplifier and the feedback, let us consider a typical MEMS oscillator. A transimpedance amplifier is used conventionally since the output of the resonator is a current and the input to the resonator is a voltage. If the amplifier interfaced has an equivalent input impedance of R in and R out, the equivalent circuit can be drawn as shown in Fig Figure 5.3: Equivalent circuit of TZ Amplifier and resonator From Fig. 5.3, we can see that the resonator is loaded by the input and output resistance of the amplifier, both of which occur in series. Hence, the expression for loaded Q can be written as: Q L = R = Q m UL L + R R mω 0 Lmω 0 m in + R R + R m in out + R = out R m R m R + R m in + R out (5-12) 5.6 Effect of resonator non-linearity Sources of resonator non-linearity 99

114 An important consideration in the derivation of phase noise for capacitive micromechanical resonators is the non-linearity inherent in the transducer. In a capacitive resonator, an input ac voltage causes a force to act upon the mechanical device and causes a displacement of the body which results in a change in capacitance between the body and the output electrode, which in turn causes an alternating current at the output. Hence, there are three sources of non-linearity in capacitive resonators: 1. Non-linear spring force that arises due to non-linear terms in spring stiffness; 2. Non-linear effects in force-capacitance transduction; and 3. Non-linear capacitive current. To analyze the effect of each of the above, one can define a noise aliasing factor that is attached to the noise voltage at the input of the resonator resulting in an output current noise. The noise aliasing factor has three terms, one accounting for each source of nonlinearity and each is dependent on the device Q, gap size, stiffness, the resonant frequency, the electromechanical force coupling and the applied dc bias voltage. i ( Ω F sp + Ω tx + Ω ct ) = vn inω eff n out = vn, in,, (5-13) where the noise aliasing coefficients have the units of resistance. A more detailed treatment of each of the above terms can be found in [21]. For the resonators discussed in this work, it can be shown that the electromechanical term of (5-13) predominate Effect on amplifier noise Thermal Noise 100

115 To find the effect of noise aliasing on the phase noise, one can solve for the rms output noise as follows: far-from the resonance, the input noise voltage (dominated by thermal noise) is not aliased by the resonator and hence the output noise current is simply: vn, in t in, out = (5-14) R + jω L m m m The spectral noise density of thermal noise can hence be written as: f 0 v n, out t = vn, in t 1+ (5-15) 2Qf m Flicker Noise In (5-15), the effective thermal noise input voltage includes the thermal noise of the amplifier and that of the resonator. Close to resonance, the input noise voltage comprises largely of 1/f noise (of the amplifier) which is up-converted by the resonator as described by (5-13) which is then amplified by the amplifier in the feedback loop. Thus, the 1/f noise output voltage can be written as: 2 f / f f 0 v = + + Ω n, out 1/ f vn, in 1/ f eff (5-16) f m 2Qf m To account for this effect in (5-3), we can include the coefficient of f c. 2 2Ω eff in the coefficient 101

116 5.6.3 Effect of Automatic Level Control Circuit The purpose an automatic level control circuit (or amplitude limiters in crystal type oscillators is to eliminate amplitude noise. In capacitive micromechanical resonators, the purpose of the ALC circuit would be to limit resonator vibration amplitude of the resonator within its linear limit. The linear limit can be found as the minimum displacement that maintains the non-linear terms in the spring stiffness equation, the transduction equation and the capacitive current equation to a small fraction, say onetenth of the fundamental term. In such a case, the correction factor for resonator nonlinearity may be dropped from the equation for phase noise. However, note that the thermal noise of the resonator should still be included in the final equation. 5.7 Other sources Bias Voltage Noise The effect of bias voltage noise in capacitive resonators can be analyzed from the relationship between the resonant frequency and the bias voltage. f f 0 εa = e 2 2 [( V + v ) V ] P n bias 3 kd P 2. η V V P P v n bias (5-17) Where η VP is the electrostatic tuning coefficient of the resonator and v n-bias is the equivalent noise voltage of the bias generator. Hence, the output phase noise resulting from bias voltage noise is given by: v f n, out VP = 2. η V vn biasv P P f (5-18) m 102

117 Notice that the bias voltage itself may have both thermal and 1/f noise and this can result in 1/f 2 and 1/f 3 noise. Further, if charge pumping techniques are used for generating large dc bias voltages [39, 40], this can cause significant clock spurs in the phase noise if the charge pump ripple is not sufficiently filtered. Further, large gaps may be used if the electrostatic tuning coefficient needs to be minimized Random vibrations The effect of random vibration also adds to the phase noise of the resonators [22]. To account for the phase noise of vibration, we note that the change in frequency due to acceleration a is given by: f f 0 = r Γ acc r. a (5-19) where Γ acc is the acceleration sensitivity of the resonator. Hence, the phase noise caused by this mechanism can be written as: L( ω ) m acc r Γ r ω 2 2 = 2 0 cos acc a θ ωm 2 (5-20) Since the acceleration sensitivity is caused by the amount of stress induced in the resonator as a result of an accelerating force, the acceleration sensitivity can be minimized by choosing a Stress-Compensated cut (SC-cut). However, since the option is 103

118 unavailable in silicon MEMS resonators, fabrication techniques that can minimize coupling of vibration must be adopted Temperature gradients The effect of random temperature fluctuations also results in change in the frequency to the extent of about -25ppm/ C in single crystal silicon resonators. f f 0 = α T T (5-21) Also, the existence of temperature gradients adds to the phase noise. To model the effect of temperature gradients, we can model the body of the resonator as discrete elements associated with a thermal conductance with a parallel noise source and a thermal capacitance as shown in Fig Figure 5.4: Thermal equivalent circuit The phase noise arising from the temperature gradient can be written as shown in (5-22) [22]: L( ω ) m T 2 = 4 kt / g π 1+ ω τ (5-22) 2 m 2 T 104

119 where τ T is the thermal time constant of the circuit. Clearly, to minimize the phase noise due to thermal gradient, it is essential to have a large thermal conductance. Hence, it may be useful to use highly doped single crystal silicon so that resistivity (both electrical and thermal) is low Particle adsorption and desorption The effect of particle adsorption and desorption on the surface changes the effective mass of the resonator and hence causes variation in the instantaneous value of the frequency. Since, the frequency is given by: k ω 0 = (5-23) M the change in frequency due to a change in mass is given by: f f 0 M = 2M (5-24) The change in mass is dependent on the effective number of particles adsorbed (or desorbed) which in turn depends on the number of adsorption sites present in the resonator, the effective time constant for an adsorption-desorption cycle, absolute temperature and the energy barrier for desorption. If r a and r d are the effective adsorption and desorption rates, N a is the number of adsorbant sites, m is the average mass of a molecule of adsorbant, then we can derive an expression for the term M in (5-24). It has been shown earlier [8, 18] that the phase noise caused by this process can be expressed as: 105

120 L( N aσ adsτ ads m ω0 ω ) = m ads (5-25) + ωmτ ads M ωm where σ ads is the occupational probability of a site and τ ads is the time constant of the adsorption-desorption cycle. It can be observed that the phase noise characteristic has a 1/f 4 slope. For micromechanical resonators, the smaller volume will imply that a larger 1/f 4 noise contribution as compared to crystal type oscillators. Hence, in order to reduce the deterioration of phase noise caused by this mechanism, we can minimize the number of molecules adsorbed (by operating in vacuum), maximize the desoprtion rate (by increasing temperature) or decrease the adsorption probability by having a smooth resonator surface. 5.8 Summary of Phase Noise Sources To arrive at a complete expression for the phase noise of a capacitive micromechanical resonator oscillator, the effect of various phase noise sources can be grouped based on the phase noise slope for each term as shown in (5-26) and each region (1/f 4 through 1/f 0 ) has a coefficient attached to it. The phase noise slope coefficients b 0 through b 4 can be arrived at by combining the terms from Table 5.1.This form can be easily curve fit to real phase noise data to verify the contribution of each of the sources. Table 5.1 presents a summary of different phase noise sources and the corresponding expressions along with comments on applicability. ( b b b b ) = (5-26) f L f m b f m f m f m 4 4 m 106

121 TABLE 5.1: SUMMARY OF PHASE NOISE SOURCES IN CAPACITIVE SILICON MICROMECHANICAL RESONATOR OSCILLATORS Source Phase Noise Expression Slope Comments Amplifier + Resonator Thermal Noise Amplifier 1/f Noise Capacitive Nonlinearity Bias Voltage Noise 2 FkT f 0 1/f 0 Need to include both 1 + Ps 2QL f m + 1/f 2 resonator and amplifier noise FkT f Ps 2QL f m 2 f f c m Thermal Noise Negligible effect 1/f Noise - 2 f c f Ω eff f m 2Qf 2. η v VP n bias V P f f 0 m 2 m 2 1/f + 1/f 3 f c f1/ f 1/f 0 + 1/f 2 1/f + 1/f 3 ALC - Particle Adsorption N aσ adsτ ads m ω + ωmτ ads M ωm 2 Temperature 4 kt / g 2 2 Gradients π 1+ ω τ Vibration Q-loading r Γ Q acc 2 r a 2 cos 2 m T 0 ω θ ω m R 2 Thermal Noise is not affected significantly by non-linearity. 1/f noise is scaled by the aliasing factor 1/f 2 Can cause spurs as + 1/f 3 well if charge pumps are used 1/f 4 = m L QUL Rm + Rin + R - out Neglect effect of capacitive nonlinearity on noise Much more significant in micromechanical resonators as compared to quartz 1/f 2-1/f 2 - Affects noise everywhere except noise floor 107

122 5.9 Design Optimization The optimization of the design of the resonator can be carried out to minimize the dominant sources of noise in Table 5.1. The minimization of thermal and 1/f noise and the trade-offs involved are well-known and addressed. Bulk-mode resonators with low motional resistance are preferred and the amplifier noise figure is minimized. Resonator non-linearity is minimized using an ALC circuit. Particle adsorption can be minimized by operating in vacuum, elevating the operating temperature and by having a clean smooth resonator surface. Bias voltage noise can be minimized by using large gaps. However, this reduces the electrostatic signal coupling and the effective signal power. Hence, there exists a fundamental trade-off between minimizing bias voltage induced noise and signal power. The design of the resonator (motional impedance and electrostatic tuning) has to be optimized by a careful choice of resonator-electrode gap to minimize the total noise. The effect of temperature gradients can be minimized by increasing thermal conductance of the silicon (by increasing dopant concentration). The resistivity of the SOI wafers used here range between 0.001Ω-cm and 0.01 Ω-cm. Vibration noise can be minimized by fabricating the resonator along with a force-cancelling accelerometer or by fabricating the device on a vibration isolated platform. The effect of Q-loading is minimized by an optimal choice of input and output impedances of the interfacing amplifier. Further improvements are readily achieved by using fully differential configuration for the oscillator. This provides well-known advantages of minimal power supply and common mode rejection and minimizes bias voltage induced noise as well (since that can be modeled as a common-mode signal). In fact, it has been verified with simulation that a 108

123 simple fully differential trans-impedance amplifier shows an improvement of over 10dB over traditional single-ended schemes. The phase noise plots for the single-ended and differential schemes for a 1GHz oscillator is shown in Fig Figure 5.5: Simulated phase noise of 1GHz differential and single-ended oscillators 5.10 Data and Analysis To verify the phase noise theory, the phase noise of a 6MHz IBAR oscillator and a 100MHz SiBAR oscillator were measured. All the experiments above were carried out in a thermally stable environment (at room temperature) under vacuum levels of ~1uTorr unless mentioned otherwise. Under these conditions, the effect of thermal gradients and particle adsorption is minimized. It is further assumed that the effect of acceleration is minimal for these oscillators, a claim that can be validated by the data obtained. Also, the 109