CAT24C32BC4, CAT24C32BAC4. EEPROM Serial 32-Kb I 2 C in a 4-ball WLCSP

Transcription

1 2432B4, 2432B4 EEROM erial 32-b I 2 in a 4-ball WL Description he 2432B4 and 2432B4 are EEROM erial 32 b I 2 devices available in a 4 ball WL package. Both devices are internally organized as 4096 words of 8 bits each. hey feature a 32 byte page write buffer and support the tandard (100 khz), Fast (400 khz) and Fast lus (1 MHz) I 2 protocol. he 2432B4 and 2432B4 respond to a different lave ddress and are therefore suitable in applications that require two serial EEROM devices with 4 ball WL on the same I 2 bus. Features upports tandard, Fast and Fast lus I 2 rotocol 1.7 V to 5.5 V upply Voltage Range 32 Byte age Write Buffer Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low ower MO echnology 1,000,000 rogram/erase ycles 100 Year Data Retention Industrial emperature Range 4 ball WL ackage his Device is b Free, Halogen Free/BFR Free, and RoH ompliant V IN ONFIGURION (op View) V 1 L WL 4 4 UFFIX E 567JY 1 WL (4) MRING DIGRM 2 V B1 B2 D X YM X = pecific Device ode = B: 2432B4 = J: 2432B4 Y = roduction Year (Last Digit) M = roduction Month (1 9, O, N, D) For the location of in 1, please consult the corresponding package drawing. IN FUNION L 2432B4 2432B4 D in Name D L V V Function erial Data erial lock ower upply Ground ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. V Figure 1. Functional ymbol emiconductor omponents Industries, LL, 2016 May, 2018 Rev. 3 1 ublication Order Number: 2432B4/D

2 2432B4, 2432B4 able 1. BOLUE MXIMUM RING arameters Ratings Units torage emperature 65 to +150 Voltage on ny in with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. RELIBILIY HRERII (Note 2) ymbol arameter Min Units N END (Note 3) Endurance 1,000,000 rogram/erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. age Mode, V = 5 V, 25. able 3. D.. OERING HRERII (V = 1.7 V to 5.5 V, = 40 to +85, unless otherwise specified.) ymbol arameter est onditions Min Max Units I R Read urrent Read, f L = 1 MHz 0.4 m I W Write urrent Write 0.6 m I B tandby urrent ll I/O ins at GND or V 1 I L I/O in Leakage in at GND or V 2 V IL Input Low Voltage V 2.2 V 0.5 V x 0.3 V V < 2.2 V 0.5 V x 0.25 V V IH Input High Voltage V 2.2 V V x 0.7 V V V < 2.2 V V x 0.75 V V V OL Output Low Voltage V 2.2 V, I OL = 3.0 m 0.4 V V < 2.2 V, I OL = 1.0 m 0.2 V able 4. IN IMEDNE HRERII (V = 1.7 V to 5.5 V, = 40 to +85, unless otherwise specified.) ymbol arameter onditions Max Units IN (Note 4) D I/O in apacitance V IN = 0 V 8 pf IN (Note 4) Input apacitance (other pins) V IN = 0 V 6 pf 4. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 2

3 2432B4, 2432B4 able 5... HRERII (V = 1.7 V to 5.5 V, = 40 to +85 ) (Note 5) ymbol arameter tandard Fast Fast lus Min Max Min Max Min Max F L lock Frequency ,000 khz t HD: R ondition Hold ime s t LOW Low eriod of L lock s t HIGH High eriod of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime s t U:D Data In etup ime ns t R (Note 6) D and L Rise ime 1, ns t F (Note 6) D and L Fall ime ns t U:O O ondition etup ime s t BUF Bus Free ime Between O and R Units s t L Low to Data Out Valid s t DH (Note 6) Data Out Hold ime ns i (Note 6) Noise ulse Filtered at L and D Inputs ns t WR Write ycle ime ms t U (Notes 6, 7) ower up to Ready Mode ms roduct parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. roduct performance may not be indicated by the Electrical haracteristics if operated under different conditions. 5. est conditions according to.. est onditions table. 6. ested initially and after a design or process change that affects this parameter. 7. t U is the delay between the time V is stable and the device is ready to accept commands. able 6... E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load V 2.2 V: 0.2 x V to 0.8 x V V < 2.2 V: 0.15 x V to 0.85 x V 50 ns 0.3 x V, 0.7 x V 0.3 x V, 0.7 x V urrent ource: I OL = 3 m (V 2.2 V); I OL = 1 m (V < 2.2 V); L = 100 pf 3

4 2432B4, 2432B4 ower On Reset (OR) Each 2432B4/2432B4 incorporates ower On Reset (OR) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the OR trigger level and will power down into Reset mode when V drops below the OR trigger level. his bi directional OR behavior protects the device against brown out failure following a temporary loss of power. in Description L: he erial lock input pin accepts the clock signal generated by the Master. D: he erial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. Functional Description he 2432B4/2432B4 supports the Inter Integrated ircuit (I 2 ) Bus protocol. he protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and lave devices which execute requests. he 2432B4/2432B4 operates as a lave device. Both Master and lave can transmit or receive, but only the Master can assign those roles. I 2 Bus rotocol he 2 wire I 2 bus consists of two lines, L and D, connected to the V supply via pull up resistors. he Master provides the clock to the L line, and either the Master or the laves drive the D line. 0 is transmitted by pulling a line LOW and a 1 by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, D must remain stable while L is HIGH. R/O ondition n D transition while L is HIGH creates a R or O condition (Figure 2). he R consists of a HIGH to LOW D transition, while L is HIGH. bsent the R, a lave will not respond to the Master. he O completes all commands, and consists of a LOW to HIGH D transition, while L is HIGH. Device ddressing he Master addresses a lave by creating a R condition and then broadcasting an 8 bit lave address (Figure 3). he first 4 bits of the lave address are set to he next 3 bits are set to ( 2432B4) or to (2432B4). he last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. cknowledge During the 9 th clock cycle following every byte sent to the bus, the transmitter releases the D line, allowing the receiver to respond. he receiver then either acknowledges () by pulling D LOW, or does not acknowledge (No) by letting D stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. L D R ONDIION Figure 2. tart/top iming O ONDIION R/W 2432B R/W 2432B4 Figure 3. lave ddress Bits 4

5 2432B4, 2432B4 BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R tlow tlow L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming WRIE OERION Byte Write o write data to memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 0. he Master then sends two address bytes and a data byte and concludes the session by creating a O condition on the bus. he lave responds with after every byte sent by the Master (Figure 6). he O starts the internal Write cycle, and while this operation is in progress (t WR ), the D output is tri stated and the lave does not acknowledge the Master (Figure 7). age Write he Byte Write operation can be expanded to age Write, by sending more than one data byte to the lave before issuing the O condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal age Write Buffer starting at the address provided by the Master. he page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the O, data loaded during the age Write session will be written to memory in a single internal Write cycle (t WR ). cknowledge olling s soon (and as long) as internal Write is in progress, the lave will not acknowledge the Master. his feature enables the Master to immediately follow up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a No response from the lave, the Master simply repeats the request until the lave responds with. Delivery tate he 2432B4/2432B4 is shipped erased, i.e., all bytes are FFh. 5

6 2432B4, 2432B4 BU IVIY: MER R LVE LVE DDRE *a 15 a 12 are don t care bits. DDRE DDRE * * * * D a 15 a 8 a 7 a 0 d 7 d 0 Figure 6. Byte Write equence O L D 8th Bit Byte n t WR O ONDIION R ONDIION DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE DDRE DDRE D n D n+1 D n+ O LVE Figure 8. age Write equence 6

7 2432B4, 2432B4 RED OERION Immediate Read o read data from memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 1. he lave responds with and starts shifting out data residing at the current address. fter receiving the data, the Master responds with No and terminates the session by creating a O condition on the bus (Figure 9). he lave then returns to tandby mode. elective Read o read data residing at a specific address, the selected address must first be loaded into the internal address register. his is done by starting a Byte Write sequence, whereby the Master creates a R condition, then broadcasts a lave address with the R/W bit set to 0 and then sends two address bytes to the lave. Rather than completing the Byte Write sequence by sending data, the Master then creates a R condition and broadcasts a lave address with the R/W bit set to 1. he lave responds with after every byte sent by the Master and then sends out data residing at the selected address. fter receiving the data, the Master responds with No and then terminates the session by creating a O condition on the bus (Figure 10). equential Read If, after receiving data sent by the lave, the Master responds with, then the lave will continue transmitting until the Master responds with No followed by O (Figure 11). During equential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. BU IVIY: MER R LVE DDRE N O O LVE D L 8 9 D 8th Bit D OU NO Figure 9. Immediate Read equence and iming O BU IVIY: MER R LVE DDRE DDRE DDRE R LVE DDRE N O O LVE D Figure 10. elective Read equence BU IVIY: MER LVE DDRE N O O LVE D n D n+1 D n+2 D n+x Figure 11. equential Read equence 7

8 2432B4, 2432B4 ORDERING INFORMION Device Order Number 2432B4R B WL 4 with Die oat 2432B4R (Note 9) J WL 4 with Die oat pecific Device Marking ackage ype emperature Range Lead Finish hipping I = Industrial ( 40 to +85 ) I = Industrial ( 40 to +85 ) ng ng ape & Reel, 5,000 Units / Reel ape & Reel, 5,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. 8. ll packages are RoH compliant (Lead free, Halogen free). 9. his WL 4 option responds to a different lave ddress compared to 2432B4R. 10.aution: he EEROM devices delivered in WL must never be exposed to ultra violet light. When exposed to ultra violet light the EEROM cells lose their stored data. ON emiconductor is licensed by the hilips orporation to carry the I 2 bus protocol. 8

9 MEHNIL E OULINE GE DIMENION LE 4:1 WL4, 0.77x0.77 E 567JY IUE DE 07 MR 2017 NOE 5 IN 1 REFERENE NOE 4 4X 0.05 b 0.05 B 0.03 DEIL B E O VIEW IDE VIEW 1 2 e BOOM VIEW 2 e B D REOMMENDED OLDERING FOORIN* 1 GE OULINE NOE 3 EING LNE NOE 6 DIE O (OIONL) DEIL 3 2 NOE: 1. DIMENIONING ND OLERNING ER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DUM, HE EING LNE, I DEFINED BY HE HERIL ROWN OF HE OLDER BLL. 4. OLNRIY LIE O HERIL ROWN OF HE OLDER BLL. 5. DIMENION b I MEURED HE MXIMUM ON BLL DIMEER RLLEL O DUM. 6. BIDE OING I OIONL. MILLIMEER DIM MIN NOM MX REF REF b D E e 0.40 B GENERI MRING DIGRM* X Y W X YW = pecific Device ode = Year = Work Week *his information is generic. lease refer to device data sheet for actual part marking. b Free indicator, G or microdot, may or may not be present IH 4X IH DIMENION: MILLIMEER *For additional information on our b Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. DOUMEN NUMBER: U: NEW NDRD: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIION: 98ON85186F ON EMIONDUOR NDRD WL4, 0.77X Electronic versions are uncontrolled except when accessed directly from the Document Repository. rinted versions are uncontrolled except when stamped ONROLLED OY in red. ase Outline Number: GE 1 OF XXX 2

10 DOUMEN NUMBER: 98ON85186F GE 2 OF 2 IUE REVIION DE O RELEED FOR RODUION. REQ. BY I. MRINO. 06 MY 2014 ORREED DEIL ND DIMENION 1, DDED NOMINL VLUE. REQ. BY V. RIUNOIU. 23 JUN 2016 B MODIFIED DIMENION D ND E O 0.77X0.77. REQ. BY V. RIUNOIU. 02 UG 2016 MODIFIED DIMENION 1 ND 2 VLUE. REQ. BY V. RIUNOIU. 07 MR 2017 ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2017 March, 2017 Rev. ase Outline Number: 567JY

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