CAT24AA01, CAT24AA02. EEPROM Serial 1/2-Kb I 2 C

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1 2401, 2402 EEROM erial 1/2-b I 2 Description he 2401/2402 are EEROM erial 1/2 b I 2 devices internally organized as 128x8/256x8 bits. hey feature a 16 byte page write buffer and support the tandard (100 khz), Fast (400 khz) and Fast lus (1 MHz) I 2 protocols. In contrast to the 2401/2402, the 2401/2402 have no external address pins, and are therefore suitable in applications that require a single 2401/02 on the I 2 bus. Features upports tandard, Fast and Fast lus I 2 rotocol 1.7 V to 5.5 V upply Voltage Range 16 Byte age Write Buffer Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low ower MO echnology 1,000,000 rogram/erase ycles 100 Year Data Retention Industrial emperature Range hese Devices are b Free, Halogen Free/BFR Free and are RoH ompliant V D O 23 D UFFIX E 419E IN ONFIGURION L 1 V O (op View) MRING DIGRM W V L D RYM W V Figure 1. Functional ymbol R = Device ode Y = roduction Year (Last Digit) M = roduction Month (1 9, O, N, D) IN FUNION in Name Function D erial Data/ddress L lock Input W Write rotect V ower upply V Ground ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. emiconductor omponents Industries, LL, 2015 pril, 2018 Rev. 6 1 ublication Order Number: 2401/D

2 2401, 2402 able 1. BOLUE MXIMUM RING arameters Ratings Units torage emperature 65 to +150 Voltage on any in with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. REBILIY HRERII (Note 2) ymbol arameter Min Units N END (Note 3) Endurance 1,000,000 rogram/erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. age 25 able 3. D.. OERING HRERII (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) ymbol arameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz 0.5 m I W Write urrent Write 1 m I B tandby urrent ll I/O ins at GND or V 1 I L I/O in Leakage in at GND or V 1 V IL Input Low Voltage 0.5 V x 0.3 V V IH Input High Voltage V x 0.7 V V V OL1 Output Low Voltage V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltage V < 2.5 V, I OL = 1.0 m 0.2 V roduct parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. roduct performance may not be indicated by the Electrical haracteristics if operated under different conditions. able 4. IN IMEDNE HRERII (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) ymbol arameter onditions Max Units IN (Note 2) D I/O in apacitance V IN = 0 V 8 pf IN (Note 2) Input apacitance (other pins) V IN = 0 V 6 pf I W (Note 4) W Input urrent V IN < V IH 100 V IN > V IH 1 4. When not driven, the W pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 2

3 2401, 2402 able 5... HRERII (Note 5) (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) tandard V = 1.7 V 5.5 V Fast V = 1.7 V 5.5 V 1 MHz V = 2.5 V 5.5 V ymbol arameter Min Max Min Max Min Max Units F L lock Frequency khz t HD: R ondition Hold ime s t LOW Low eriod of L lock s t HIGH High eriod of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime ns t U:D Data In etup ime ns t R (Note 6) t F (Note 6) D and L Rise ime ns D and L Fall ime ns t U:O O ondition etup ime s t BUF Bus Free ime Between O and R s t L Low to Data Out Valid s t DH Data Out Hold ime ns i (Note 6) Noise ulse Filtered at L and D Inputs ns t U:W W etup ime s t HD:W W Hold ime s t WR Write ycle ime ms t U (Notes 6, 7) ower up to Ready Mode ms 5. est conditions according to.. est onditions table. 6. ested initially and after a design or process change that affects this parameter. 7. t U is the delay between the time V is stable and the device is ready to accept commands. able 6... E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 3

4 2401, 2402 ower On Reset (OR) Each 2401/02 incorporates ower On Reset (OR) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the OR trigger level and will power down into Reset mode when V drops below the OR trigger level. his bi directional OR behavior protects the device against brown out failure, following a temporary loss of power. in Description L: he erial lock input pin accepts the clock signal generated by the Master. D: he erial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of L. W: When the Write rotect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LOW internally. Functional Description he 2401/02 supports the Inter Integrated ircuit (I 2 ) Bus protocol. he protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and lave devices which execute requests. he 2401/02 operates as a lave device. Both Master and lave can transmit or receive, but only the Master can assign those roles. I 2 BU ROOOL he 2 wire I 2 bus consists of two lines, L and D, connected to the V supply via pull up resistors. he Master provides the clock to the L line, and the Master and laves drive the D line. 0 is transmitted by pulling a line LOW and a 1 by releasing it HIGH. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, D must remain stable while L is HIGH. R/O ondition n D transition while L is HIGH creates a R or O condition (Figure 2). R is generated by a HIGH to LOW transition, while a O is generated by a LOW to HIGH transition. he R acts like a wake up call. bsent a R, no lave will respond to the Master. he O completes all commands. Device ddressing he Master addresses a lave by creating a R condition and then broadcasting an 8 bit lave address (Figure 3). he four most significant bits of the lave address are 1010 (h). For the 2401/02 the next three bits must be 000. he last bit, R/W, instructs the lave to either provide (1) or accept (0) data, i.e. it signals a Read (1) or a Write (0) request. cknowledge During the 9 th clock cycle following every byte sent onto the bus, the transmitter releases the D line, allowing the receiver to respond. he receiver then either acknowledges () by pulling D LOW, or does not acknowledge (No) by letting D stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. L D R ONDIION Figure 2. tart/top iming O ONDIION R/W Figure 3. lave ddress Bits 4

5 2401, 2402 BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R t LOW t LOW L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming WRIE OERION Byte Write o write data to memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 0. he Master then sends an address byte and a data byte and concludes the session by creating a O condition on the bus. he lave responds with after every byte sent by the Master (Figure 5). he O starts the internal Write cycle, and while this operation is in progress (t WR ), the D output is tri stated and the lave does not acknowledge the Master (Figure 6). age Write he Byte Write operation can be expanded to age Write, by sending more than one data byte to the lave before issuing the O condition (Figure 7). Up to 16 distinct data bytes can be loaded into the internal age Write Buffer starting at the address provided by the Master. he page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the O, data loaded during the age Write session will be written to memory in a single internal Write cycle (t WR ). cknowledge olling s soon (and as long) as internal Write is in progress, the lave will not acknowledge the Master. his feature enables the Master to immediately follow up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a No response from the lave, the Master simply repeats the request until the lave responds with. Hardware Write rotection With the W pin held HIGH, the entire memory is protected against Write operations. If the W pin is left floating or is grounded, it has no impact on the Write operation. he state of the W pin is strobed on the last falling edge of L immediately preceding the 1 st data byte (Figure 8). If the W pin is HIGH during the strobe interval, the lave will not acknowledge the data byte and the Write request will be rejected. Delivery tate he 2401/02 is shipped erased, i.e., all bytes are FFh. 5

6 2401, 2402 BU IVIY: MER R LVE DDRE DDRE D a 7 a 0 d 7 d 0 O LVE Figure 6. Byte Write equence L D 8th Bit Byte n t WR O ONDIION Figure 7. Write ycle iming R ONDIION DDRE BU IVIY: MER R LVE DDRE DDRE D n D n+1 D n+x O LVE n = 1 x 15 Figure 8. age Write equence DDRE D L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figure 9. W iming 6

7 2401, 2402 RED OERION Immediate Read o read data from memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 1. he lave responds with and starts shifting out data residing at the current address. fter receiving the data, the Master responds with No and terminates the session by creating a O condition on the bus (Figure 10). he lave then returns to tandby mode. elective Read o read data residing at a specific address, the selected address must first be loaded into the internal address register. his is done by starting a Byte Write sequence, whereby the Master creates a R condition, then broadcasts a lave address with the R/W bit set to 0 and then sends an address byte to the lave. Rather than completing the Byte Write sequence by sending data, the Master then creates a R condition and broadcasts a lave address with the R/W bit set to 1. he lave responds with after every byte sent by the Master and then sends out data residing at the selected address. fter receiving the data, the Master responds with No and then terminates the session by creating a O condition on the bus (Figure 11). equential Read If, after receiving data sent by the lave, the Master responds with, then the lave will continue transmitting until the Master responds with No followed by O (Figure 12). During equential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. For the 2401, the internal address counter will not wrap around at the end of the 128 byte memory space. BU IVIY: N O MER R LVE DDRE O LVE D L 8 9 D 8th Bit D OU NO O Figure 10. Immediate Read equence and iming BU IVIY: N O MER R LVE DDRE DDRE R LVE DDRE O LVE D BU IVIY: MER LVE DDRE Figure 11. elective Read equence O N O LVE D n D n+1 DE BY n+2 D n+x Figure 12. equential Read equence 7

8 2401, 2402 Ordering Information Device Order Number pecific Device Marking ackage ype emperature Range 2401DI G3 R O 23 5 I = Industrial ( 40 to +85 ) Lead Finish hipping Nidu ape & Reel, 3,000 Units / Reel 2402DI G3 R O 23 5 I = Industrial ( 40 to +85 ) Nidu ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. 8. ll packages are RoH compliant (Lead free, Halogen free). 9. he standard lead finish is Nidu. 10. For additional package and temperature options, please contact your nearest ON emiconductor sales office. ON emiconductor is licensed by the hilips orporation to carry the I 2 bus protocol. 8

9 MEHNIL E OULINE GE DIMENION O 23, 5 LED E 419E 01 IUE O DE 19 DE 2008 e D YMBOL 1 MIN NOM MX b c E1 E D E 2.90 B 2.80 B E B e 0.95 Y L L REF O VIEW L2 θ 0.25 B 0º 8º 2 b 1 L1 L c L2 IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-193. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIION: 98ON34392E ON EMIONDUOR NDRD O 23, 5 LED 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. rinted versions are uncontrolled except when stamped ONROLLED OY in red. ase Outline Number: GE 1 OF XXX 2

10 DOUMEN NUMBER: 98ON34392E GE 2 OF 2 IUE REVIION DE O RELEED FOR RODUION FROM OD #O O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 419E

11 ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at /site/pdf/atent Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor E. 32nd kwy, urora, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative

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