CAT24C128. EEPROM Serial 128-Kb I 2 C
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1 24128 EEPROM erial 128-b I 2 Description he is a EEPROM erial 128 b I 2 internally organized as 16,384 words of 8 bits each. It features a 64 byte page write buffer and supports both the tandard (100 khz), Fast (400 khz) and Fast Plus (1 MHz) I 2 protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). On hip E (Error orrection ode) makes the device suitable for high reliability applications.* Features upports tandard, Fast and Fast Plus I 2 Protocol 1.8 V to 5.5 V upply Voltage Range 64 Byte Page Write Buffer Hardware Write Protection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low Power MO echnology 1,000,000 Program/Erase ycles 100 Year Data Retention Industrial and Extended emperature Range his Device is Pb Free, Halogen Free/BFR Free and RoH ompliant** L 2, 1, 0 WP V V Figure 1. Functional ymbol D ** For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. OI 8 W UFFIX E 751BD PIN ONFIGURION V V WP L D OI (W), OP (Y), UDFN (HU4) Pin Name 0, 1, 2 D L WP V UDFN 8 HU4 UFFIX E 517Z PIN FUNION OP 8 Y UFFIX E 948L Device ddress Inputs erial Data Input/Output erial lock Input Write Protect Input Power upply OI 8 WIDE X UFFIX E 751BE For the location of Pin 1, please consult the corresponding package drawing. Function V Ground he exposed pad for the DFN/UDFN packages can be left floating or connected to Ground. ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. emiconductor omponents Industries, LL, 2013 May, 2018 Rev Publication Order Number: 24128/D
2 24128 able 1. BOLUE MXIMUM RING Parameter Rating Units torage emperature 65 to +150 Voltage on ny Pin with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. RELIBILIY HRERII (Note 2) ymbol Parameter Min Units N END (Notes 3, 4) Endurance 1,000,000 Program / Erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. Page Mode, V = 5 V, he new product revision () uses E (Error orrection ode) logic with 6 E bits to correct one bit error in 4 data bytes. herefore, when a single byte has to be written, 4 bytes (including the E bits) are re programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. able 3. D.. OPERING HRERII Mature Product (Rev B) (V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz 1 m I W Write urrent Write, f L = 400 khz 3 m I B tandby urrent ll I/O Pins at GND or V = 40 to = 40 to I L I/O Pin Leakage Pin at GND or V = 40 to = 40 to V IL Input Low Voltage 0.5 V x 0.3 V V IH Input High Voltage V x 0.7 V V V OL1 Output Low Voltage V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltage V < 2.5 V, I OL = 1.0 m 0.2 V able 4. PIN IMPEDNE HRERII Mature Product (Rev B) (V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter onditions Max Units IN (Note 5) D I/O Pin apacitance V IN = 0 V 8 pf IN (Note 5) Input apacitance (other pins) V IN = 0 V 6 pf I WP (Note 6) WP Input urrent V IN < V IH 200 V IN > V IH 1 5. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 2
3 24128 able 5. D.. OPERING HRERII New Product (Rev ) (Note 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz/1 MHz 1 m I W Write urrent 3 m I B tandby urrent ll I/O Pins at GND or V = 40 to = 40 to I L I/O Pin Leakage Pin at GND or V = 40 to = 40 to V IL1 Input Low Voltage 2.5 V V 5.5 V V V V IL2 Input Low Voltage 1.8 V V < 2.5 V V V V IH1 Input High Voltage 2.5 V V 5.5 V 0.7 V V V V IH2 Input High Voltage 1.8 V V < 2.5 V 0.75 V V V V OL1 Output Low Voltage V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltage V < 2.5 V, I OL = 1.0 m 0.2 V able 6. PIN IMPEDNE HRERII New Product (Rev ) (Note 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter onditions Max Units IN (Note 8) D I/O Pin apacitance V IN = 0 V 8 pf IN (Note 8) Input apacitance (other pins) V IN = 0 V 6 pf I WP, I (Note 9) WP Input urrent, ddress Input V IN < V IH, V = 5.5 V 75 urrent ( 0, 1, 2 ) V IN < V IH, V = 3.3 V 50 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 7. he product Rev is identified by letter or dedicated marking code on top of the package. 8. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 9. When not driven, the WP, 0, 1, 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 3
4 24128 able 7... HRERII (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125 ) (Note 10) ymbol Parameter tandard V = 1.8 V 5.5 V Fast V = 1.8 V 5.5 V Fast Plus (Note 13) V = 2.5 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frequency ,000 khz t HD: R ondition Hold ime s t LOW Low Period of L lock s t HIGH High Period of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime s t U:D Data In etup ime ns t R (Note 11) D and L Rise ime 1, ns t F (Note 11) D and L Fall ime ns t U:O OP ondition etup ime s t BUF Bus Free ime Between OP and R Units s t L Low to Data Out Valid s t DH Data Out Hold ime ns i (Note 11) Noise Pulse Filtered at L and D Inputs ns t U:WP WP etup ime s t HD:WP WP Hold ime s t WR Write ycle ime ms t PU (Notes 11, 12) Power-up to Ready Mode ms 10. est conditions according to.. est onditions table. 11. ested initially and after a design or process change that affects this parameter. 12.t PU is the delay between the time V is stable and the device is ready to accept commands. 13.Fast Plus (1 MHz) speed class available for new product revision. he die revision is identified by letter or a dedicated marking code on top of the package. able 8... E ONDIION Input Levels 0.2 x V to 0.8 x V Input Rise and Fall imes 50 ns Input Reference Levels 0.3 x V, 0.7 x V Output Reference Levels 0.5 x V Output Load urrent ource: I OL = 3 m (V 2.5 V); I OL = 1 m (V < 2.5 V); L = 100 pf 4
5 24128 Power On Reset (POR) he incorporates Power On Reset (POR) circuitry which protects the device against powering up in the wrong state. he will power up into tandby mode after V exceeds the POR trigger level and will power down into Reset mode when V drops below the POR trigger level. his bi directional POR feature protects the device against brown out failure following a temporary loss of power. Pin Description L: he erial lock input pin accepts the erial lock generated by the Master. D: he erial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2 : he ddress pins accept the device address. When not driven, these pins are pulled LOW internally. WP: he Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Functional Description he supports the Inter Integrated ircuit (I 2 ) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all R and OP conditions. he acts as a lave device. Master and lave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs 0, 1, and 2. I 2 Bus Protocol he I 2 bus consists of two wires, L and D. he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the 2 wire bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a R or OP condition (Figure 2). he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake up call to all receivers. bsent a R, a lave will not respond to commands. he OP condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address are set to 1010, for normal Read/Write operations (Figure 3). he next 3 bits, 2, 1 and 0, select one of 8 possible lave devices and must match the state of the external address pins. he last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. cknowledge fter processing the lave address, the lave responds with an acknowledge () by pulling down the D line during the 9 th clock cycle (Figure 4). he lave will also acknowledge all address bytes and every data byte presented in Write mode. In Read mode the lave shifts out a data byte, and then releases the D line during the 9 th clock cycle. s long as the Master acknowledges the data, the lave will continue transmitting. he Master terminates the session by not acknowledging the last data byte (No) and by issuing a OP condition. Bus timing is illustrated in Figure
6 24128 L D R ONDIION Figure 2. R/OP onditions OP ONDIION DEVIE DDRE R/W Figure 3. lave ddress Bits BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EUP ( t U:D ) t F t HIGH t R tlow tlow L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming 6
7 24128 Write Operations Byte Write Upon receiving a lave address with the R/W bit set to 0, the will interpret the next two bytes as address bytes. hese bytes are used to initialize the internal address counter; the 2 most significant bits are don t care, the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. byte following the address bytes will be interpreted as data. he data will be loaded into the Page Write Buffer and will eventually be written to memory at the address specified by the 14 active address bits provided earlier. he will acknowledge the lave address, address bytes and data byte. he Master then starts the internal Write cycle by issuing a OP condition (Figure 6). During the internal Write cycle (t WR ), the D output will be tri stated and additional Read or Write requests will be ignored (Figure 7). Page Write By continuing to load data into the Page Write Buffer after the 1 st data byte and before issuing the OP condition, up to 64 bytes can be written simultaneously during one internal Write cycle (Figure 8). If more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is latched and the address count automatically increments to and then wraps around at the page boundary. Previously loaded data can thus be overwritten by new data. What is eventually written to memory reflects the latest Page Write Buffer contents. Only data loaded within the most recent Page Write sequence will be written to memory. cknowledge Polling he ready/busy status of the can be ascertained by sending Read or Write requests immediately following the OP condition that initiated the internal Write cycle. s long as internal Write is in progress, the will not acknowledge the lave address. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the he state of the WP pin is strobed on the last falling edge of L immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the will not acknowledge the data byte and the Write request will be rejected. Delivery tate he is shipped erased, i.e., all bytes are FFh. BU IVIY: MER R LVE DDRE DDRE DDRE a 13 a 8 a 7 a 0 D O P * * P LVE * = Don t are Bit Figure 6. Byte Write equence L D 8th Bit Byte n t WR OP ONDIION Figure 7. Write ycle iming R ONDIION DDRE 7
8 24128 BU IVIY: MER R LVE DDRE DDRE DDRE a 13 a 8 a 7 a 0 D n D n+1 D n+p O P * * P LVE * = Don t are Bit P 63 Figure 8. Page Write equence DDRE D L D a 7 a 0 d 7 d 0 t U:WP WP t HD:WP Figure 9. WP iming Read Operations Immediate Read Upon receiving a lave address with the R/W bit set to 1, the will interpret this as a request for data residing at the current byte address in memory. he will acknowledge the lave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (No) and then follows up with a OP condition (Figure 10), the returns to tandby mode. elective Read o read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the two address bytes with data, the Master instead follows up with an Immediate Read sequence, then the will use the 14 active address bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (No) and then follows up with a OP condition (Figure 11), the returns to tandby mode. equential Read If during a Read session the Master acknowledges the 1 st data byte, then the will continue transmitting data residing at subsequent locations until the Master responds with a No, followed by a OP (Figure 12). In contrast to Page Write, during equential Read the address count will automatically increment to and then wrap around at end of memory (rather than end of page). 8
9 24128 BU IVIY: MER R LVE DDRE N O O P P LVE D L 8 9 D 8th Bit D OU NO OP Figure 10. Immediate Read equence and iming BU IVIY: MER R LVE DDRE DDRE DDRE a 13 a 8 a 7 a 0 R LVE DDRE N O OP * * P LVE * = Don t are Bit D Figure 11. elective Read equence BU IVIY: MER LVE DDRE N O O P P LVE D n D n+1 D n+2 D n+x Figure 12. equential Read equence 9
10 24128 ORDERING INFORMION (Notes 14 thru 17) Device Order Number pecific Device Marking* 24128WI G OI 8, JEDE Package ype emperature Range Lead Finish hipping I = Industrial ( 40 to +85 ) NiPdu ape & Reel, 3,000 Units / Reel 24128YI G3 28 OP 8 I = Industrial ( 40 to +85 ) 24128XI 2 BD OI 8 I = Industrial ( 40 to +85 ) NiPdu Matte in ape & Reel, 3,000 Units / Reel ape & Reel, 2,000 Units / Reel 24128HU4IG3 7U UDFN 8 I = Industrial ( 40 to +85 ) NiPdu ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8011/D. 14. ll packages are RoH compliant (Lead free, Halogen free). 15. he standard lead finish is NiPdu. 16. For additional package and temperature options, please contact your nearest ON emiconductor ales office. 17. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON emiconductor Device Nomenclature document, ND310/D, available at ON emiconductor is licensed by the Philips orporation to carry the I 2 bus protocol. 10
11 MEHNIL E OULINE PGE DIMENION 1 LE 2:1 UDFN8, 2x3 EXENDED PD E 517Z IUE DE 23 MR 2015 PIN ONE REFERENE NOE D ÇÇ ÇÇ OP VIEW DEIL B 1 IDE VIEW B E 3 L1 EXPOED u EING PLNE L DEIL LERNE ONRUION ÉÉ MOLD MPD DEIL B LERNE ONRUION L ÉÉÉ 1 3 NOE: 1. DIMENIONING ND OLERNING PER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DIMENION b PPLIE O PLED ERMINL ND I MEURED BEWEEN 0.15 ND 0.25MM FROM HE ERMINL IP. 4. OPLNRIY PPLIE O HE EXPOED PD WELL HE ERMINL. MILLIMEER DIM MIN MX REF b D 2.00 B D E 3.00 B E e 0.50 B L L GENERI MRING DIGRM* DEIL D2 1 4 L 1 XXXXX WLYW 8 5 e BOOM VIEW E2 8X b 0.10 M 0.05 M B NOE 3 XXXXX = pecific Device ode = ssembly Location WL = Wafer Lot Y = Year W = Work Week = Pb Free Package *his information is generic. Please refer to device data sheet for actual part marking. Pb Free indicator, G or microdot, may or may not be present. REOMMENDED OLDERING FOOPRIN* X PIH 8X 0.30 DIMENION: MILLIMEER *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. DOUMEN NUMBER: 98ON42552E U: ON EMIONDUOR NDRD REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: UDFN8, 2X3 EXENDED PD 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2
12 DOUMEN NUMBER: 98ON42552E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #UDFN O ON EMION- 23 JUL 2009 DUOR. REQ. BY B. BERGMN. REDREW PGE DRWING O ON EMIONDUOR/JEDE NDRD. REQ. BY B. BEER. 23 MR 2015 ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2015 March, 2015 Rev. ase Outline Number: 517Z
13 MEHNIL E OULINE PGE DIMENION OI 8, 150 mils E 751BD 01 IUE O DE 19 DE 2008 YMBOL MIN NOM MX b E1 E c D E E e 1.27 B h PIN # 1 IDENIFIION L θ 0º 8º OP VIEW D h 1 θ c e b L IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M-012. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34272E ON EMIONDUOR NDRD OI 8, 150 MIL 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2
14 DOUMEN NUMBER: 98ON34272E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OI O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 751BD
15 MEHNIL E OULINE PGE DIMENION OP8, 4.4x3 E 948L 01 IUE O DE 19 DE 2008 b YMBOL MIN NOM MX b E1 E c D E E e 0.65 B L 1.00 REF L1 θ º 8º e OP VIEW D 2 1 c IDE VIEW 1 L1 END VIEW L Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-153. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34428E ON EMIONDUOR NDRD OP8, 4.4X3 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2
16 DOUMEN NUMBER: 98ON34428E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OP O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 948L
17 MEHNIL E OULINE PGE DIMENION OI 8, 208 mils E 751BE 01 IUE O DE 19 DE 2008 E1 E YMBOL MIN NOM MX 1 b c D E E e 1.27 B L θ 0º 8º PIN#1 IDENIFIION OP VIEW D e b 1 L c IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with EIJ EDR DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34273E ON EMIONDUOR NDRD OI 8, 208 MIL 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2
18 DOUMEN NUMBER: 98ON34273E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OI O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 751BE
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CAT24C256. EEPROM Serial 256-Kb I 2 C
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