CAT1024, CAT1025. Supervisory Circuits with I 2 C Serial 2k-bit CMOS EEPROM and Manual Reset

Transcription

1 1024, 1025 upervisory ircuits with I 2 erial 2k-bit MO EEROM and Manual Reset Description he 1024 and 1025 are complete memory and supervisory solutions for microcontroller based systems. 2k bit serial EEROM memory and a system power supervisor with brown out protection are integrated together in low power MO technology. Memory interface is via a 400 khz I 2 bus. he 1025 provides a precision V sense circuit and two open drain outputs: one (REE) drives high and the other (REE) drives low whenever V falls below the reset threshold voltage. he 1025 also has a Write rotect input (W). Write operations are disabled if W is connected to a logic high. he 1024 also provides a precision V sense circuit, but has only a REE output and does not have a Write rotect input. ll supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or hangs the system. For the 1024 and 1022, the watchdog timer monitors the D signal. he 1023 has a separate watchdog timer interrupt input pin, WDI. he power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, I or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other Is is simple. In addition, the REE pin or a separate input, MR, can be used as an input for push button manual reset capability. he 1024/25 memory features a 16 byte page. In addition, hardware data protection is provided by a V sense circuit that prevents writes to memory whenever V falls below the reset threshold or until V reaches the reset threshold during power up. vailable packages include an 8 pin DI and a surface mount 8 pin O, 8 pin O, 8 pin DFN and 8 pin MO packages. he DFN package thickness is 0.8 mm maximum. DFN footprint is 3 x 3 mm. DI 8 E 646 MO 8 E 846D O 8 E 948 OI 8 E 751BD DFN 8 E 511L ORDERING INFORMION For Ordering Information details, see page 13. Features recision ower upply Voltage Monitor 5 V, 3.3 V and 3 V ystems Five hreshold Voltage Options ctive High or Low Reset Valid Reset Guaranteed at V = 1 V 400 khz I 2 Bus 2.7 V to 5.5 V Operation Low ower MO echnology 16 Byte age Write Buffer Built in Inadvertent Write rotection W in (1025) 1,000,000 rogram/erase ycles Manual Reset Input 100 Year Data Retention Industrial and Extended emperature Ranges Green ackages vailable with Nidu Lead Finished hese Devices are b Free, Halogen Free/BFR Free and are RoH ompliant emiconductor omponents Industries, LL, 2011 November, 2011 Rev ublication Order Number: 1024/D

2 1024, 1025 able 1. HREHOLD VOLGE OION art Dash Number Minimum hreshold Maximum hreshold EXERNL LOD BLO DIGRM V V D OU WORDDDRE BUFFER ENEM HIF REGIER OLUMN DEODER D W* R/O LOGI ONROL LOGI XDE 2kbit EEROM D IN ORGE HIGHVOLGE/ IMING ONROL REE ontroller E OUNER L MR recision Vcc Monitor LVE DDRE OMROR REE* REE *1025 Only 2

3 1024, 1025 IN ONFIGURION DI ackage (L) OI ackage (W) O ackage (Y) MO ackage (Z) (Bottom View) DFN ackage: 3 mm x 3 mm 0.8mm maximum height (ZD4) MR REE N V V N L D V N L D MR REE N V MR REE REE V V W L D V WDI L D MR REE REE V IN DERIION REE/REE: REE OUUs (REE 1025 Only) hese are open drain pins and REE can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. he REE pin must be connected through a pull down resistor, and the REE pin must be connected through a pull up resistor. D: ERIL D DDRE he bidirectional serial data/address pin is used to transfer all data into and out of the device. he D pin is an open drain output and can be wire ORed with other open drain or open collector outputs. L: ERIL LO erial clock input. MR: MNUL REE INU Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. ulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. he input has an internal pull up resistor. W (1025 Only): WRIE ROE INU When W input is tied to V or left unconnected write operations to the entire array are allowed. When tied to V, the entire array is protected. his input has an internal pull down resistor. able 2. IN FUNION in Name N REE V D L REE V W MR No onnect Function ctive Low Reset Input/Output Ground erial Data/ddress lock Input ctive High Reset Output (1025 Only) ower upply Write rotect (1025 Only) Manual Reset Input able 3. OERING EMERURE RNGE Industrial 40 to 85 Extended 40 to 125 3

4 1024, 1025 able X FMILY OVERVIEW Device Manual Reset Input in Watchdog Watchdog Monitor in Write rotection in Independent uxiliary Voltage ense REE: ctive High and LOW 1021 D 2k 1022 D 2k 1023 WDI 2k k k k 1027 WDI 2k NOE: For supervisory circuits with embedded 16k EEROM, please refer to the 1161, 1162 and 1163 data sheets. EEROM EIFIION able 5. BOLUE MXIMUM RING arameters Ratings Units emperature Under Bias 55 to +125 torage emperature 65 to +150 Voltage on any in with Respect to Ground (Note 1) 2.0 to V V V with Respect to Ground 2.0 to 7.0 V ackage ower Dissipation apability ( = 25 ) 1.0 W Lead oldering emperature (10 s) 300 Output hort ircuit urrent (Note 2) 100 m tresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. 1. he minimum D input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum D voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. able 6. D.. OERING HRERII V = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. ymbol arameter est onditions Min yp Max Units I LI Input Leakage urrent V IN = GND to V 2 10 I LO Output Leakage urrent V IN = GND to V I 1 ower upply urrent (Write) f L = 400 khz V = 5.5 V I 2 ower upply urrent (Read) f L = 400 khz V = 5.5 V 3 m 1 m I B tandby urrent V = 5.5 V V IN = GND or V 40 V IL (Note 3) Input Low Voltage x V V V IH (Note 3) Input High Voltage 0.7 x V V V V OL Output Low Voltage (D, REE) I OL = 3 m V = 2.7 V 0.4 V V OH Output High Voltage (REE) I OH = 0.4 m V = 2.7 V V 0.75 V 4

5 1024, 1025 able 6. D.. OERING HRERII V = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. ymbol arameter est onditions V H Reset hreshold 102x 45 (V = 5.0 V) 102x 42 (V = 5.0 V) 102x 30 (V = 3.3 V) 102x 28 (V = 3.3 V) 102x 25 (V = 3.0 V) Min yp Max Units V V RVLID Reset Output Valid V Voltage 1.00 V V R (Note 4) Reset hreshold Hysteresis 15 mv 3. V IL min and V IH max are reference values only and are not tested. 4. his parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. able 7. INE = 25, f = 1.0 MHz, V = 5 V ymbol est est onditions Max Units OU (Note 5) Output apacitance V OU = 0 V 8 pf IN (Note 5) Input apacitance V IN = 0 V 6 pf able 8. HRERII V = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write ycle (Note 6) ymbol arameter Min Max Units f L lock Frequency 400 khz t Input Filter pike uppression (D, L) 100 ns t LOW lock Low eriod 1.3 s t HIGH lock High eriod 0.6 s t R (Note 5) D and L Rise ime 300 ns t F (Note 5) D and L Fall ime 300 ns t HD; tart ondition Hold ime 0.6 s t U; tart ondition etup ime (for a Repeated tart) 0.6 s t HD; D Data Input Hold ime 0 ns t U; D Data Input etup ime 100 ns t U; O top ondition etup ime 0.6 s t L Low to Data Out Valid 900 ns t DH Data Out Hold ime 50 ns t BUF (Note 5) ime the Bus must be Free Before a New ransmission an tart 1.3 s t W (Note 7) Write ycle ime (Byte or age) 5 ms 5. his parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. est onditions according to est onditions table. 7. he write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, D is allowed to remain high and the device does not respond to its slave address. 5

6 1024, 1025 able 9. REE IRUI HRERII ymbol arameter est onditions Min yp Max Units t UR ower Up Reset imeout Note ms t RD V H to REE output Delay Note 3 5 s t GLIH V Glitch Reject ulse Width Notes 4 and 5 30 ns MR Glitch Manual Reset Glitch Immunity Note ns t MRW MR ulse Width Note 1 5 s t MRD MR Input to REE Output Delay Note 1 1 s able 10. OWER U IMING (Notes 5 and 6) ymbol arameter est onditions Min yp Max Units t UR ower Up to Read Operation 270 ms t UW ower Up to Write Operation 270 ms able 11. E ONDIION arameter Input ulse Voltages Input Rise and Fall imes Input Reference Voltages Output Reference Voltages Output Load est onditions 0.2 x V to 0.8 x V 10 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource: I OL = 3 m; L = 100 pf able 12. RELIBILIY HRERII ymbol arameter Reference est Method Min Max Units N END (Note 5) Endurance MIL D 883, est Method ,000,000 ycles/byte DR (Note 5) Data Retention MIL D 883, est Method Years V Z (Note 5) ED usceptibility MIL D 883, est Method Volts I LH (Notes 5 & 7) Latch Up JEDE tandard m 1. est onditions according to est onditions table. 2. ower up, Input Reference Voltage V = V H, Reset Output Reference Voltage and Load according to est onditions able 3. ower Down, Input Reference Voltage V = V H, Reset Output Reference Voltage and Load according to est onditions able 4. V Glitch Reference Voltage = V Hmin ; Based on characterization data 5. his parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. t UR and t UW are the delays required from the time V is stable until the specified memory operation can be initiated. 7. Latch up protection is provided for stresses up to 100 m on input and output pins from 1 V to V + 1 V. 6

7 1024, 1025 DEVIE OERON Reset ontroller Description he 1024/25 precision REE controllers ensure correct system operation during brownout and power up/down conditions. hey are configured with open drain REE outputs. During power up, the REE outputs remain active until V reaches the VH threshold and will continue driving the outputs for approximately 200 ms (tur) after reaching VH. fter the tur timeout interval, the device will cease to drive the reset outputs. t this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power down, the REE outputs will be active when V falls below VH. he REE output will be valid so long as V is > 1.0 V (VRVLID). he device is designed to ignore the fast negative going V transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Operation he REE pin can operate as reset output and manual reset input. he input is edge triggered; that is, the REE input will initiate a reset timeout after detecting a high to low transition. When REE I/O is driven to the active state, the 200 ms timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. he 1024/25 also have a separate manual reset input. Driving the MR input low by connecting a pushbutton (normally open) from MR pin to GND will generate a reset condition. he input has an internal pull up resistor. Reset remains asserted while MR is low and for the Reset imeout period after MR input has gone high. Glitches shorter than 100 ns on MR input will not generate a reset pulse. No external debouncing circuits are required. Manual reset operation using MR input is shown in Figure 2. Hardware Data rotection he 1024/25 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. n internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before V reaches the minimum value of 2 V. In addition, the 1025 includes a Write rotection Input which when tied to V will disable any write operations to the device. 7

8 1024, 1025 t GLIH V H V RV LI D V t UR t RD tur t RD REE REE Figure 1. REE Output iming t MRW MR t MRD t UR REE REE Figure 2. MR Operation and iming 8

9 1024, 1025 EMBEDDED EEROM OERON he 1024 and 1025 feature a 2 kbit embedded serial EEROM that supports the I 2 Bus data transmission protocol. his Inter Integrated ircuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. he transfer is controlled by the Master device which generates the serial clock and all R and O conditions for bus access. Both the Master device and lave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I 2 Bus rotocol he features of the I 2 bus protocol are defined as follows: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. ny changes in the data line while the clock line is high will be interpreted as a R or O condition. tart ondition he R ondition precedes all commands to the device, and is defined as a HIGH to LOW transition of D when L is HIGH. he 1024/25 monitors the D and L lines and will not respond until this condition is met. top ondition LOW to HIGH transition of D when L is HIGH determines the O condition. ll operations must end with a O condition. DEVIE DDREING he Master begins a transmission by sending a R condition. he Master sends the address of the particular slave device it is requesting. he four most significant bits of the 8 bit slave address are programmable in metal and the default is he last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. fter the Master sends a R condition and the slave address byte, the 1024/25 monitors the bus and responds with an acknowledge (on the D line) when its address matches the transmitted slave address. he 1024/25 then perform a Read or Write operation depending on the R/W bit. t F t HIGH t R t LOW tlow L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 3. Bus iming L D 8H BI BYE n t WR O ONDIION Figure 4. Write ycle iming R ONDIION DDRE 9

10 1024, 1025 NOWLEDGE fter a successful data transfer, each receiving device is required to generate an acknowledge. he acknowledging device pulls down the D line during the ninth clock cycle, signaling that it received the 8 bits of data. he 1024/25 responds with an acknowledge after receiving a R condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 bit byte. When the 1024/25 begins a RED mode it transmits 8 bits of data, releases the D line and monitors the line for an acknowledge. Once it receives this acknowledge, the 1024/25 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a O condition. WRIE OERION Byte Write In the Byte Write mode, the Master device sends the R condition and the slave address information (with the R/W bit set to zero) to the lave device. fter the lave generates an acknowledge, the Master sends a 8 bit address that is to be written into the address pointers of the device. fter receiving another acknowledge from the lave, the Master device transmits the data to be written into the addressed memory location. he 1024/25 acknowledges once more and the Master generates the O condition. t this time, the device begins an internal programming cycle to non volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. D L R BI Figure 5. tart/top iming O BI L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R NOWLEDGE Figure 6. cknowledge iming Default onfiguration R/W Figure 7. lave ddress Bits 10

11 1024, 1025 age Write he 1024/25 writes up to 16 bytes of data in a single write cycle, using the age Write operation. he page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. fter each byte has been transmitted, the 1024/25 will respond with an acknowledge and internally increment the lower order address bits by one. he high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the O condition, the address counter wraps around, and previously transmitted data will be overwritten. When all 16 bytes are received, and the O condition has been sent by the Master, the internal programming cycle begins. t this point, all received data is written to the 1024/25 in a single write cycle. BU IVIY: MER LVE DDRE BYE DDRE D O D LINE R Figure 8. Byte Write iming BU IVIY: MER R LVE DDRE BYE DDRE (n) D n D n + 1 D n+15 O D LINE Figure 9. age Write iming cknowledge olling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host s write operation, the 1024/25 initiates the internal write cycle. polling can be initiated immediately. his involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no will be returned. If a write operation has completed, an will be returned and the host can then proceed with the next read or write operation. WRIE ROEION IN (W) he Write rotection feature (1025 only) allows the user to protect against inadvertent memory array programming. If the W pin is tied to V, the entire memory array is protected and becomes read only. he 1025 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device s failure to send an acknowledge after the first byte of data is received. RED OERION he RED operation for the 1024/25 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. hree different RED operations are possible: Immediate/urrent ddress RED, elective/random RED and equential RED. 11

12 1024, 1025 BU IVI Y: MER R L VE DDRE O D LINE D N O L 8 9 D 8H BI D OU NO O Figure 10. Immediate ddress Read iming Immediate/urrent ddress Read he 1024 and 1025 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last RED or WRIE access was to address N, the RED immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. fter the 1024/1025 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. he master device does not send an acknowledge, but will generate a O condition. elective/random Read elective/random RED operations allow the Master device to select at random any memory location for a RED operation. he Master device first performs a dummy write operation by sending the R condition, slave address and byte addresses of the location it wishes to read. fter the 1024 and 1025 acknowledges, the Master device sends the R condition and the slave address again, this time with the R/W bit set to one. he 1024 and 1025 then responds with its acknowledge and sends the 8 bit byte requested. he master device does not send an acknowledge but will generate a O condition. equential Read he equential RED operation can be initiated by either the Immediate ddress RED or elective RED operations. fter the 1024 and 1025 sends the initial 8 bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. he 1024 and 1025 will continue to output an 8 bit byte for each acknowledge, thus sending the O condition. he data being transmitted from the 1024 and 1025 is sent sequentially with the data from address N followed by data from address N + 1. he RED operation address counter increments all of the 1024 and 1025 address bits so that the entire memory array can be read during one operation. BU IVIY: MER R LVE DDRE BYE DDRE (n) R LVE DDRE O D LINE Figure 11. elective Read iming D n N O 12

13 1024, 1025 BU IVIY: MER LVE DDRE D n D n+1 D n+2 D n+x O D LINE N O Figure 12. equential Read iming ORDERING INFORMION Orderable art Numbers 1024 eries (ee Notes 1 5) Device Reset hreshold ackage hipping 1024LI 45 G 1024LI 42 G 1024LI 30 G 1024LI 28 G 1024LI 25 G 1024WI 45 G3 1024WI 42 G3 1024WI 30 G3 1024WI 28 G3 1024WI 25 G3 1024YI 45 G3 1024YI 42 G3 1024YI 30 G3 1024YI 28 G3 1024YI 25 G3 1024ZI 45 G3 1024ZI 42 G3 1024ZI 30 G3 1024ZI 28 G3 1024ZI 25 G3 1024ZD4I 453* 1024ZD4I 423* 1024ZD4I 303* 1024ZD4I 283* 1024ZD4I 253* DI OI O MO DFN 3000 ape & Reel 1. ll packages are RoH compliant (Lead free, Halogen free). 2. he standard lead finish is Nidu. 3. For additional package and temperature options, please contact your nearest ON emiconductor ales office. 4. DFN not available in Nidu ( G) version. 5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON emiconductor Device Nomenclature document, ND310/D, available at 13

14 1024, 1025 Orderable art Numbers 1025 eries (ee Notes 1 5) Device Reset hreshold ackage hipping 1025LI 45 G 1025LI 42 G 1025LI 30 G 1025LI 28 G 1025LI 25 G 1025WI 45 G3 1025WI 42 G3 1025WI 30 G3 1025WI 28 G3 1025WI 25 G3 1025YI 45 G3 1025YI 42 G3 1025YI 30 G3 1025YI 28 G3 1025YI 25 G3 1025ZI 45 G3 1025ZI 42 G3 1025ZI 30 G3 1025ZI 28 G3 1025ZI 25 G3 1025ZD4I 453* 1025ZD4I 423* 1025ZD4I 303* 1025ZD4I 283* 1025ZD4I 253* DI OI O MO DFN 3000 ape & Reel 1. ll packages are RoH compliant (Lead free, Halogen free). 2. he standard lead finish is Nidu. 3. For additional package and temperature options, please contact your nearest ON emiconductor ales office. 4. DFN not available in Nidu ( G) version. 5. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON emiconductor Device Nomenclature document, ND310/D, available at 14

15 1024, 1025 GE DIMENION OI 8, 150 mils E 751BD 01 IUE O YMBOL MIN NOM MX b E1 E c D E E e 1.27 B h IN # 1 IDENIFIION L θ 0º 8º O VIEW D h 1 θ c e b L IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M

16 1024, 1025 DI 8, 300 mils E IUE YMBOL MIN NOM MX IN # 1 IDENIFIION D E b b2 c D E E1 e eb B L O VIEW E 2 1 L b2 c e b eb IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. (2) omplies with JEDE M

17 1024, 1025 MO 8, 3x3 E 846D 01 IUE O YMBOL MIN NOM MX b c E E1 D E E e 0.65 B L L REF L2 θ 0.25 B 0º 6º O VIEW D 2 DEIL 1 e b c IDE VIEW END VIEW L2 Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-187. DEIL L1 L 17

18 1024, 1025 DFN8, 3x3 E 511L 01 IUE D e b L E E2 IN#1 ID IN#1 INDEX RE 1 D2 O VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX REF b D D E E FRON VIEW e 0.65 Y L Notes: (1) ll dimensions are in millimeters. (2) omplies with JEDE MO

19 1024, 1025 O 8 E IUE 0.20 (0.008) 0.20 (0.008) L U U (0.003) EING LNE IN 1 IDEN D 2X L/ x V REF (0.004) M U V G B U J N ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ DEIL E N J1 1 EION N N 0.25 (0.010) M W NOE: 1. DIMENIONING ND OLERNING ER NI Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DIMENION DOE NO INLUDE MOLD FLH. RORUION OR GE BURR. MOLD FLH OR GE BURR HLL NO EXEED 0.15 (0.006) ER IDE. 4. DIMENION B DOE NO INLUDE INERLED FLH OR RORUION. INERLED FLH OR RORUION HLL NO EXEED 0.25 (0.010) ER IDE. 5. ERMINL NUMBER RE HOWN FOR REFERENE ONLY. 6. DIMENION ND B RE O BE DEERMINED DUM LNE -W-. MILLIMEER INHE DIM MIN MX MIN MX B D F G 0.65 B B J J L 6.40 B B M F DEIL E ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor.o. Box 5163, Denver, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter hone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative 1024/D