NV24M01WF. EEPROM Serial 1-Mb I 2 C - Automotive Grade 1 in Wettable Flank UDFN8 Package

Transcription

1 EERM erial 1-Mb I 2 - utomotive Grade 1 in Wettable Flank UDFN8 ackage Description he NV24M01WF is a EERM erial 1 Mb I 2 utomotive Grade 1, internally organized as 131,072 words of 8 bits each. It features a 256 byte page write buffer and supports the tandard (100 khz), Fast (400 khz) and Fast lus (1 MHz) I 2 protocol. Write operations can be inhibited by taking the W pin High (this protects the entire memory). External address pins make it possible to address up to four NV24M01WF devices on the same bus. n hip E (Error orrection ode) makes the device suitable for high reliability applications. Features utomotive emperature Grade 1 ( 40 to +125 ) 1.8 V to 5.5 V upply Voltage Range 256 Byte age Write Buffer Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low ower M echnology 1,000,000 rogram/erase ycles 100 Year Data Retention Industrial and Extended emperature Range 8 pad UDFN Wettable Flank ackage hese Devices are b Free, Halogen Free/BFR Free and are RoH ompliant V 1, 2 D L W V V W WL Y W in Name UDFN 8 (Wettable Flank) MUW3 UFFIX E 517DH MRING DIGRM 1 1 W WLYW = pecific Device ode = ssembly Location = Wafer Lot = Year = Work Week = b Free ackage IN FUNIN Device ddress erial Data erial lock Write rotect ower upply Ground Function L 2, 1 NV24M01WF D RDERING INFRMIN ee detailed ordering and shipping information on page 123 of this data sheet. W V Figure 1. Functional ymbol emiconductor omponents Industries, LL, 2017 May, 2018 Rev. 1 1 ublication rder Number: NV24M01WF/D

2 able 1. BLUE MXIMUM RING arameters Ratings Units torage emperature 65 to +150 Voltage on any in with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. RELIBILIY HRERII (Note 2) ymbol arameter Min Units N END (Notes 3, 4) Endurance 1,000,000 rogram/erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. est ondition: age Mode, V = 5 V, he device uses E (Error orrection ode) logic with 6 E bits to correct one bit error in 4 data bytes. herefore, when a single byte has to be written, 4 bytes (including the E bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. able 3. D ERING HRERII V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified. ymbol arameter est onditions Min Max Units I R Read urrent Read, f L = 1 MHz 1 m I W Write urrent 8.0 m I B tandby urrent ll I/ ins at GND or V = 40 to = 40 to I L I/ in Leakage in at GND or V = 40 to = 40 to V IL1 Input Low Voltage 2.5 V V 5.5 V V V V IL2 Input Low Voltage 1.8 V V < 2.5 V V V V IH1 Input High Voltage 2.5 V V 5.5 V 0.7 V V V V IH2 Input High Voltage 1.8 V V < 2.5 V 0.8 V V V V L1 utput Low Voltage V 2.5 V, I L = 3.0 m 0.4 V V L2 utput Low Voltage V < 2.5 V, I L = 1.0 m 0.2 V 2

3 able 4. IN IMEDNE HRERII V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified. ymbol arameter onditions Max Units IN (Note 5) D I/ in apacitance V IN = 0 V 8 pf IN (Note 5) Input apacitance (other pins) V IN = 0 V 6 pf I W, I (Note 6) W Input urrent, ddress Input urrent ( 1, 2 ) V IN < V IH, V = 5.5 V 75 V IN < V IH, V = 3.3 V 50 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 5. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 6. When not driven, the W, 1, 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the M input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. able 5. HRERII (Note 7) V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified. Fast V = 1.8 V 5.5 V Fast lus V = 2.5 V 5.5 V ymbol arameter Min Max Min Max F L lock Frequency 400 1,000 khz t HD: R ondition Hold ime s t LW Low eriod of L lock s t HIGH High eriod of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime 0 0 s t U:D Data In etup ime ns t R (Note 8) D and L Rise ime ns t F (Note 8) D and L Fall ime ns t U: ondition etup ime s t BUF Bus Free ime Between and R s t L Low to Data ut Valid s t DH Data ut Hold ime ns i (Note 8) Noise ulse Filtered at L and D Inputs ns t U:W W etup ime 0 0 s t HD:W W Hold ime s t WR Write ycle ime 5 5 ms t U (Notes 8, 9) ower-up to Ready Mode ms 7. est conditions according to.. est onditions table. 8. ested initially and after a design or process change that affects this parameter. 9. t U is the delay between the time V is stable and the device is ready to accept commands. able 6. E NDIIN Input Levels 0.2 x V to 0.8 x V (V < 2.5 V) and 0.3 x Vcc to 0.7 x Vcc (V 2.5 V) Input Rise and Fall imes utput Reference Levels utput Load 50 ns 0.5 x V urrent ource: I L = 3 m (V 2.5 V); I L = 1 m (V < 2.5 V); L = 100 pf Units 3

4 ower-n Reset (R) he NV24M01 incorporates ower n Reset (R) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the R trigger level and will power down into Reset mode when V drops below the R trigger level. his bi directional R behavior protects the device against brown out failure, following a temporary loss of power. in Description L: he erial lock input pin accepts the erial lock signal generated by the Master. D: he erial Data I/ pin receives input data and transmits data stored in EERM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 1 and 2 : he ddress pins accept the device address. hese pins have on chip pull down resistors. W: he Write rotect input pin inhibits all write operations, when pulled HIGH. his pin has an on chip pull down resistor. Functional Description he NV24M01 supports the Inter Integrated ircuit (I 2 ) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all R and conditions. he NV24M01 acts as a lave device. Master and lave alternate as either transmitter or receiver. Up to 4 devices may be connected to the bus as determined by the device address inputs 1 and 2. I 2 Bus rotocol he I 2 bus consists of two wires, L and D. he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the 2 wire bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a R or condition (Figure 2). R he R condition precedes all commands. It consists of a HIGH to LW transition on D while L is HIGH. he R acts as a wake up call to all receivers. bsent a R, a lave will not respond to commands. he condition completes all commands. It consists of a LW to HIGH transition on D while L is HIGH. he starts the internal Write cycle (when following a Write command) or sends the lave into standby mode (when following a Read command). Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address are set to 1010, for normal Read/Write operations (Figure 3). he next 2 bits, 2, 1, select one of 4 possible memory devices connected on a single I 2 bus. he 2 and 1 bits must match the state of the external address pins. he seventh bit, a16 is the most significant internal address bit. he last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. o select an internal memory location (data byte) a 17 bit address word is required: a16 bit from the lave address byte followed by two address bytes. cknowledge fter processing the lave address, the lave responds with an acknowledge () by pulling down the D line during the 9th clock cycle (Figure 4). he lave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the lave shifts out a data byte, and then releases the D line during the 9th clock cycle. If the Master acknowledges the data, then the lave continues transmitting. he Master terminates the session by not acknowledging the last data byte (No) and by sending a to the lave. Bus timing is illustrated in Figure 5. 4

5 L D R NDIIN Figure 2. tart/top iming NDIIN a 16 R/W DEVIE DDRE Figure 3. lave ddress Bits BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FRM MER D UU FRM RNMIER D UU FRM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R t LW t LW L t U: t HD: t HD:D t U:D t U: D IN t t DH t BUF D U Figure 5. Bus iming 5

6 WRIE ERIN Byte Write In Byte Write mode the Master sends a R, followed by lave address, two byte address and data to be written (Figure 6). he lave acknowledges all 4 bytes, and the Master then follows up with a, which in turn starts the internal Write operation (Figure 7). During internal Write, the lave will not acknowledge any Read or Write request from the Master. age Write he NV24M01 contains 131,072 bytes of data, arranged in 512 pages of 256 bytes each. he most significant 9 bits of the address word (a16 from the lave ddress byte and most significant ddress byte) identify the page and the last 8 bits identify the byte within the page. he 17 bit address word (a16 from the lave ddress byte followed by two address bytes) points to the first byte to be written. Up to 256 bytes can be written in one Write cycle (Figure 8). he internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 256 data bytes, then earlier bytes will be overwritten by later bytes in a wrap around fashion (within the selected page). he internal Write cycle starts immediately following the. cknowledge olling cknowledge polling can be used to determine if the NV24M01 is busy writing or is ready to accept commands. olling is implemented by interrogating the device with a elective Read command (see RED ERIN). he NV24M01 will not acknowledge the lave address, as long as internal Write is in progress. Hardware Write rotection With the W pin held HIGH, the entire memory is protected against Write operations. If the W pin is left floating or is grounded, it has no impact on the operation of the NV24M01. he state of the W pin is strobed on the last falling edge of L immediately preceding the first data byte (Figure 9). If the W pin is HIGH during the strobe interval, the NV24M01 will not acknowledge the data byte and the Write request will be rejected. Delivery tate he NV24M01 is shipped erased, i.e., all bytes are FFh. 6

7 BU IVIY: MER R LVE DDRE BYE DDRE a 15 a 8 a 7 a 0 D D LINE Figure 6. Byte Write iming L D 8th Bit Byte n t WR NDIIN R NDIIN DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE BYE DDRE a 15 a 8 a 7 a 0 D D n D n+63 D LINE Figure 8. age Write iming DDRE BYE D BYE L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figure 9. W iming 7

8 RED ERIN Immediate ddress Read In standby mode, the NV24M01 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that previous byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a R, the NV24M01 is presented with a lave address containing a 1 in the R/W bit position (Figure 10), it will acknowledge () in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. he Master can stop further transmission by issuing a No, followed by a condition. elective Read he Read operation can also be started at an address different from the one stored in the internal address counter. he address counter can be initialized by performing a dummy Write operation (Figure 11). Here the R is followed by the lave address (with the R/W bit set to 0 ) and the desired two byte address. Instead of following up with data, the Master then issues a 2nd R, followed by the Immediate ddress Read sequence, as described earlier. equential Read If the Master acknowledges the 1st data byte transmitted by the NV24M01, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will wrap around to the beginning of memory, etc. equential Read works with either Immediate ddress Read or elective Read, the only difference being the starting byte address. BU IVIY: MER R LVE DDRE D LINE D N L 8 9 D 8th Bit D U N Figure 10. Immediate ddress Read iming BU IVIY: MER R LVE DDRE BYE DDRE a 15 a 8 a 7 a 0 R LVE DDRE D D LINE Figure 11. elective Read iming N BU IVIY: MER LVE DDRE D n D n+1 D n+2 D n+x D LINE Figure 12. equential Read iming N 8

9 RDERING INFRMIN Device rder Number pecific Device Marking emperature Range ackage ype hipping NV24M01MUW3VBG W 40 to +125 UDFN8 (b Free, Wettable Flank) 3000 / ape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. 10. ll packages are RoH compliant (b Free, Halogen free). N emiconductor is licensed by the hilips orporation to carry the I 2 bus protocol. 9

10 MEHNIL E ULINE GE DIMENIN 1 LE 2:1 UDFN8 2x3, 0.5 E 517DH IUE DE 06 NV 2015 IN NE INDIR NE DEIL 0.05 D ÇÇ ÇÇ VIEW 1 IDE VIEW D2 1 4 DEIL B L B E 3 L1 EXED u EING LNE L DEIL LERNE NRUIN ÉÉ MLD MD DEIL B LERNE NRUIN L ÉÉÉ 1 3 NE: 1. DIMENINING ND LERNING ER ME Y14.5M, NRLLING DIMENIN: MILLIMEER. 3. DIMENIN b LIE LED ERMINL ND I MEURED BEWEEN 0.15 ND 0.25MM FRM HE ERMINL I. 4. LNRIY LIE HE EXED D WELL HE ERMINL. 5. FR DEVIE N NINING W IN, DEIL B LERNE NRUIN I N LIBLE. MILLIMEER DIM MIN MX REF b D 2.00 B D E 3.00 B E e 0.50 B L L GENERI MRING DIGRM* 1 XXXXX WLYW 8 5 e BM VIEW E2 8X b 0.10 M 0.05 M B NE 3 REMMENDED LDERING FRIN* XXXXX = pecific Device ode = ssembly Location WL = Wafer Lot Y = Year W = Work Week = b Free ackage *his information is generic. lease refer to device data sheet for actual part marking. b Free indicator, G or microdot, may or may not be present X IH 8X 0.30 DIMENIN: MILLIMEER *For additional information on our b Free strategy and soldering details, please download the N emiconductor oldering and Mounting echniques Reference Manual, LDERRM/D. DUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 ctober, 2002 Rev. 0 DERIIN: 98N06579G N EMINDUR NDRD UDFN8 2X3, Electronic versions are uncontrolled except when accessed directly from the Document Repository. rinted versions are uncontrolled except when stamped NRLLED Y in red. ase utline Number: GE 1 F XXX 2

11 DUMEN NUMBER: 98N06579G GE 2 F 2 IUE REVIIN DE RELEED FR RDUIN. REQ. BY I. HYLND. 06 NV 2015 N emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2015 November, 2015 Rev. ase utline Number: 517DH

12 N emiconductor and are trademarks of emiconductor omponents Industries, LL dba N emiconductor or its subsidiaries in the United tates and/or other countries. N emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of N emiconductor s product/patent coverage may be accessed at /site/pdf/atent Marking.pdf. N emiconductor reserves the right to make changes without further notice to any products herein. N emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does N emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using N emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by N emiconductor. ypical parameters which may be provided in N emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. N emiconductor does not convey any license under its patent rights nor the rights of others. N emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use N emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold N emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that N emiconductor was negligent regarding the design or manufacture of the part. N emiconductor is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIIN RDERING INFRMIN LIERURE FULFILLMEN: Literature Distribution enter for N emiconductor E. 32nd kwy, urora, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: N emiconductor Website: rder Literature: For additional information, please contact your local ales Representative