Voltage Supervisor with I 2 C Serial CMOS EEPROM

Transcription

1 140xx Voltage upervisor with I 2 erial MO EEROM FEURE recision ower upply Voltage Monitor 5V, 3.3V, 3V & 2.5V systems 7 threshold voltage options ctive High or Low Reset Valid reset guaranteed at V = 1 V upports tandard and Fast I 2 rotocol 16-Byte age Write Buffer Low power MO technology 1,000,000 rogram/erase cycles 100 year data retention Industrial temperature range RoH-compliant 8-pin OI package For Ordering Information details, see page 14. IN ONFIGURION OI (W) / 08 / 04 / 02 N / N / N / 0 N / N / 1 / 1 N / 2 / 2 / 2 V IN FUNION V R/R L D in Name Function 0, 1, 2 Device ddress Inputs D erial Data Input/Output L erial lock Input R/R Reset Output V ower upply V Ground N No onnect DERIION he 140xx (see table below) are memory and supervisory solutions for microcontroller based systems. MO serial EEROM memory and a system power supervisor with brown-out protection are integrated together. Memory interface is via both the standard (100kHz) as well as fast (400kHz) I 2 protocol. he 140xx provides a precision V sense circuit with two reset output options: MO active low output or MO active high. he REE output is active whenever V is below the reset threshold or falls below the reset threshold voltage. he power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. even reset threshold voltages support 5V, 3.3V, 3V and 2.5V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, I or peripherals from operating. Reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level. MEMORY IZE ELEOR roduct Memory density bit bit bit bit HREHOLD UFFIX ELEOR Nominal hreshold Voltage hreshold uffix Designation 4.63V L 4.38V M 4.00V J 3.08V 2.93V 2.63V R 2.32V Z 2008 ILL. ll rights reserved. 1 Doc. No. MD-1117 Rev. B

2 140xx BLO DIGRM V D L 0 EEROM VOLGE DEEOR R or R 1 2 V BOLUE MXIMUM RING (1) arameters Ratings Units torage emperature -65 to +150 Voltage on ny in with Respect to Ground (2) -0.5 to +6.5 V RELIBILIY HRERII (3) ymbol arameter Min Units NEND (4) Endurance 1,000,000 rogram/ Erase ycles DR Data Retention 100 Years D.. OERING HRERII V = +2.5V to +5.5V unless otherwise specified. Limits ymbol arameter Min. yp. Max. est ondition Units I upply urrent 1 Read or Write at 400kHz m I B tandby urrent V < 5.5V; ll I/O ins at V or V 8 17 V < 3.6V; ll I/O ins at V or V μ I L I/O in Leakage 2 in at GND or V μ V IL Input Low Voltage -0.5 V x 0.3 V V IH Input High Voltage V x 0.7 V V V OL Output Low Voltage D 0.4 V 2.5 V, I OL = 3.0 m V Notes: (1) tresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. hese are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) he D input voltage on any pin should not be lower than -0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than V V, for periods of less than 20 ns. (3) hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E-Q100 and JEDE test methods. (4) age Mode, V = 5 V, 25 Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

3 140xx.. HRERII (MEMORY) (1) V = 2.5V to 5.5V, = -40 to 85, unless otherwise specified. tandard Fast ymbol arameter Min Max Min Max F L lock Frequency khz t HD: R ondition Hold ime µs t LOW Low eriod of L lock µs t HIGH High eriod of L lock µs t U: R ondition etup ime µs t HD:D Data In Hold ime 0 0 µs t U:D Data In etup ime ns t R (2) t F (2) D and L Rise ime ns D and L Fall ime ns t U:O O ondition etup ime µs t BUF Bus Free ime Between O and R µs t L Low to Data Out Valid µs t DH Data Out Hold ime ns i (2) Noise ulse Filtered at L and D Inputs ns t WR Write ycle ime 5 5 ms t U (2, 3) Notes: ower-up to Ready Mode 1 1 ms (1) est conditions according to.. est onditions table. (2) ested initially and after a design or process change that affects this parameter. (3) t U is the delay between the time V is stable and the device is ready to accept commands. Units.. E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource: I OL = 3 m; L = 100 pf 2008 ILL. ll rights reserved. 3 Doc. No. MD-1117 Rev. B

4 140xx ELERIL HRERII (UERVIORY FUNION) V = Full range, = -40º to +85º unless otherwise noted. ypical values at = +25º and V = 5V for L/M/J versions, V = 3.3V for / versions, V = 3V for R version and V = 2.5V for Z version. ymbol arameter hreshold onditions Min yp Max Units V H Reset hreshold Voltage L M J R Z = +25º = -40º to +85º = +25º = -40º to +85º = +25º = -40º to +85º = +25º = -40º to +85º = +25º = -40º to +85º = +25º = -40º to +85º = +25º = -40º to +85º V ymbol arameter onditions Min yp (1) Max Units Reset hreshold empco 30 ppm/º t RD V to Reset Delay (2) V = V H to (V H -100mV) 20 µs t UR Reset ctive imeout eriod = -40º to +85º ms V OL REE Output Voltage Low (ush-pull, active LOW, 140xx9) V = V H min, I IN = 1.2 m R///Z V = V H min, I IN = 3.2 m J/L/M V V > 1.0V, I IN = 50µ 0.3 V OH REE Output Voltage High (ush-pull, active LOW, 140xx9) V = V H max, I OURE = -500µ R///Z V = V H max, I OURE = -800µ J/L/M 0.8V V V V OL REE Output Voltage Low (ush-pull, active HIGH, 140xx1) V > V H max, I IN = 1.2m R///Z V > V H max, I IN = 3.2m J/L/M V V OH REE Output Voltage High (ush-pull, active HIGH, 140xx1) 1.8V < V V H min, I OURE = -150µ 0.8V V Notes: (1) roduction testing done at = +25º; limits over temperature guaranteed by design only. (2) REE output for the 140xx9; REE output for the 140xx1. Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

5 140xx IN DERIION REE/REE : REE OUU his output is available in two versions: MO ctive Low (140xx9) and MO ctive High (140xx1). Both versions are push-pull outputs for high efficiency. D: ERIL D DDRE he erial Data I/O pin receives input data and transmits data stored in EEROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. L: ERIL LO he erial lock input pin accepts the erial lock generated by the Master. and remains asserted for at least 140ms (t UR ) after the power supply voltage has risen above the threshold. Reset output timing is shown in Figure 1. he 140xx devices protect μs against brownout failure. hort duration V transients of 4μsec or less and 100mV amplitude typically do not generate a Reset pulse. Figure 2 shows the maximum pulse duration of negativegoing V transients that do not cause a reset condition. s the amplitude of the transient goes further below the threshold (increasing V H - V ), the maximum pulse duration decreases. In this test, the V starts from an initial voltage of 0.5V above the threshold and drops below it by the amplitude of the overdrive voltage (V H - V ). 0, 1, 2: Device ddress Inputs he ddress inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. DEVIE OERION he 140xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard EEROMs from atalyst emiconductor. RNIEN DURION [µs] 140xxM MB = 25º 140xxZ REE ONROLLER DERIION he reset signal is asserted LOW for the 140xx9 and HIGH for the 140xx1 when the power supply voltage falls below the threshold trip voltage REE OVERDRIVE V H - V [mv] Figure 2. Maximum ransient Duration Without ausing a Reset ulse vs. Overdrive Voltage V H V V RVLID t UR t RD t UR t RD REE 140xx9 REE 140xx1 Figure 1. REE Output iming 2008 ILL. ll rights reserved. 5 Doc. No. MD-1117 Rev. B

6 140xx EMBEDDED EEROM OERION he 140xx supports the Inter-Integrated ircuit (I 2 ) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all R and O conditions. he 140xx acts as a lave device. Master and lave alternate as either transmitter or receiver. I 2 BU ROOOL he I 2 bus consists of two wires, L and D. he two wires are connected to the V supply via pull-up resistors. Master and lave devices connect to the 2-wire bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a R or O condition (Figure 3). he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake-up call to all receivers. bsent a R, a lave will not respond to commands. he O condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. R he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake-up call to all receivers. bsent a R, a lave will not respond to commands. O he O condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. he O starts the internal Write cycle (when following a Write command) or sends the lave into standby mode (when following a Read command). Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8-bit serial lave address. For normal Read/Write operations, the first 4 bits of the lave address are fixed at 1010 (h). he next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. he last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. he 3 address space extension bits are assigned as illustrated in Figure 4. 2, 1 and 0 must match the state of the external address pins, and a 10, a 9 and a 8 are internal address bits. cknowledge fter processing the lave address, the lave responds with an acknowledge () by pulling down the D line during the 9 th clock cycle (Figure 5). he lave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the lave shifts out a data byte, and then releases the D line during the 9 th clock cycle. s long as the Master acknowledges the data, the lave will continue transmitting. he Master terminates the session by not acknowledging the last data byte (No) and by issuing a O condition. Bus timing is illustrated in Figure 6. Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

7 140xx Figure 3. R/O onditions L D R ONDIION O ONDIION Figure 4. lave ddress Bits R/W a8 R/W a9 a8 R/W a10 a9 a8 R/W Figure 5. cknowledge iming BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) EU ( t U:D ) Figure 6. Bus iming t F t HIGH t R t LOW t LOW L t U: t HD:D t HD: t U:D t U:O D IN t t DH t BUF D OU 2008 ILL. ll rights reserved. 7 Doc. No. MD-1117 Rev. B

8 140xx WRIE OERION Byte Write In Byte Write mode, the Master sends the R condition and the lave address with the R/W bit set to zero to the lave. fter the lave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the 140xx. fter receiving another acknowledge from the lave, the Master transmits the data byte to be written into the addressed memory location. he 140xx device will acknowledge the data byte and the Master generates the O condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 7). While this internal cycle is in progress (t WR ), the D output will be tristated and the 140xx will not respond to any request from the Master device (Figure 8). age Write he 140xx writes up to 16 bytes of data in a single write cycle, using the age Write operation (Figure 9). he age Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. fter each byte has been transmitted the 140xx will respond with an acknowledge and internally increments the four low order address bits. he high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the O condition, the address counter wraps around to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the O condition has been sent by the Master, the internal Write cycle begins. t this point all received data is written to the 140xx in a single write cycle. cknowledge olling he acknowledge () polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host s write operation, the 140xx initiates the internal write cycle. he polling can be initiated immediately. his involves issuing the start condition followed by the slave address for a write operation. If the 140xx is still busy with the write operation, No will be returned. If the 140xx has completed the internal write operation, an will be returned and the host can then proceed with the next read or write operation. Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

9 140xx Figure 7. Byte Write equence BU IVIY: MER R LVE DDRE DDRE BYE a7 a0 D BYE d7 d0 O LVE Figure 8. Write ycle iming L D 8 th Bit Byte n t WR O ONDIION R ONDIION DDRE Figure 9. age Write iming BU IVIY: MER R LVE DDRE DDRE BYE D BYE n D BYE n+1 D BYE n+ O LVE n = ILL. ll rights reserved. 9 Doc. No. MD-1117 Rev. B

10 140xx RED OERION Immediate Read Upon receiving a lave address with the R/W bit set to 1, the 140xx will interpret this as a request for data residing at the current byte address in memory. he 140xx will acknowledge the lave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (No) and then follows up with a O condition (Figure 10), the 140xx returns to tandby mode. elective Read elective Read operations allow the Master device to select at random any memory location for a read operation. he Master device first performs a dummy write operation by sending the R condition, slave address and byte address of the location it wishes to read. fter the 140xx acknowledges the byte address, the Master device resends the R condition and the slave address, this time with the R/W bit set to one. he 140xx then responds with its acknowledge and sends the requested data byte. he Master device does not acknowledge the data (No) but will generate a O condition (Figure 11). equential Read If during a Read session, the Master acknowledges the 1 st data byte, then the 140xx will continue transmitting data residing at subsequent locations until the Master responds with a No, followed by a O (Figure 12). In contrast to age Write, during equential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page). OWER-ON REE (OR) Each 140xx incorporates ower-on Reset (OR) circuitry which protects the internal logic against powering up in the wrong state. 140xx device will power up into tandby mode after V exceeds the OR trigger level and will power down into Reset mode when V drops below the OR trigger level. his bi-directional OR feature protects the device against brown-out failure follo wing a temporary loss of power. Delivery tate he 140xx is shipped erased, i.e., all bytes are FFh. Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

11 140xx Figure 10. Immediate Read equence and iming BU IVIY: MER R LVE DDRE N O O LVE D BYE L 8 9 D 8th Bit D OU NO O Figure 11. elective Read equence BU IVIY: N O MER R LVE DDRE DDRE BYE R LVE DDRE O LVE D BYE Figure 12. equential Read equence BU IVIY: MER LVE DDRE O N O LVE D BYE n D BYE n+1 D BYE n+2 D BYE n+x 2008 ILL. ll rights reserved. 11 Doc. No. MD-1117 Rev. B

12 140xx GE OULINE DRWING OI 8-Lead 150 mil (W) E1 E D h x 45 q1 e b 1 L YMBOL MIN NOM MX 1 b D E E e 1.27 B h L q1 0 8 Notes: (1) ll dimensions are in millimeters. (2) omplies with JEDE specification M-012 dimensions. Doc. No. MD-1117 Rev. B ILL. ll rights reserved.

13 140xx ORDERING INFORMION refix Device # uffix W I - G 3 Lead Finish G: Nidu (F) ompany ID roduct ype with Memory Density 02 2-bits 04 4-bits 08 8-bits bits ackage W: OI emperature Range I = Industrial (-40º to 85º) ape & Reel : ape & Reel 3: 3000 units / Reel Reset hreshold Voltage L: 4.50V 4.75V M: 4.25V 4.50V J: 3.89V 4.10V : 3.00V 3.15V : 2.85V 3.00V R: 2.55V 2.70V Z: 2.25V 2.38V upervisor Output ype 9: MO ctive Low 1: MO ctive High Notes: (1) ll packages are RoH-compliant (Lead-free, Halogen-free). (2) he standard lead finish is Nidu pre-plated (F) lead frames. (3) he device used in the above example is a WI-G3 (2b EEROM, with ctive Low MO output, with a reset threshold between 2.85V V, in an OI, Industrial emperature, Nidu, ape and Reel. (4) For additional package and temperature options, please contact your nearest ON emiconductor ales office ILL. ll rights reserved. 13 Doc. No. MD-1117 Rev. B

14 140xx REVIION HIORY Date Rev. Description 9-ept-06 Initial Issue 10-Nov-08 B hange logo and fine print to ON emiconductor ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer's technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor.o. Box 5163, Denver, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter: hone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative Doc. No. MD-1117 Rev. B ILL. ll rights reserved.