CAT34TS V Digital Temperature Sensor

Transcription

1 V Digital emperature ensor Description 3400 is a low-voltage digital temperature sensor, which implements the JEDE J42.4 specification measures temperature every 100 ms over a range of 20 to +125, with a resolution of 12 bits. he host communicates with the device via the serial I 2 / MBus Interface, at either 100 khz or 400 khz. emperature readings can be retrieved via serial interface. Internally, they are compared to high, low and critical trigger limits stored in device registers. Over or under limit conditions can be signaled on the open drain EVEN pin. hese limits, as well as other settings, can be configured via serial interface. Features JEDE J42.4 ompliant emperature ensor upply Range: 1.7 V to 1.9 V emperature Range: 20 to +125 I 2 / MBus Interface emperature ampling Rate: 100 ms max emperature Reading ccuracy: ±0.5 typ for ctive Range (+75 to +95 ) chmitt riggers and Noise uppression Filters on L and D Inputs 2 x 3 x 0.75 mm DFN Package hese Devices are Pb Free and are RoH ompliant ypical pplications olid tate Drives Graphics ards Portable Devices Process ontrol Equipment V 1 2 V PIN ONFIGURION 0 1 DFN8 VP2 UFFIX E 511K DFN (VP2) V EVEN L D For the location of Pin 1, please consult the corresponding package drawing. MRKING DIGRM DFN8 (op View) O LL YM O = pecific Device ode = ssembly Location ode LL = ssembly Lot Number (Last wo Digits) Y = Production Year (Last Digit) M = Production Month (1 9, O, N, D) = Pb Free Package = Pin 1 Indicator PIN FUNION L Pin Name Function 2, 1, EVEN 0, 1, 2 V Device ddress Inputs Ground D D L erial Data Input / Output erial lock Input EVEN Open drain Event Output V Figure 1. Functional ymbol V DP Power upply Backside Exposed DP at V ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. emiconductor omponents Industries, LL, 2016 November, 2018 Rev. 2 1 Publication Order Number: 3400/D

2 3400 able 1. BOLUE MXIMUM RING (Notes 1 and 2) Parameter Rating Unit Voltage on any pin (except 0 ) with respect to Ground (Note 3) 0.5 to +6.5 V Voltage on pin 0 with respect to Ground 0.5 to V Operating emperature 45 to +130 torage emperature Range 65 to +150 tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELERIL HRERII, REOMMENDED OPERING RNGE and/or PPLIION INFORMION for afe Operating parameters. 2. For information, please refer to our oldering and Mounting echniques Reference Manual, OLDERRM/D. 3. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. L and D inputs can be raised to the maximum limit, irrespective of V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. EMPERURE HRERII Parameter onditions Max Unit emperature Reading Error , active range ± , monitor range ± , sensing range ±3.0 D Resolution 12 Bits emperature Resolution onversion ime 100 ms hermal Resistance (Note 4) J Junction to mbient (till ir) 92 /W 4. Power Dissipation is defined as P J = ( J )/ J, where J is the junction temperature and is the ambient temperature. he thermal resistance value refers to the case of a package being used on a standard 2 layer PB. able 3. D.. OPERING HRERII (V = 1.7 V to 1.9 V, = 20 to +125, unless otherwise specified) ymbol Parameter est onditions/omments Min Max Unit I upply urrent active, Bus idle 500 I HDN tandby urrent shut down; Bus idle 5 I LKG I/O Pin Leakage urrent Pin at GND or V 2 V IL Input Low Voltage x V V V IH Input High Voltage 0.7 x V V V V OL Output Low Voltage I OL = 1 m 0.2 V Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2

3 3400 able 4... HRERII (V = 1.7 V to 1.9 V, = 20 to +125 ) ymbol Parameter 100 khz 400 khz Min Max Min Max F L (Note 5) lock Frequency khz t HIGH High Period of L lock s t LOW Low Period of L lock s t IMEOU (Note 6) MBus L lock Low imeout ms t R (Note 7) D and L Rise ime ns t F (Note 7) D and L Fall ime ns t U:D Input Data etup ime ns t U: R ondition etup ime s t HD: R ondition Hold ime s t U:O OP ondition etup ime s t BUF Bus Free ime Between OP and R s t HD:D Input Data Hold ime 0 0 ns t DH (Note 7) Output Data Hold ime ns i (Note 7) Noise Pulse Filtered at L and D Inputs ns t PU (Note 8) Power-Up Delay to Valid emperature Recording ms 5. iming reference points are set at 30%, respectively 70% of V, as illustrated in Figure 5. Bus loading must be such as to allow meeting the V IL and V OL as well as all other timing requirements. he minimum clock frequency of 10 khz is an MBus recommendation; the minimum operating clock frequency is limited only by the MBus time out. he device also meets the Fast and tandard I 2 specifications, except that i and t DH are shorter. 6. For the 3400, the interface will reset itself and will release the D line if the L line stays low beyond the t IMEOU limit. he time out count takes place when L is low in the time interval between R and OP. 7. In a Wired OR system (such as I 2 or MBus), D rise time is determined by bus loading. ince each bus pull down device must be able to sink the (external) bus pull up current (in order to meet the V IL and/or V OL limits), it follows that D fall time is inherently faster than D rise time. D rise time can exceed the standard recommended t R limit, as long as it does not exceed t LOW t DH t U:D, where t LOW and t DH are actual values (rather than spec limits). shorter t DH leaves more room for a longer D t R, allowing for a more capacitive bus or a larger bus pull up resistor. 8. he first valid temperature recording can be expected after t PU at nominal supply voltage. able 5. PIN PINE ( = 25, V = 1.9 V, f = 400 khz) ymbol Parameter est onditions/omments Min Max Unit IN D, EVEN Pin apacitance V IN = 0 8 pf Input apacitance (other pins) V IN = 0 6 pf able 6. INPU IMPEDNE ymbol Parameter est onditions Min Max Unit Z EIL Input Impedance for 0, 1, 2 Pins V IN < 0.3 * V 30 k Z EIH Input Impedance for 0, 1, 2 Pins V IN > 0.7 * V 800 k Units 3

4 3400 PULL UP REINE (k ) ns Rise ime 300 ns Rise ime D V R L L V LOD PINE (pf) Figure 2. Pull up Resistance vs. Load apacitance 4

5 3400 Pin Description L: he erial lock input pin accepts the erial lock generated by the Master (Host). D: he erial Data I/O pin receives input data and transmits data stored in the registers. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2: he ddress pins accept the device address. hese pins have on chip pull down resistors. EVEN: he open drain EVEN pin can be programmed to signal over/under temperature limit conditions. Power On Reset (POR) he 3400 incorporates Power On Reset (POR) circuitry which protects the device against powering up to an undetermined logic state. s V exceeds the POR trigger level, the device will power up into conversion mode. When V drops below the POR trigger level, the device will power down into Reset mode. his bi directional POR behavior protects 3400 against brown out failure following a temporary loss of power. he POR trigger level is set below the minimum operating V level. Device Interface he 3400 supports the Inter Integrated ircuit (I 2 ) and the ystem Management Bus (MBus) data transmission protocols. hese protocols describe serial communication between transmitters and receivers sharing a 2 wire data bus. Data flow is controlled by a Master device, which generates the serial clock and the R and OP conditions. he 3400 acts as a lave device. Master and lave alternate as transmitter and receiver. Up to devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs 0, 1, and 2. he 3400 contains eight 16 bit internal registers which can be accessed for write and read using the I 2 /MBus protocol. I 2 /MBus Protocol he I 2 /MBus uses two wires, one for clock (L) and one for data (D). he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a R or OP condition (Figure 3). R he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake up call to all laves. bsent a R, a lave will not respond to commands. OP he OP condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. he OP tells the lave that no more data will be written to or read from the lave. Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address (the preamble) are fixed at binary 0011 (3hex). he next 3 bits, 2, 1 and 0, select one of 8 possible lave devices. he last bit, R/W, specifies whether a Read (1) or Write (0) operation is being performed. cknowledge matching lave address is acknowledged (K) by the lave by pulling down the D line during the 9 th clock cycle (Figure 4). fter that, the lave will acknowledge all data bytes sent to the bus by the Master. When the lave is the transmitter, the Master will in turn acknowledge data bytes in the 9 th clock cycle. he lave will stop transmitting after the Master does not respond with acknowledge (NoK) and then issues a OP. Bus timing is illustrated in Figure 5. D L R BI Figure 3. tart/top iming OP BI 5

6 3400 L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R Figure 4. cknowledge iming KNOWLEDGE t F t LOW t HIGH t R L 70% 70% 70% 30% 30% 70% D IN t U: t HD: t HD:D t U:D 70% 30% t U:O 70% 30% 30% 70% 70% t BUF D OU 70% 30% t DH Figure 5. Bus iming Write Operations o write data to one of the internal registers, the Master creates a R condition on the bus, and then sends out the appropriate lave address (with the R/W bit set to 0 ), followed by the register address, followed by two data bytes. he matching lave will acknowledge the lave address, register address and each data byte (Figure 6). he Master then ends the session by creating a OP condition on the bus. he OP completes the register update. Read Operations Immediate Read 3400 presented with a lave address containing a 1 in the R/W position will acknowledge the lave address and will then start transmitting the content of the register at the current address pointer location. he Master stops this transmission by responding with NoK, followed by a OP (Figure 7). elective Read he Read operation can be started from a specific address, by preceding the Immediate Read sequence with a data less Write sequence. he Master sends out a R, lave address and register address, but rather than following up with data (as in a Write operation), the Master then issues another R and continues with an Immediate Read sequence (Figure 8). BU IVIY: MER R LVE DDRE REGIER DDRE D (MB) D (LB) O P D LINE P LVE K K K K K K Figure 6. emperature ensor Register Write 6

7 3400 BU IVIY: MER R LVE DDRE K N O O K P D LINE P LVE K D (MB) D (LB) Figure 7. emperature ensor Immediate Read BU IVIY: MER LVE DDRE REGIER DDRE R LVE DDRE K N O O K P P D LINE R LVE K K K D (MB) D (LB) Figure 8. emperature ensor elective Read emperature ensor Operation he component in the 3400 combines a Proportional to bsolute emperature (P) sensor with a modulator, yielding a 12 bit plus sign digital temperature representation. he runs on an internal clock, and starts a new conversion cycle at least every 100 ms. he result of the most recent conversion is stored in the emperature Data Register (DR), and remains there following a hut Down. Reading from the DR does not interfere with the conversion cycle. he value stored in the DR is compared against limits stored in the High Limit Register (HLR), the Low Limit Register (LLR) and/or ritical emperature Register (R). If the measured value is outside the alarm limits or above the critical limit, then the EVEN pin may be asserted. he EVEN output function is programmable, via the onfiguration Register for interrupt mode, comparator mode and polarity. he temperature limit registers can be Read or Written by the host, via the serial interface. t power on, all the (writable) internal registers default to 0x0000, and should therefore be initialized by the host to the desired values. he EVEN output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. While the is enabled (not shut down), event conditions are normally generated by a change in measured temperature as recorded in the DR, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and PB, it is recommended that the exposed backside die attach pad (DP) be soldered to the PB ground plane. Registers he 3400 contains eight 16 bit wide registers allocated to functions, as shown in able 7. Upon power up, the internal address counter points to the capability register. apability Register (User Read Only) his register lists the capabilities of the, as detailed in the corresponding bit map. onfiguration Register (Read/Write) his register controls the various operating modes of the, as detailed in the corresponding bit map. emperature rip Point Registers (Read/Write) he 3400 features 3 temperature limit registers, the HLR, LLR and LR mentioned earlier. he temperature value recorded in the DR is compared to the various limit values, and the result is used to activate the EVEN pin. o avoid undesirable EVEN pin activity, this pin is automatically disabled at power up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two s complement with the LB representing 0.25, as detailed in the corresponding bit maps. emperature Data Register (User Read Only) his register stores the measured temperature, as well as trip status information. B15, B14, and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVEN status or by onfiguration register settings regarding EVEN pin. Measured temperature is represented by bits B12 to B0. Data format is two s complement, where B12 represents the sign, B11 represents 128, etc. and B0 represents

8 3400 Manufacturer ID Register (Read Only) he manufacturer ID assigned by the PI IG trade organization to the 3400 device is fixed at 0x1B09. Device ID and Revision Register (Read Only) his register contains specific device ID and device revision information. able 7. HE EMPERURE ENOR REGIER Register ddress Register Name Power On Default Read/Write 0x00 apability Register 0x0077 Read 0x01 onfiguration Register 0x0000 Read/Write 0x02 High Limit Register 0x0000 Read/Write 0x03 Low Limit Register 0x0000 Read/Write 0x04 ritical Limit Register 0x0000 Read/Write 0x05 emperature Data Register Undefined Read 0x06 Manufacturer ID Register 0x1B09 Read 0x07 Device ID/Revision Register 0x2201 Read able 8. PBILIY REGIER B15 B14 B13 B12 B11 B10 B9 B8 RFU (Note 9) RFU RFU RFU RFU RFU RFU RFU B7 B6 B5 B4 B3 B2 B1 B0 EVD MOU X RE [1:0] RNGE EVEN 9. RFU stands for Reserved for Future Use Bit Description B15:B8 Reserved for future use; can not be written; should be ignored; will read as 0 B7 (Note 10) 0: onfiguration Register bit 4 is frozen upon onfiguration Register bit 8 being set (i.e. a shut down freezes the EVEN output) 1: onfiguration Register bit 4 is cleared upon onfiguration Register bit 8 being set (i.e. a shut down de asserts the EVEN output) B6 0: Not used 1: he implements MBus time out within the range 25 to 35 ms B5 X: May be 0 or 1 (Default = 1) B4:B3 00: LB = 0.50 (9 bit resolution) 01: LB = 0.25 (10 bit) 10: LB = (11 bit) 11: LB = (12 bit) B2 0: Not used 1: he temperature monitor can read temperatures below 0 and sets the sign bit appropriately B1 0: Not used 1: he temperature monitor has ±1 accuracy over the active range (75 to 95 ) and ±2 accuracy over the monitoring range (40 to 125 ) B0 0: Not used 1: he device supports interrupt capabilities 10. onfiguration Register bit 4 can be cleared (but not set) after onfiguration Register bit 8 is set, by writing a 1 to onfiguration Register bit 5 (EVEN output can be de asserted during shut down periods) 8

9 3400 able 9. ONFIGURION REGIER B15 B14 B13 B12 B11 B10 B9 B8 RFU RFU RFU RFU RFU HY [1:0] HDN B7 B6 B5 B4 B3 B2 B1 B0 RI_LOK LRM_LOK LER EVEN_ EVEN_RL RI_ONLY EVEN_POL EVEN_MODE Bit Description B15:B11 Reserved for future use; can not be written; should be ignored; will read as 0 B10:B9 (Note 11) 00: Disable hysteresis 01: et hysteresis at : et hysteresis at 3 11: et hysteresis at 6 B8 (Note 15) 0: hermal ensor is enabled; temperature readings are updated at sampling rate 1: hermal ensor is shut down; temperature reading is frozen to value recorded before HDN B7 (Note 14) 0: ritical trip register can be updated 1: ritical trip register cannot be modified; this bit can be cleared only at POR B6 (Note 14) 0: larm trip registers can be updated 1: larm trip registers cannot be modified; this bit can be cleared only at POR B5 (Note 13) 0: lways reads as 0 (self clearing) 1: Writing a 1 to this position clears an event recording in interrupt mode only B4 (Note 12) 0: EVEN output pin is not being asserted 1: EVEN output pin is being asserted B3 (Note 11) 0: EVEN output disabled; polarity dependent: open drain for B1 = 0; grounded for B1 = 1 1: EVEN output enabled B2 (Note 17) 0: event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only B1 (Notes 11, 16) 0: EVEN output active low 1: EVEN output active high B0 (Note 11) 0: omparator mode 1: Interrupt mode 11. annot be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set. 12.his bit is a polarity independent software copy of the EVEN pin, i.e. it is under the control of B3. his bit is read only. 13.Writing a 1 to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 9). 14.leared at power on reset (POR). Once set, this bit can only be cleared by a POR condition. 15.he powers up into active mode, i.e. this bit is cleared at power on reset (POR). When the is shut down the D is disabled and the temperature reading is frozen to the most recently recorded value. he cannot be shut down (B8 cannot be set) as long as either one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. 16.he EVEN output is open drain and requires an external pull up resistor for either polarity. he natural polarity is active low, as it allows wired or operation on the EVEN bus. 17.annot be set as long as lock bit B6 is set. 9

10 3400 able 10. HIGH LIMI REGIER B15 B14 B13 B12 B11 B10 B9 B ign B7 B6 B5 B4 B3 B2 B1 B able 11. LOW LIMI REGIER B15 B14 B13 B12 B11 B10 B9 B ign B7 B6 B5 B4 B3 B2 B1 B able 12. RI LIMI REGIER B15 B14 B13 B12 B11 B10 B9 B ign B7 B6 B5 B4 B3 B2 B1 B able 13. EMPERURE D REGIER B15 B14 B13 B12 B11 B10 B9 B8 RI HIGH LOW ign B7 B6 B5 B4 B3 B2 B1 B (Note 18) 18. When supported as defined by apability Register bits RE (1:0) (Note 18) (Note 18) Bit B15 B14 B13 B12 0: emperature is below the RI limit 1: emperature is above the RI limit 0: emperature is below the High limit 1: emperature is above the High limit 0: emperature is above the Low limit 1: emperature is below the Low limit 0: Positive temperature 1: Negative temperature Description 10

11 3400 Register Data Format he values used in the temperature data register and the 3 temperature trip point registers are expressed in two s complement format. he measured temperature value is expressed with 12 bit resolution, while the 3 trip temperature limits are set with 10 bit resolution. he total temperature range is arbitrarily defined as 256, thus yielding an LB of for the measured temperature and 0.25 for the 3 limit values. Bit B12 in all temperature registers represents the sign, with a 0 indicating a positive, and a 1 a negative value. In two s complement format, negative values are obtained by complementing their positive counterpart and adding a 1, so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. Note that trailing 0 bits, are 0 irrespective of polarity. herefore the don t care bits (B1 and B0) in the 10 bit resolution temperature limit registers, are always 0. able BI EMPERURE D FORM Binary (B12 to B0) Hex emperature E E FFF D Event Pin Functionality he EVEN output reacts to temperature changes as illustrated in Figure 9, and according to the operating mode defined by the onfiguration register. In Interrupt Mode, the (enabled) EVEN output will be asserted every time the temperature crosses one of the alarm window limits, and can be de asserted by writing a 1 to the clear event bit (B5) in the configuration register. Once the temperature exceeds the critical limit, the EVEN remains asserted as long as the temperature stays above the critical limit and cannot be cleared. clear request sent to the 3400 while the temperature is above the critical limit will be acknowledged, but will be executed only after the temperature drops below the critical limit. In omparator Mode, the EVEN output is asserted outside the alarm window limits, while in ritical emperature Mode, EVEN is asserted only above the critical limit. lear requests are ignored in this mode. he exact trip limits are determined by the 3 temperature limit settings and the hysteresis offsets, as illustrated in Figure 10. Following a shut down request, the converter is stopped and the most recently recorded temperature value present in the DR is frozen; the EVEN output will continue to reflect the state immediately preceding the shut down command. herefore, if the state of the EVEN output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the. his may require clearing the event, disabling the EVEN output or perhaps changing the EVEN output polarity. In normal use, events are triggered by a change in recorded temperature, but the 3400 will also respond to limit register changes. Whereas recorded temperature values are updated at sampling rate frequency, limits can be modified at any time. he enabled EVEN output will react to limit changes as soon as the respective registers are updated. his feature may be useful during testing. 11

12 3400 EMPERURE RIIL HYEREI FFE HEE RIP POIN UPPER LRM WINDOW LOWER IME EVEN in INERRUP Mode EVEN in INERRUP Mode EVEN in INERRUP Mode EVEN in OMPROR Mode EVEN in RIIL EMP ONLY Mode lear request executed immediately lear request acknowledged but execution delayed until measured temperature drops below the active ritical emperature limit Figure 9. Event Detail H H HY L L HY BELOW WINDOW BI BOVE WINDOW BI Figure 10. Hysteresis Detail 12

13 3400 PKGE DIMENION DFN8, 2x3, 0.5P E 511K IUE B PIN ONE REFERENE NOE D ÇÇ ÇÇ OP VIEW DEIL B 1 IDE VIEW B E 3 L1 EING PLNE L DEIL LERNE ONRUION EXPOED u L MOLD MPD DEIL B LERNE ONRUION NOE: 1. DIMENIONING ND OLERNING PER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DIMENION b PPLIE O PLED ERMINL ND I MEURED BEWEEN 0.15 ND 0.25MM FROM HE ERMINL IP. 4. OPLNRIY PPLIE O HE EXPOED PD WELL HE ERMINL. MILLIMEER DIM MIN MX REF b D 2.00 B D E 3.00 B E e 0.50 B L L REOMMENDED OLDERING FOOPRIN* DEIL D2 1 4 L X 0.68 E e BOOM VIEW 8X b 0.10 M 0.05 M B NOE PIH 8X 0.30 DIMENION: MILLIMEER *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. 13

14 3400 Example of Ordering Information Device Order Number pecific Device Marking Package ype hipping 3400VP2G4 O DFN8 ape & Reel, 4,000 Units / Reel 19. ll packages are RoH compliant (Lead free, Halogen free) 20. he standard lead finish is NiPdu. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8011/D. ON emiconductor is licensed by Philips orporation to carry the I 2 Bus Protocol. ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor E. 32nd Pkwy, urora, olorado U Phone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative 3400/D