CAT34TS02. Digital Output Temperature Sensor with On-board SPD EEPROM

Transcription

1 Digital Output emperature ensor with On-board D EEOM Description he combines a J42.4 compliant emperature ensor () with 2 b of erial resence Detect (D) EEOM. he measures temperature at least 1 times every second. emperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open drain EVEN pin. he integrated 2 b D EEOM is internally organized as 16 pages of 16 bytes each, for a total of 6 bytes. It features a 16 byte page write buffer and supports both the tandard ( khz) as well as Fast (4 khz) I 2 protocol. Write operations to the lower half memory can be inhibited via software commands. he features ermanent, as well as eversible oftware Write rotection, as defined for DD3 DIMMs. Features JEDE J42.4 ompliant emperature ensor emperature ange: 2 to +1 DD3 DIMM ompliant D EEOM upply ange: 3.3 V ± 1% I 2 / MBus Interface chmitt riggers and Noise uppression Filters on L and D Inputs Low ower MO echnology 2 x 3 x. mm DFN ackage hese Devices are b Free and are oh ompliant V 1 2 V IN ONFIGUION 1 DFN 8 V2 UFFIX E 511 V EVEN L D (op View) For the location of in 1, please consult the corresponding package drawing. MING DIGM GX LL YM GX = pecific Device ode = ssembly Location ode LL = ssembly Lot Number (Last wo Digits) Y = roduction Year (Last Digit) M = roduction Month (1 9, O, N, D) = b Free ackage L IN FUNION 2, 1, EVEN in Name, 1, 2 Function Device ddress Input D D L erial Data Input/Output erial lock Input EVEN Open drain Event Output V Figure 1. Functional ymbol V V ower upply Ground D Backside Exposed D at V ODEING INFOMION ee detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. emiconductor omponents Industries, LL, ublication Order Number: February, 213 ev. 1 /D

2 able 1. BOLUE MXIMUM ING arameter ating Units Operating emperature 45 to +13 torage emperature 65 to +1 Voltage on any pin (except ) with respect to Ground (Note 1).5 to +6.5 V Voltage on pin with respect to Ground.5 to +1.5 V tresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating onditions is not implied. Extended exposure to stresses above the ecommended Operating onditions may affect device reliability. 1. he D input voltage on any pin should not be lower than.5 V or higher than V +.5 V. he pin can be raised to a HV level for W command execution. L and D inputs can be raised to the maximum limit, irrespective of V. able 2. ELIBILIY HEII (Note 3) ymbol arameter Min Units N END (Note 2) Endurance (EEOM) 1,, Write ycles D Data etention (EEOM) Years 2. age Mode, V = 3.3 V, able 3. EMEUE HEII (V = 3.3 V ± 1%, = 2 to +1, unless otherwise specified) emperature eading Error lass B, J42.4 compliant arameter est onditions/omments Max Unit + +95, active range ± , monitor range ± , sensing range ±3. D esolution 12 Bits emperature esolution.6 onversion ime ms hermal esistance (Note 3) J Junction to mbient (till ir) 92 /W 3. ower Dissipation is defined as J = ( J )/ J, where J is the junction temperature and is the ambient temperature. he thermal resistance value refers to the case of a package being used on a standard 2 layer B. able 4. D.. OEING HEII (V = 3.3 V ± 1%, = 2 to +1, unless otherwise specified) ymbol arameter est onditions/omments Min Max Unit I upply urrent active, D and Bus idle D Write, shut down I HDN tandby urrent shut down; D and Bus idle 1 I LG I/O in Leakage urrent in at GND or V 2 V IL Input Low Voltage.5.3 x V V V IH Input High Voltage.7 x V V +.5 V V OL1 Output Low Voltage I OL = 3 m, V > 2.7 V.4 V V OL2 Output Low Voltage I OL = 1 m, V < 2.7 V.2 V 2

3 able 5... HEII (V = 3.3 V ± 1%, = 2 to +1 ) (Note 4) ymbol arameter Min Max Units F L (Note 5) lock Frequency 1 4 khz t HIGH High eriod of L lock 6 ns t LOW Low eriod of L lock 13 ns t IMEOU (Note 5) MBus L lock Low imeout 35 ms t (Note 6) D and L ise ime 3 ns t F (Note 6) D and L Fall ime 3 ns t U:D (Note 7) Data etup ime ns t U: ondition etup ime 6 ns t HD: ondition Hold ime 6 ns t U:O O ondition etup ime 6 ns t BUF Bus Free ime Between O and 13 ns t HD:D Input Data Hold ime ns t DH (Note 6) Output Data Hold ime 2 9 ns i Noise ulse Filtered at L and D Inputs ns t W Write ycle ime 5 ms t U (Note 8) ower up Delay to Valid emperature ecording ms 4. iming reference points are set at 3%, respectively 7% of V, as illustrated in Figure 23. Bus loading must be such as to allow meeting the V IL, V OL as well as the various timing limits. 5. For the ev. B, the interface will reset itself and will release the D line if the L line stays low beyond the t IMEOU limit. he time out count is started (and then re started) on every negative transition of L in the time interval between and O. he minimum clock frequency of 1 khz is an MBus recommendation; the minimum operating clock frequency for the s D component is D, while the minimum operating frequency for the component is limited only by the MBus time out. For the ev., both the and the D implement the time out feature. 6. In a Wired O system (such as I 2 or MBus), D rise time is determined by bus loading. ince each bus pull down device must be able to sink the (external) bus pull up current (in order to meet the V IL and/or V OL limits), it follows that D fall time is inherently faster than D rise time. D rise time can exceed the standard recommended t limit, as long as it does not exceed t LOW t DH t U:D, where t LOW and t DH are actual values (rather than spec limits). shorter t DH leaves more room for a longer D t, allowing for a more capacitive bus or a larger bus pull up resistor. t the minimum t LOW spec limit of 13 ns, the maximum t DH of 9 ns demands a maximum D t of 3 ns. he s maximum t DH is <7 ns, thus allowing for an D t of up to ns at minimum t LOW. 7. he minimum t U:D of ns is a limit recommended by standards. he will accept a t U:D of ns. 8. he first valid temperature recording can be expected after t U at nominal supply voltage. able 6. IN INE ( =, V = 3.3 V, f = 1 MHz) ymbol arameter est onditions/omments Min Max Unit IN D, EVEN in apacitance V IN = 8 pf Input apacitance (other pins) V IN = 6 pf 3

4 YIL EFOMNE HEII (V = 3.3 V, = 2 to +1, unless otherwise specified.) I ( ) 1 I ( ) Figure 2. ctive urrent (ev. B) (I 2 bus and D EEOM Idle) Figure 3. ctive urrent (ev. ) (I 2 bus and D EEOM Idle) I HDN ( ) 4 3 I HDN ( ) Figure 4. tandby urrent (ev. B) (I 2 bus and D EEOM Idle, hut down) Figure 5. tandby urrent (ev. ) (I 2 bus and D EEOM Idle, hut down) 4 4 I _W ( ) 3 I _W ( ) Figure 6. D EEOM Write urrent (ev. B) (I 2 bus Idle, hut down) Figure 7. D EEOM Write urrent (ev. ) (I 2 bus Idle, hut down) 4

5 YIL EFOMNE HEII (V = 3.3 V, = 2 to +1, unless otherwise specified.) art # art # 2 ( ) 1 2 art # 1 ( ) 1 2 art # Figure 8. emperature ead Out Error (ev. B) Figure 9. emperature ead Out Error (ev. ) ONV (ms) 6 4 ONV (ms) Figure 1. /D onversion ime (ev. B) Figure 11. /D onversion ime (ev. ) t W (ms) 3.5 t W (ms) Figure 12. EEOM Write ime (ev. B) Figure 13. EEOM Write ime (ev. ) 1 5

6 YIL EFOMNE HEII (V = 3.3 V, = 2 to +1, unless otherwise specified.) V H (V) V H (V) U DN 1. Figure 14. O hreshold Voltage (ev. B) 1 Figure 15. O hreshold Voltage (ev. ) V H (V) V H (V) U DN Figure 16. D O hreshold Voltage (ev. B) Figure 17. D O hreshold Voltage (ev. ) t IMEOU (ms) 3 t IMEOU (ms) Figure 18. MBus L lock Low imeout (ev. B) Figure 19. MBus L lock Low imeout (ev. ) 6

7 in Description L: he erial lock input pin accepts the erial lock generated by the Master (Host). D: he erial Data I/O pin receives input data and transmits data stored in the internal registers. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L., 1 and 2: he ddress pins accept the device address. hese pins have on chip pull down resistors. EVEN: he open drain EVEN pin can be programmed to signal over/under temperature limit conditions. ower On eset (O) he incorporates ower On eset (O) circuitry which protects the device against powering up to invalid state. he component will power up into conversion mode after V exceeds the O trigger level and the D component will power up into standby mode after V exceeds the D O trigger level. Both the and D components will power down into eset mode when V drops below their respective O trigger levels. his bi directional O behavior protects the against brown out failure following a temporary loss of power. he O trigger levels are set below the minimum operating V level. Device Interface he supports the Inter Integrated ircuit (I 2 ) and the ystem Management Bus (MBus) data transmission protocols. hese protocols describe serial communication between transmitters and receivers sharing a 2 wire data bus. Data flow is controlled by a Master device, which generates the serial clock and the and O conditions. he acts as a lave device. Master and lave alternate as transmitter and receiver. Up to 8 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs, 1, and 2. I 2 /MBus rotocol he I 2 /MBus uses two wires, one for clock (L) and one for data (D). he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a or O condition (Figure 2). he condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he acts as a wake up call to all laves. bsent a, a lave will not respond to commands. O he O condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. he O tells the lave that no more data will be written to or read from the lave. Device ddressing he Master initiates data transfer by creating a condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address (the preamble) select either the emperature ensor () registers (11) or the EEOM memory contents (11), as shown in Figure 21. he next 3 bits, 2, 1 and, select one of 8 possible lave devices. he last bit, /W, specifies whether a ead (1) or Write () operation is being performed. cknowledge matching lave address is acknowledged () by the lave by pulling down the D line during the 9 th clock cycle (Figure 22). fter that, the lave will acknowledge all data bytes sent to the bus by the Master. When the lave is the transmitter, the Master will in turn acknowledge data bytes in the 9 th clock cycle. he lave will stop transmitting after the Master does not respond with acknowledge (No) and then issues a O. Bus timing is illustrated in Figure 23. 7

8 D L BI Figure 2. tart/top iming O BI EEOM /W EMEUE ENO 1 1 EMBLE 2 1 /W DEVIE DDE Figure 21. lave ddress Bits L FOM D OUU FOM NMIE D OUU FOM EEIVE Figure 22. cknowledge iming NOWLEDGE t F t LOW t HIGH t L 7% 7% 7% 3% 3% 7% D t U: t HD: t HD:D t U:D 7% 3% t U:O 7% 3% 3% 7% 7% t BUF Figure 23. Bus iming 8

9 Write Operations EEOM Byte and egister Write o write data to a register, or to the on board EEOM, the Master creates a condition on the bus, and then sends out the appropriate lave address (with the /W bit set to ), followed by an address byte and data byte(s). he matching lave will acknowledge the lave address, EEOM byte or register address and the data byte(s), one for EEOM data (Figure 24) and two for register data (Figure ). he Master then ends the session by creating a O condition on the bus. he O completes the (volatile) register update or starts the internal Write cycle for the (non volatile) EEOM data (Figure 26). EEOM age Write he on board EEOM contains 6 bytes of data, arranged in 16 pages of 16 bytes each. page is selected by the 4 most significant bits of the address byte immediately following the lave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 27). he internal EEOM byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier data will be overwritten by later data in a wrap around fashion within the selected page. he internal Write cycle, using the most recently loaded data, then starts immediately following the O. cknowledge olling cknowledge polling can be used to determine if the is busy writing to EEOM, or is ready to accept commands. olling is executed by interrogating the device with a elective ead command (see ED OEION). he will not acknowledge the lave address as long as internal EEOM Write is in progress. Delivery tate he is shipped unprotected, i.e. neither oftware Write rotection (W) flag is set. he entire 2 b memory is erased, i.e. all bytes are xff. BU IVIY: D LVE DDE BYE DDE D O D LINE LVE Figure 24. EEOM Byte Write BU IVIY: LVE DDE EGIE DDE D (MB) D (LB) O D LINE LVE Figure. emperature ensor egister Write L D 8th Bit Byte n t W O ONDIION ONDIION DDE Figure 26. EEOM Write ycle iming 9

10 BU IVIY: D LVE DDE BYE DDE (n) D n D n+1 D n+ O D LINE LVE NOE: In this example n = XXXX (B); X = 1 or Figure 27. EEOM age Write ead Operations Immediate ead Upon power up, the address counters for both the emperature ensor () and on board EEOM are initialized to h. he address counter will thus point to the apability egister and the EEOM address counter will point to the first location in memory. he two address counters may be updated by subsequent operations. presented with a lave address containing a 1 in the /W position will acknowledge the lave address and will then start transmitting data being pointed at by the current EEOM data or respectively register address counter. he Master stops this transmission by responding with No, followed by a O (Figure 28). elective ead he ead operation can be started at an address different from the one stored in the respective address counters, by preceding the Immediate ead sequence with a data less Write operation. he Master sends out a, lave address and address byte, but rather than following up with data (as in a Write operation), the Master then issues another and continuous with an Immediate ead sequence (Figure 29). equential EEOM ead EEOM data can be read out indefinitely, as long as the Master responds with (Figure 3). he internal address count is automatically incremented after every data byte sent to the bus. If the end of memory is reached during continuous ead, then the address counter wraps around to beginning of memory, etc. equential ead works with either Immediate ead or elective ead, the only difference being that in the latter case the starting address is intentionally updated. BU IVIY: D LVE DDE N O O D LINE LVE D BU IVIY: LVE DDE N O O D LINE LVE D (MB) D (LB) Figure 28. Immediate ead 1

11 BU IVIY: D LVE DDE BYE DDE (n) LVE DDE N O O D LINE LVE D n BU IVIY: LVE DDE EGIE DDE LVE DDE N O O D LINE LVE D (MB) D (LB) Figure 29. elective ead BU IVIY: D LVE DDE N O O D LINE LVE D n D n+1 D n+2 Figure 3. EEOM equential ead D n+x oftware Write rotection he lower half of memory (first 128 bytes) can be protected against Write requests by setting one of two oftware Write rotection (W) flags. he ermanent oftware Write rotection (W) flag can be set or read while all address pins are at regular MO levels (GND or V ), whereas the very high voltage V HV must be present on address pin to set, clear or read the eversible oftware Write rotection (W) flag. he D.. OEING ONDIION for W operations are shown in able 7. he W commands are listed in able 8. ll commands are preceded by a and terminated with a O, following the or No from the. ll W related lave addresses use the pre amble: 11 (6h), instead of the regular 11 (h) used for memory access. For W commands, the three address pins can be at any logic level, whereas for W commands the address pins must be at pre assigned logic levels. V HV is interpreted as logic 1. he V HV condition must be established on pin before the and maintained just beyond the O. Otherwise an W request could be interpreted by the as a W request. he W lave addresses follow the standard I 2 convention, i.e. to read the state of the W flag, the LB of the lave address must be 1, and to set or clear a flag, it must be. For Write commands a dummy byte address and dummy data byte must be provided (Figure 31). In contrast to a regular memory ead, a W ead does not return Data. Instead the will respond with No if the flag is set and with if the flag is not set. herefore, the Master can immediately follow up with a O, as there is no meaningful data following the interval (Figure 32). 11

12 able 7. W D.. OEION ONDIION ymbol arameter est onditions Min Max Units V HV Overdrive (V HV V ) 4.8 V I HVD High Voltage Detector urrent 1.7 V < V < 3.6 V.1 m V HV Very High Voltage 7 1 V able 8. W OMMND ction et W ontrol in Levels (Note 9) Flag tate (Note 1) 2 1 W W X lave ddress b7 to b4 b3 b2 b1 b? 2 1 X No 2 1 X 2 1 Yes X Yes X Yes Yes 2 1 X Yes ddress Byte? Data Byte? Write ycle GND GND V HV 1 X 1 X No et W GND GND V HV 1 1 X No 11 GND GND V HV 1 Yes X Yes X Yes Yes lear W GND GND V HV 1 1 Yes GND V V HV 1 X 1 1 X No GND V V HV X 1 1 Yes X Yes X Yes Yes GND V V HV X Yes 9. Here 2, 1 and are either at V or GND. 1.1 stands for et, stands for Not et, X stands for don t care. BU IVIY: LVE DDE BYE DDE D O D LINE X XXXXXXX X XXXXXXX LVE or N O X = Don t are Figure 31. oftware Write rotect (Write) BU IVIY: LVE DDE O D LINE LVE or N O Figure 32. oftware Write rotect (ead) 12

13 emperature ensor Operation he component in the combines a roportional to bsolute emperature () sensor with a modulator, yielding a 12 bit plus sign digital temperature representation. he runs on an internal clock, and starts a new conversion cycle at least every ms. he result of the most recent conversion is stored in the emperature Data egister (D), and remains there following a hut Down. eading from the D does not interfere with the conversion cycle. he value stored in the D is compared against limits stored in the High Limit egister (HL), the Low Limit egister (LL) and/or ritical emperature egister (). If the measured value is outside the alarm limits or above the critical limit, then the EVEN pin may be asserted. he EVEN output function is programmable, via the onfiguration egister for interrupt mode, comparator mode and polarity. he temperature limit registers can be ead or Written by the host, via the serial interface. t power on, all the (writable) internal registers default to x, and should therefore be initialized by the host to the desired values. he EVEN output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. While the is enabled (not shut down), event conditions are normally generated by a change in measured temperature as recorded in the D, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and B, it is recommended that the exposed backside die attach pad (D) be soldered to the B ground plane. egisters he contains eight 16 bit wide registers allocated to functions, as shown in able 9. Upon power up, the internal address counter points to the capability register. apability egister (User ead Only) his register lists the capabilities of the, as detailed in the corresponding bit map. onfiguration egister (ead/write) his register controls the various operating modes of the, as detailed in the corresponding bit map. emperature rip oint egisters (ead/write) he features 3 temperature limit registers, the HL, LL and L mentioned earlier. he temperature value recorded in the D is compared to the various limit values, and the result is used to activate the EVEN pin. o avoid undesirable EVEN pin activity, this pin is automatically disabled at power up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two s complement with the LB representing., as detailed in the corresponding bit maps. emperature Data egister (User ead Only) his register stores the measured temperature, as well as trip status information. B15, B14, and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVEN status or by onfiguration register settings. Measured temperature is represented by bits B12 to B. Data format is two s complement, where B12 represents the sign, B11 represents 128, etc. and B represents.6. Manufacturer ID egister (ead Only) he manufacturer ID assigned by the I IG trade organization to the device is fixed at x1b9. able 9. HE EGIE Device ID and evision egister (ead Only) his register contains manufacturer specific device ID and device revision information. egister ddress egister Name ower On Default ead/write x apability egister x7f ead x1 onfiguration egister x ead/write x2 High Limit egister x ead/write x3 Low Limit egister x ead/write x4 ritical Limit egister x ead/write x5 emperature Data egister Undefined ead x6 Manufacturer ID egister x1b9 ead x7 Device ID/evision egister ev. B x813 ead ev. x 13

14 able 1. BILIY EGIE B15 B14 B13 B12 B11 B1 B9 B8 FU FU FU FU FU FU FU FU B7 B6 B5 B4 B3 B2 B1 B EVD MOU FU E [1:] NGE EVEN Bit Description B15:B8 eserved for future use; can not be written; should be ignored; will read as B7 (Note 11) : onfiguration egister bit 4 is frozen upon onfiguration egister bit 8 being set (i.e. a shut down freezes the EVEN output) 1: onfiguration egister bit 4 is cleared upon onfiguration egister bit 8 being set (i.e. a shut down de asserts the EVEN output) B6 : he implements MBus time out within the range 1 to 6 ms 1: he implements MBus time out within the range to 35 ms B5 : in V HV compliance required for W Write/lear operations not explicitly stated 1: in V HV compliance required for W Write/lear operations explicitly stated B4:B3 : LB =. (9 bit resolution) 1: LB =. (1 bit) 1: LB =.1 (11 bit) 11: LB =.6 (12 bit) B2 : ositive emperature Only 1: ositive and Negative emperature B1 : ±2 over the active range and ±3 over the operating range (lass ) 1: ±1 over the active range and ±2 over the monitor range (lass B) B : ritical emperature only 1: larm and ritical emperature 11. onfiguration egister bit 4 can be cleared (but not set) after onfiguration egister bit 8 is set, by writing a 1 to onfiguration egister bit 5 (EVEN output can be de-asserted during shut-down periods) 14

15 able 11. ONFIGUION EGIE B15 B14 B13 B12 B11 B1 B9 B8 FU FU FU FU FU HY [1:] HDN B7 B6 B5 B4 B3 B2 B1 B I_LO EVEN_LO LE EVEN_ EVEN_L I_ONLY EVEN_OL EVEN_MODE Bit Description B15:B11 eserved for future use; can not be written; should be ignored; will read as B1:B9 (Note 12) : Disable hysteresis 1: et hysteresis at 1.5 1: et hysteresis at 3 11: et hysteresis at 6 B8 (Note 16) : hermal ensor is enabled; temperature readings are updated at sampling rate 1: hermal ensor is shut down; temperature reading is frozen to value recorded before HDN B7 (Note 15) : ritical trip register can be updated 1: ritical trip register cannot be modified; this bit can be cleared only at O B6 (Note 15) : larm trip registers can be updated 1: larm trip registers cannot be modified; this bit can be cleared only at O B5 (Note 14) : lways reads as (self clearing) 1: Writing a 1 to this position clears an event recording in interrupt mode only B4 (Note 13) : EVEN output pin is not being asserted 1: EVEN output pin is being asserted B3 (Note 12) : EVEN output disabled; polarity dependent: open drain for B1 = ; grounded for B1 = 1 1: EVEN output enabled B2 (Note 18) : event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only B1 (Notes 12, 17) : EVEN output active low 1: EVEN output active high B (Note 12) : omparator mode 1: Interrupt mode 12.an not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set. 13.his bit is a polarity independent software copy of the EVEN pin, i.e. it is under the control of B3. his bit is read only. 14.Writing a 1 to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 24). 15.leared at power-on reset (O). Once set, this bit can only be cleared by a O condition. 16.he powers up into active mode, i.e. this bit is cleared at power-on reset (O). When the is shut down the D is disabled and the temperature reading is frozen to the most recently recorded value. he can not be shut down (B8 can not be set) as long as either one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. 17.he EVEN output is open-drain and requires an external pull-up resistor for either polarity. he natural polarity is active low, as it allows wired-or operation on the EVEN bus. 18.an not be set as long as lock bit B6 is set. 15

16 able 12. HIGH LIMI EGIE B15 B14 B13 B12 B11 B1 B9 B8 ign B7 B6 B5 B4 B3 B2 B1 B able 13. LOW LIMI EGIE B15 B14 B13 B12 B11 B1 B9 B8 ign B7 B6 B5 B4 B3 B2 B1 B able 14. I LIMI EGIE B15 B14 B13 B12 B11 B1 B9 B8 ign B7 B6 B5 B4 B3 B2 B1 B able 15. EMEUE D EGIE B15 B14 B13 B12 B11 B1 B9 B8 I HIGH LOW ign B7 B6 B5 B4 B3 B2 B1 B (Note 19) 19. When applicable (as defined by apability bit E), unsupported bits will read as.1 (Note 19).6 (Note 19) Bit B15 B14 B13 B12 : emperature is below the I limit 1: emperature is equal to or above the I limit : emperature is equal to or below the High limit 1: emperature is above the High limit : emperature is equal to or above the Low limit 1: emperature is below the Low limit : ositive temperature 1: Negative temperature Description 16

17 egister Data Format he values used in the temperature data register and the 3 temperature trip point registers are expressed in two s complement format. he measured temperature value is expressed with 12 bit resolution, while the 3 trip temperature limits are set with 1 bit resolution. he total temperature range is arbitrarily defined as 6, thus yielding an LB of.6 for the measured temperature and. for the 3 limit values. Bit B12 in all temperature registers represents the sign, with a indicating a positive, and a 1 a negative value. In two s complement format, negative values are obtained by complementing their positive counterpart and adding a 1, so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. Note that trailing bits, are irrespective of polarity. herefore the don t care bits (B1 and B) in the 1 bit resolution temperature limit registers, are always. able BI EMEUE D FOM Binary (B12 to B) Hex emperature E E FFF D +1 Event in Functionality he EVEN output reacts to temperature changes as illustrated in Figure 33, and according to the operating mode defined by the onfiguration register. In Interrupt Mode, the enabled EVEN output will be asserted every time the temperature crosses one of the alarm window limits, and can be de asserted by writing a 1 to the clear event bit (B5) in the configuration register. When the temperature exceeds the critical limit, the event remains asserted as long as the temperature stays above the critical limit and can not be cleared. In omparator Mode, the EVEN output is asserted outside the alarm window limits, while in ritical emperature Mode, EVEN is asserted only above the critical limit. he exact trip limits are determined by the 3 temperature limit settings and the hysteresis offsets, as illustrated in Figure 34. Following a shut down request, the converter is stopped and the most recently recorded temperature value present in the D is frozen; the EVEN output will continue to reflect the state immediately preceding the shut down command. herefore, if the state of the EVEN output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the. his may require clearing the event, disabling the EVEN output or perhaps changing the EVEN output polarity. In normal use, events are triggered by a change in recorded temperature, but the will also respond to limit register changes. Whereas recorded temperature values are updated at sampling rate frequency, limits can be modified at any time. he enabled EVEN output will react to limit changes as soon as the respective registers are updated. his feature may be useful during testing. 17

18 EMEUE IIL UE LM WINDOW LOWE HYEEI FFE HEE I OIN /W LE EVEN IME EVEN IN INEU EVEN IN OMO MODE EVEN IN IIL EM ONLY MODE *EVEN cannot be cleared once the DU temperature is greater than the critical temperature Figure 33. Event Detail H H HY L L HY BELOW WINDOW BI BOVE WINDOW BI Figure 34. Hysteresis Detail 18

19 GE DIMENION DFN8, 2x3 E 511 IUE D e b E E2 IN#1 IDENIFIION IN#1 INDEX E 1 D2 L O VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX EF b D D FON VIEW E E e. Y L Notes: (1) ll dimensions are in millimeters. (2) omplies with JEDE MO

20 Example of Ordering Information Device Order Number V2G4B (Not recommended for new designs.) pecific Device Marking ackage ype Lead Finish hipping GB DFN 8 Nidu ape & eel, 4, Units / eel V2G4 G DFN 8 Nidu ape & eel, 4, Units / eel Device evision 2. ll packages are oh compliant (Lead free, Halogen free) 21. he standard lead finish is Nidu. 22. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and eel ackaging pecifications Brochure, BD811/D. B ON emiconductor is licensed by hilips orporation to carry the I 2 Bus rotocol. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ODEING INFOMION LIEUE FULFILLMEN: Literature Distribution enter for ON emiconductor.o. Box 5163, Denver, olorado 8217 U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter hone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales epresentative /D