CAT5270. Dual Digitally Programmable Potentiometers (DPP) with 256 Taps & I 2 C Compatible Interface

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5270 ual igitally rogrammable otentiometers () with 256 aps & 2 ompatible nterface escription he 5270 is a volatile 256 tap by two channels, digitally programmable potentiometer () with an 2

1 5270 ual igitally rogrammable otentiometers () with 256 aps & 2 ompatible nterface escription he 5270 is a volatile 256 tap by two channels, digitally programmable potentiometer () with an 2 compatible interface. Each consists of a linear taper series of resistive elements connected between two externally accessible end points. he tap points between each resistive element are connected to the wiper outputs with M switches. n power up the wiper position goes to mid scale. he 5270 can be used as a potentiometer or as a two terminal, variable resistor. t is available in a 14 lead package operating over the industrial temperature range ( 40 to 85 ). Features wo Linear aper igitally rogrammable otentiometers 256 esistor aps per otentiometer End to End esistance 50 k, 100 k 2 ompatible nterface Low Wiper esistance 75 (typ.) 2.5 V to 5.5 V peration tandby urrent Less than 1 ower n to Mid cale 14 lead ackage ndustrial emperature ange H0 H1 0 V L H W 2 1 N NNEN ENG NFMN ee detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet Y UFFX E 948M 14 (Y) (op View) 3 L GN W1 H1 L1 1 L 2 M- BLE NEFE 256 N EE NL W0 W NL LG L0 L1 Figure 1. Functional iagram emiconductor omponents ndustries, LL, 2012 May, 2012 ev. 4 1 ublication rder Number: 5270/

2 5270 in escription L: erial lock he 5270 serial clock input pin is used to clock all data transfers into or out of the device. : erial ata he 5270 bidirectional serial data pin is used to transfer data into and out of the device. he pin is an open drain output and can be wire d with the other open drain or open collector /s. 0, 1, 2, 3: evice ddress nputs hese inputs set the device address when addressing multiple devices. total of sixteen devices can be addressed on a single bus. match in the slave address must be made with the address input in order to initiate communication with the H, L : esistor End oints he two sets of H and L pins are equivalent to the terminal connections on a mechanical potentiometer. W : Wiper he W pins are equivalent to the wiper terminal of a mechanical potentiometer. evice peration he 5270 is two resistor arrays integrated with an 2 compatible interface and two 8 bit wiper control registers. Each resistor array contains 255 separate resistive elements connected in series. he physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer ( H and L ). he tap positions between and at the ends of the series resistors are connected to the output able 1. N EN in # 14 Name Function 1 0 evice ddress, LB 2 V upply Voltage 3 L0 Low eference erminal for otentiometer 0 4 H0 High eference erminal for otentiometer 0 5 W0 Wiper erminal for otentiometer evice ddress 7 erial ata nput/utput 8 1 evice ddress 9 L1 Low eference erminal for otentiometer 1 10 H1 High eference erminal for otentiometer 1 11 W1 Wiper erminal for otentiometer 1 12 GN Ground 13 L Bus erial lock 14 3 evice ddress wiper terminals ( W ) by a M transistor switch. nly one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. ata can be read or written to the wiper control register via the 2 compatible interface. lso, the device can be instructed to operate in an increment/ decrement mode. 2

3 5270 able 2. BLUE MXMUM NG arameters atings Units emperature Under Bias 55 to +125 torage emperature 65 to +150 Voltage on ny in with espect to V (Note 1) 2.0 to +V V V with espect to Ground 2.0 to +6.0 V ackage ower issipation apability ( = 25 ) 1.0 W Lead oldering emperature (10 sec) 300 Wiper urrent ±6 m tresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended perating onditions is not implied. Extended exposure to stresses above the ecommended perating onditions may affect device reliability. 1. he minimum input voltage is 0.5 V. uring transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns. able 3. EMMENE ENG NN arameters atings Units V +2.5 to +5.5 V ndustrial emperature 40 to +85 able 4. ENMEE HE (V = +2.5 V to +5.5 V, unless otherwise specified.) ymbol arameter est onditions Limits Min yp Max otentiometer esistance (100 k ) 100 k otentiometer esistance (50 k ) 50 k otentiometer esistance olerance ±20 % Matching 1 % ower ating 25, each pot 50 mw W Wiper urrent ±3 m W Wiper esistance W = ±3 V = 3 V W Wiper esistance W = ±3 V = 5 V V EM Voltage on any H or L in V = 0 V V V V esolution 0.4 % bsolute Linearity (Note 4) w(n)(actual) (n)(expected) (Note 7) ±1 LB (Note 6) elative Linearity (Note 5) w(n+1) [w(n)+lb] (Note 7) ±0.2 LB (Note 6) emperature oefficient of (Note 3) ±100 ppm/ atiometric emp. oefficient (Note 3) 20 ppm/ H / L / W otentiometer apacitances (Note 3) 10/10/25 pf fc Frequency esponse = 50 k (Note 3) 0.4 MHz 2. Latch up protection is provided for stresses up to 100 m on address and data pins from 1 V to V +1 V. 3. his parameter is tested initially and after a design or process change that affects the parameter. 4. bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. t is a measure of the error in step size. 6. LB = / 255 or ( H L ) / 255, single pot 7. n = 0, 1, 2,..., 255 Units 3

4 5270 able 5. ENG HE (V = +2.5 V to +5.5 V, unless otherwise specified.) ymbol arameter est onditions Min Max Units ower upply urrent f L = 400 khz, = pen V = 5.5 V, nputs = GN 1 m B tandby urrent (V = 5.0 V) V N = GN or V, = pen 5 L nput Leakage urrent V N = GN to V 10 L utput Leakage urrent V U = GN to V 10 V L nput Low Voltage 1 V x 0.3 V V H nput High Voltage V x 0.7 V V V L1 utput Low Voltage (V = 2.5 V) L = 3 m 0.4 V able 6. NE ( = 25, f = 1.0 MHz, V = 5 V) ymbol est onditions Max Units / (Note 8) nput/utput apacitance () V / = 0 V 8 pf N (Note 8) nput apacitance (0, 1, 2, 3, L, W) V N = 0 V 6 pf able 7. HE 2.5 V 5.5 V ymbol arameter Min Max Units f L lock Frequency 400 khz (Note 8) Noise uppression ime onstant at L, nputs 200 ns t L Low to ata ut and ut 1 s t BUF (Note 8) ime the bus must be free before a new transmission can start 1.2 s t H: tart ondition Hold ime 0.6 s t LW lock Low eriod 1.2 s t HGH lock High eriod 0.6 s t U: tart ondition etup ime (for a epeated tart ondition) 0.6 s t H: ata in Hold ime 0 ns t U: ata in etup ime 50 ns t (Note 8) and L ise ime 0.3 s t F (Note 8) and L Fall ime 300 ns t U: top ondition etup ime 0.6 s t H ata ut Hold ime 100 ns able 8. WE U MNG (Notes 8 and 9) ymbol arameter Max Units t U ower up to ead peration 1 ms t UW ower up to Write peration 1 ms able 9. WE MNG ymbol arameter Max Units t W Wiper esponse ime fter ower upply table 10 s t WL Wiper esponse ime fter nstruction ssued 10 s 8. his parameter is tested initially and after a design or process change that affects the parameter. 9. t U and t UW are delays required from the time V is stable until the specified operation can be initiated. 4

5 5270 t F t HGH t t LW t LW L t U: t H: t H: t U: t U: N t th t BUF U Figure 2. Bus iming erial Bus rotocol he following defines the features of the 2 compatible interface protocol: 1. ata transfer may be initiated only when the bus is not busy. 2. uring a data transfer, the data line must remain stable whenever the clock line is high. ny changes in the data line while the clock is high will be interpreted as a or condition. he device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, the 5270 will be considered a slave device in all applications. ondition he ondition precedes all commands to the device, and is defined as a HGH to LW transition of when L is HGH (see Figure 3). he 5270 monitors the and L lines and will not respond until this condition is met. ondition LW to HGH transition of when L is HGH determines the condition (see Figure 3). ll operations must end with a condition. evice ddressing he bus Master begins a transmission by sending a condition. he Master then sends the lave ddres Byte which contains the address of the particular slave device it is requesting. he four most significant bits of the 8 bit slave address are fixed as 0101 for the he next four significant bits (3, 2, 1, 0) are the device address bits and define which device the Master is accessing (see Figure 5). Up to sixteen devices may be individually addressed by the system. ypically, +5 V (V ) and ground are hard wired to these pins to establish the device s address. fter the Master sends a condition and the slave address byte, the 5270 monitors the bus and responds with an acknowledge (on the line) when its address matches the transmitted slave address. lave ddress Byte he most significant four bits of the slave address are a device type identifier. hese bits for the 5270 are fixed at 0101[B] (refer to Figure 5). he next four bits, 3 0, are the internal slave address and must match the physical device address which is defined by the state of the 3 0 input pins for the 5270 to successfully continue the command sequence. nly the device which slave address matches the incoming device address sent by the master executes the instruction. he 3 0 inputs can be actively driven by M input signals or tied to V or V. cknowledge fter a successful data transfer, each receiving device is required to generate an acknowledge. he cknowledging device pulls down the line during the ninth clock cycle, signaling that it received the 8 bits of data (see Figure 4). he 5270 responds with an acknowledge after receiving a condition and its slave address. f the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 bit byte. When the 5270 is in a E mode it transmits 8 bits of data, releases the line, and monitors the line for an acknowledge. nce it receives this acknowledge, the 5270 will continue to transmit data. f no acknowledge is sent by the Master, the device terminates data transmission and waits for a condition. f the device has been selected with an N/E operation it will no longer responds with acknoleadge as the received data it is not in a byte format. 5

6 5270 L NN NN Figure 3. tart/top ondition L FM ME UU FM NME UU FM EEVE Figure 4. cknowledge ondition NWLEGE evice ype dentifier lave ddress (MB) (LB) Figure 5. dentification Format for lave ddress Byte 6

7 5270 nstruction and egister escription nstruction Byte he next byte sent to the 5270 contains the instruction and register pointer information. he four most significant bits used provide the instruction opcode 3 0. nstructions nstructions are three bytes in length. hese instructions are: ead Wiper ontrol egister read the current wiper position of the selected potentiometer in the W Write Wiper ontrol egister change current wiper position in the W of the selected potentiometer ncrement/ecrement Wiper ontrol egister change step by step the current wiper position in the W of the selected potentiometer he basic sequence of the three byte instructions is illustrated in Figure 8. Write peration n the Write mode, the Master device sends the condition and the slave address information to the lave device. fter the lave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of he instruction byte consists of a seven bit opcode followed by pot/register selection bit. fter receiving another acknowledge from the lave, the Master device transmits the data to be written into the selected register. he 5270 acknowledges once more and the Master generates the condition. nstruction pcode ncrement/ecrement ommand he last command is ncrement/ecrement (Figures 9 and 10). he ncrement/ecrement command is different from the other commands. nce the instruction is issued and the 5270 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each L clock pulse (t HGH ) while is HGH, the selected wiper will move one resistor segment towards the H terminal. imilarly, for each L clock pulse while is LW, the selected wiper will move one resistor segment towards the L terminal. ee nstructions format for more details. Wiper ontrol egister (W) he 5270 contains two 8 bit Wiper ontrol egisters, one for each potentiometer. he Wiper ontrol egister output is decoded to select one of 256 switches along its resistor array. he contents of the W can be altered in two ways: it may be written by the host via Write Wiper ontrol egister instruction; or it can be modified one step at a time by the ncrement/decrement instruction (see nstruction section for more details). W 0 et 0 wiper position 1 et 1 wiper position he Wiper ontrol egister is a volatile register that loses its contents when the 5270 is powered down. Upon power up, the wiper is set to midspan and may be repositioned anytime after the power has become stable. W ot elector (MB) (LB) Figure 6. nstruction Byte Format able 10. NUN E nstruction nstruction et (Note 10) F2 F1 F0 W/ peration ead Wiper ontrol egister /0 ead the contents of the Wiper ontrol egister pointed to by Write Wiper ontrol egister /0 Write new value to the Wiper ontrol egister pointed to by ncrement/ecrement Wiper ontrol egister 10.1/0 = data is one or zero /0 Enable ncrement/decrement of the ontrol Latch pointed to by 7

8 evice F2 F1 F0 nternal ddress nstruction pcode Fixed ot/w W[7:0] Figure 7. Write nstruction equence evice F2 F1 F0 nternal ddress nstruction pcode Fixed ot/w Figure 8. ead nstruction equence ata egister [7:0] evice F2 F1 F0 nternal ddress nstruction pcode Fixed ot/w N 1 N2 Nn E1 En Figure 9. ncrement/ecrement nstruction equence No Fixed Length N/E ommand ssued L t WL W Voltage ut Figure 10. ncrement/ecrement iming Limits nstruction Format ead Wiper ontrol egister (W) EVE EE NUN Write Wiper ontrol egister (W) EVE EE NUN ncrement ()/ecrement () Wiper ontrol egister (W) EVE EE NUN / /... / / 8

9 5270 ENG NFMN art Number esistance Lead Finish ackage hipping 5270Y 50 G2 50 k Nidu Y 00 G2 100 k (b Free) 2000 / ape & eel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and eel ackaging pecifications Brochure, B8011/. 11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the N emiconductor evice Nomenclature document, N310/, available at ll packages are oh compliant (b Free, Halogen Free). 9

10 5270 GE MENN b 14, 4.4x5 E 948M 01 UE YMBL MN NM MX b E1 E c E E e 0.65 B L 1.00 EF L1 θ º 8º N#1 ENFN VEW e 2 θ1 E VEW 1 EN VEW L1 L Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEE M-153. N emiconductor and are registered trademarks of emiconductor omponents ndustries, LL (LL). LL reserves the right to make changes without further notice to any products herein. LL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does LL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in LL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. LL does not convey any license under its patent rights nor the rights of others. LL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the LL product could create a situation where personal injury or death may occur. hould Buyer purchase or use LL products for any such unintended or unauthorized application, Buyer shall indemnify and hold LL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that LL was negligent regarding the design or manufacture of the part. LL is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLN ENG NFMN LEUE FULFLLMEN: Literature istribution enter for N emiconductor.. Box 5163, enver, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter hone: N emiconductor Website: rder Literature: For additional information, please contact your local ales epresentative 5270/

CAT5259. Quad Digital Potentiometer (POT) with 256 Taps and I 2 C Interface

CAT5259. Quad Digital Potentiometer (POT) with 256 Taps and I 2 C Interface 5259 Quad Digital otentiometer () with 256 aps and I 2 Interface Description he 5259 is four digital s integrated with control logic and 16 bytes of NVM memory. Each digital consists of a series of resistive