CAT5221. Dual Digital Potentiometer (POT) with 64 Taps and I 2 C Interface

Transcription

1 5221 Dual Digital otentiometer () with 64 aps and I 2 Interface Description he 5221 is two digital s integrated with control logic and 16 bytes of NVM memory. Each digital consists of a series of 63 resistive elements connected between two externally accessible end points. he tap points between each resistive element are connected to the wiper outputs with M switches. separate 6-bit control register (W) independently controls the wiper tap switches for each digital. ssociated with each wiper control register are four 6-bit non-volatile memory data registers (D) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a I 2 serial bus. n power-up, the contents of the first data register (D0) for each of the four potentiometers is automatically loaded into its respective wiper control register (W). he 5221 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. Features wo Linear-taper Digital otentiometers 64 esistor aps per otentiometer End to End esistance 2.5 k, 10 k, 50 k or 100 k otentiometer ontrol and Memory ccess via I 2 Interface Low Wiper esistance, ypically 80 Nonvolatile Memory torage for Up to Four Wiper ettings for Each otentiometer utomatic ecall of aved Wiper ettings at ower Up 2.5 to 6.0 Volt peration tandby urrent less than 1 1,000,000 Nonvolatile WIE ycles 100 Year Nonvolatile Memory Data etention 20-lead I and ackages Industrial emperature ange hese Devices are b-free, Halogen Free/BF Free and are oh ompliant W0 L0 H0 0 2 W1 L1 H1 D GND 20 Y UFFIX E 948Q I 20 W UFFIX E 751BJ IN NNEIN I 20 (W) 20 (Y) (op View) V N N N 1 3 L N N N DEING INFMIN ee detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. emiconductor omponents Industries, LL, 2013 July, 2013 ev ublication rder Number: 5221/D

2 5221 (I 20) MING DIGM ( 20) L3B 5221W YMXXXX LB 5221YI 3YMXXX L = ssembly Location 3 = Lead Finish Matte in B = roduct evision (Fixed as B ) = Fixed a 5221W = Device ode = emperature ange I = Industrial = utomobile E = Extended B = Leave blank if ommercial = Dash = esistance 25 = 2.5 hms 10 = 10 hms 50 = 50 hms 00 = 100 hms Y = roduction Year (Last Digit) M = roduction Month (1 9,, N, D) XXXX = Last Four Digits of ssembly Lot Number = esistance 5 = 100 hms 4 = 50 hms 2 = 10 hms 1 = 2.5 hms L = ssembly Location B = roduct evision (Fixed as B ) 5221Y = Device ode I = emperature ange (I = Industrial) 3 = Lead Finish Matte in Y = roduction Year (Last Digit) M = roduction Month (1 9,, N, D) XXX = Last hree Digits of ssembly Lot Number H0 H1 L D I 2 INEFE WIE NL EGIE W0 W NL LGI NNVLILE D EGIE L0 L1 Figure 1. Functional Diagram 2

3 5221 able 1. IN DEIIN in (I) Name Function 1 W0 Wiper erminal for otentiometer 0 2 L0 Low eference erminal for otentiometer 0 3 H0 High eference erminal for otentiometer Device ddress, LB 5 2 Device ddress 6 W1 Wiper erminal for otentiometer 1 7 L1 Low eference erminal for otentiometer 1 8 H1 High eference erminal for otentiometer 1 9 D erial Data Input/utput 10 GND Ground 11 N No onnect 12 N No onnect 13 N No onnect 14 L Bus erial lock 15 3 Device ddress 16 1 Device ddress 17 N No onnect 18 N No onnect 19 N No onnect 20 V upply Voltage IN DEIIN L: erial lock he 5221 serial clock input pin is used to clock all data transfers into or out of the device. D: erial Data he 5221 bidirectional serial data pin is used to transfer data into and out of the device. he D pin is an open drain output and can be wire-r d with the other open drain or open collector outputs. 0, 1, 2, 3: Device ddress Inputs hese inputs set the device address when addressing multiple devices. total of sixteen devices can be addressed on a single bus. match in the slave address must be made with the address input in order to initiate communication with the H, L : esistor End oints he two sets of H and L pins are equivalent to the terminal connections on a mechanical potentiometer. W : Wiper he two W pins are equivalent to the wiper terminal of a mechanical potentiometer. DEVIE EIN he 5221 is two resistor arrays integrated with I 2 serial interface logic, two 6-bit wiper control registers and eight 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. he physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer ( H and L ). H and L are symmetrical and may be interchanged. he tap positions between and at the ends of the series resistors are connected to the output wiper terminals ( W ) by a M transistor switch. nly one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the I 2 bus. dditional instructions allow data to be transferred between the wiper control registers and each respective potentiometer s non-volatile data registers. lso, the device can be instructed to operate in an increment/ decrement mode. 3

4 5221 able 2. BLUE MXIMUM ING arameter atings Units emperature Under Bias 55 to +125 torage emperature 65 to +150 Voltage on any in with espect to V (Note 1) 2.0 to +V +2.0 V V with espect to Ground 2.0 to +7.0 V ackage ower Dissipation apability ( = 25 ) 1.0 W Lead oldering emperature (10 s) 300 Wiper urrent 12 m tresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended perating onditions is not implied. Extended exposure to stresses above the ecommended perating onditions may affect device reliability. able 3. EMMENDED EING NDIIN (V cc = +2.5 V to +6 V) arameter atings Units perating mbient emperature (Industrial) 40 to +85 able 4. ENIMEE HEII (ver recommended operating conditions unless otherwise stated.) ymbol arameter est onditions Min yp Max Units otentiometer esistance ( 00) 100 k otentiometer esistance ( 50) 50 k otentiometer esistance ( 10) 10 k otentiometer esistance ( 2.5) 2.5 k otentiometer esistance olerance 20 % Matching 1 % ower ating 25, each pot 50 mw I W Wiper urrent 6 m W Wiper esistance I W = +3 V = 3 V 300 W Wiper esistance I W = +3 V = 5 V V EM Voltage on any H or L in V = 0 V GND V V N Noise (Note 3) BD nv/ Hz esolution 1.6 % bsolute Linearity (Note 4) W(n)(actual) (n)(expected) (Note 7) 1 LB (Note 6) elative Linearity (Note 5) W(n+1) [ W(n)+LB ] (Note 7) 0.2 LB (Note 6) emperature oefficient of (Note 3) 300 ppm/ I atiometric emp. oefficient (Note 3) 20 ppm/ H / L / W otentiometer apacitances (Note 3) 10/10/25 pf fc Frequency esponse = 50 k 0.4 MHz 1. he minimum D input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum D voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns. 2. Latch-up protection is provided for stresses up to 100 m on address and data pins from 1 V to V + 1 V. 3. his parameter is tested initially and after a design or process change that affects the parameter. 4. bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 6. LB = / 63 or ( H L ) / 63, single pot 7. n = 0, 1, 2,..., 63 4

5 5221 able 5. D.. EING HEII (ver recommended operating conditions unless otherwise stated.) ymbol arameter est onditions Min yp Max Units I ower upply urrent f L = 400 khz 1 m I B tandby urrent (V = 5.0 V) V IN = GND or V ; D pen 1 I LI Input Leakage urrent V IN = GND to V 10 I L utput Leakage urrent V U = GND to V 10 V IL Input Low Voltage 1 V x 0.3 V V IH Input High Voltage V x 0.7 V V V L1 utput Low Voltage (V = 3.0 V) I L = 3 m 0.4 V able 6. INE ( = 25, f = 1.0 MHz, V = 5 V) ymbol arameter est onditions Min yp Max Units I/ (Note 8) Input/utput apacitance (D) V I/ = 0 V 8 pf IN (Note 8) Input apacitance (0, 1, 2, 3, L) V IN = 0 V 6 pf able 7... HEII (ver recommended operating conditions unless otherwise stated.) ymbol arameter Min yp Max Units f L lock Frequency 400 khz I (Note 8) Noise uppression ime onstant at L, D Inputs 50 ns t L Low to D Data ut and ut 0.9 s t BUF (Note 8) ime the Bus Must Be Free Before a New ransmission an tart 1.2 s t HD: tart ondition Hold ime 0.6 s t LW lock Low eriod 1.2 s t HIGH lock High eriod 0.6 s t U: tart ondition etup ime (For a epeated tart ondition) 0.6 s t HD:D Data in Hold ime 0 ns t U:D Data in etup ime 100 ns t (Note 8) D and L ise ime 0.3 s t F (Note 8) D and L Fall ime 300 ns t U: top ondition etup ime 0.6 s t DH Data ut Hold ime 50 ns able 8. WE U IMING (Note 8) (ver recommended operating conditions unless otherwise stated.) ymbol arameter Min yp Max Units t U ower-up to ead peration 1 ms t UW ower-up to Write peration 1 ms 8. his parameter is tested initially and after a design or process change that affects the parameter. able 9. WIE YLE LIMI (ver recommended operating conditions unless otherwise stated.) ymbol arameter Min yp Max Units t W Write ycle ime 5 ms NE: he write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, D is allowed to remain high, and the device does not respond to its slave address. 5

6 5221 able 10. ELIBILIY HEII (ver recommended operating conditions unless otherwise stated.) ymbol arameter eference est Method Min yp Max Units NEND (Note 9) Endurance MIL D 883, est Method ,000,000 ycles/byte D (Note 9) Data etention MIL D 883, est Method Years VZ (Note 9) ED usceptibility MIL D 883, est Method Volts ILH (Notes 9, 10) Latch-Up JEDE tandard m 9. his parameter is tested initially and after a design or process change that affects the parameter. 10.t U and t UW are the delays required from the time V is stable until the specified operation can be initiated. t F t HIGH t t LW t LW L t U: t HD: t HD:D tu:d t U: D IN t t DH t BUF D U Figure 2. Bus iming L D 8H BI BYE n t W NDIIN NDIIN DDE Figure 3. Write ycle iming D L BI Figure 4. tart/top iming BI 6

7 5221 EIL BU L he following defines the features of the I 2 bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. ny changes in the data line while the clock is high will be interpreted as a or condition. he device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, the 5221 will be considered a slave device in all applications. ondition he ondition precedes all commands to the device, and is defined as a HIGH to LW transition of D when L is HIGH. he 5221 monitors the D and L lines and will not respond until this condition is met. ondition LW to HIGH transition of D when L is HIGH determines the condition. ll operations must end with a condition. Device ddressing he bus Master begins a transmission by sending a condition. he Master then sends the address of the particular slave device it is requesting. he four most significant bits of the 8-bit slave address are fixed as 0101 for the 5221 (see Figure 6). he next four significant bits (3, 2, 1, 0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. ypically, +5 V and ground are hard-wired to these pins to establish the device s address. fter the Master sends a condition and the slave address byte, the 5221 monitors the bus and responds with an acknowledge (on the D line) when its address matches the transmitted slave address. cknowledge fter a successful data transfer, each receiving device is required to generate an acknowledge. he cknowledging device pulls down the D line during the ninth clock cycle, signaling that it received the 8 bits of data. he 5221 responds with an acknowledge after receiving a condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the 5221 is in a ED mode it transmits 8 bits of data, releases the D line, and monitors the line for an acknowledge. nce it receives this acknowledge, the 5221 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a condition. L FM ME D UU FM NMIE D UU FM EEIVE Figure 5. cknowledge iming NWLEDGE WIE EIN In the Write mode, the Master device sends the condition and the slave address information to the lave device. fter the lave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of he instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. fter receiving another acknowledge from the lave, the Master device transmits the data to be written into the selected register. he 5221 acknowledges once more and the Master generates the condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. cknowledge olling he disabling of the inputs can be used to take advantage of the typical write cycle time. nce the stop condition is issued to indicate the end of the host s write operation, the 7

8 initiates the internal write cycle. polling can be initiated immediately. his involves issuing the start condition followed by the slave address. If the 5221 is still busy with the write operation, no will be returned. If the 5221 has completed the write operation, an will be returned and the host can then proceed with the next instruction operation * 0, 1, 2 and 3 correspond to pin 0, 1, 2 and 3 of the device. ** 0, 1, 2 and 3 must compare to its corresponding hard wired input pins. Figure 6. lave ddress Bits LVE DDE INUIN BYE BU IVIY: ME Fixed Variable op code ot/w ddress Data egister ddress D W D D LINE Figure 7. Write iming INUIN ND EGIE DEIIN Instructions lave ddress Byte he first byte sent to the 5221 from the master/ processor is called the lave ddress Byte. he most significant four bits of the slave address are a device type identifier. hese bits for the 5221 are fixed at 0101[B] (refer to Figure 8). he next four bits, 3 0, are the internal slave address and must match the physical device address which is defined by the state of the 3 0 input pins for the 5221 to successfully continue the command sequence. nly the device which slave address matches the incoming device address sent by the master executes the instruction. he 3 0 inputs can be actively driven by M input signals or tied to V or V. Device ype Identifier Instruction Byte he next byte sent to the 5221 contains the instruction and register pointer information. he four most significant bits used provide the instruction opcode I [3:0]. he 0 bit points to one of the Wiper ontrol egisters. he least two significant bits, 1 and 0, point to one of the four data registers of each associated potentiometer. he format is shown in Figure 9. able 11. D EGIE ELEIN Data egister elected 1 0 D0 0 0 D1 0 1 D2 1 0 D3 1 1 lave ddress ID3 ID2 ID1 ID (MB) (LB) Figure 8. Identification Byte Format Instruction pcode W/ot election Data egister election I3 I2 I1 I (MB) (LB) Figure 9. Instruction Byte Format 8

9 5221 WIE NL ND D EGIE Wiper ontrol egister (W) he 5221 contains two 6-bit Wiper ontrol egisters, one for each potentiometer. he Wiper ontrol egister output is decoded to select one of 64 switches along its resistor array. he contents of the W can be altered in four ways: it may be written by the host via Write Wiper ontrol egister instruction; it may be written by transferring the contents of one of four associated Data egisters via the XF Data egister instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (D0) upon power-up. he Wiper ontrol egister is a volatile register that loses its contents when the 5221 is powered-down. lthough the register is automatically loaded with the value in D0 upon power-up, this may be different from the value present at power-down. Data egisters (D) Each potentiometer has four 6-bit non-volatile Data egisters. hese can be read or written directly by the host. Data can also be transferred between any of the four Data egisters and the associated Wiper ontrol egister. ny data changes in one of the Data egisters is a non-volatile operation and will take a maximum of 5 ms. If the application does not require storage of multiple settings for the potentiometer, the Data egisters can be used as standard memory locations for system parameters or user preference data. Instructions Four of the nine instructions are three bytes in length. hese instructions are: ead Wiper ontrol egister read the current wiper position of the selected potentiometer in the W Write Wiper ontrol egister change current wiper position in the W of the selected potentiometer ead Data egister read the contents of the selected Data egister Write Data egister write a new value to the selected Data egister able 12. INUIN E Instruction I3 I2 I1 I0 0 Instruction et W0/ peration ead Wiper ontrol egister /0 0 0 ead the contents of the Wiper ontrol egister pointed to by 0 Write Wiper ontrol egister /0 0 0 Write new value to the Wiper ontrol egister pointed to by 0 ead Data egister /0 1/0 1/0 ead the contents of the Data egister pointed to by 0 and 1 0 Write Data egister /0 1/0 1/0 Write new value to the Data egister pointed to by 0 and 1 0 XF Data egister to Wiper ontrol egister XF Wiper ontrol egister to Data egister Global XF Data egisters to Wiper ontrol egisters Global XF Wiper ontrol egisters to Data egister Increment/Decrement Wiper ontrol egister /0 1/0 1/0 ransfer the contents of the Data egister pointed to by 0 and 1 0 to its associated Wiper ontrol egister /0 1/0 1/0 ransfer the contents of the Wiper ontrol egister pointed to by 0 to the Data egister pointed to by /0 1/0 ransfer the contents of the Data egisters pointed to by 1 0 of all four pots to their respective Wiper ontrol egisters /0 1/0 ransfer the contents of both Wiper ontrol egisters to their respective data egisters pointed to by 1 0 of all four pots /0 0 0 Enable Increment/decrement of the ontrol Latch pointed to by 0 NE: 1/0 = data is one or zero he basic sequence of the three byte instructions is illustrated in Figure 11. hese three-byte instructions exchange data between the W and one of the Data egisters. he W controls the position of the wiper. he response of the wiper to this action will be delayed by t WL. transfer from the W (current wiper position), to a Data egister is a write to non-volatile memory and takes a maximum of t W to complete. he transfer can occur 9

10 5221 between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 10. hese instructions transfer data between the host/processor and the 5221; either between the host and one of the data registers or directly between the host and the Wiper ontrol egister. hese instructions are: XF Data egister to Wiper ontrol egister his transfers the contents of one specified Data egister to the associated Wiper ontrol egister. XF Wiper ontrol egister to Data egister his transfers the contents of the specified Wiper ontrol egister to the specified associated Data egister. Global XF Data egister to Wiper ontrol egister his transfers the contents of all specified Data egisters to the associated Wiper ontrol egisters. Global XF Wiper ounter egister to Data egister his transfers the contents of all Wiper ontrol egisters to the specified associated Data egisters. Increment/Decrement ommand he final command is Increment/Decrement (Figures 6 and 12). he Increment/Decrement command is different from the other commands. nce the command is issued and the 5221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each L clock pulse (t HIGH ) while D is HIGH, the selected wiper will move one resistor segment towards the H terminal. imilarly, for each L clock pulse while D is LW, the selected wiper will move one resistor segment towards the L terminal. ee Instructions format for more detail. D ID3 ID2 ID1 ID I3 I2 I1 I Device ID Internal Instruction ot/w egister ddress pcode ddress ddress Figure 10. wo-byte Instruction equence D ID3 ID2 ID1 ID Device ID Internal Instruction ddress pcode I3 I2 I1 I ot/w ddress Data egister ddress D7 D6 D5 D4 D3 D2 W[7:0] or Data egister D[7:0] D1 D0 Figure 11. hree-byte Instruction equence D ID3 ID2 ID1 ID I3 I2 I1 I0 Device ID Internal Instruction ddress pcode ot/w ddress Data egister ddress Figure 12. Increment/Decrement Instruction equence I N 1 I N2 I Nn D E1 D E n 10

11 5221 IN/DE ommand Issued t WID L D W Voltage ut Figure 13. Increment/Decrement iming Limits INUIN FM able 13. ED WIE NL EGIE (W) DEVIE DDEE INUIN D able 14. WIE WIE NL EGIE (W) DEVIE DDEE INUIN D able 15. ED D EGIE (D) DEVIE DDEE INUIN D able 16. WIE D EGIE (D) DEVIE DDEE INUIN D able 17. GLBL NFE D EGIE (D) WIE NL EGIE (W) DEVIE DDEE INUIN

12 5221 able 18. GLBL NFE WIE NL EGIE (W) D EGIE (D) DEVIE DDEE INUIN able 19. NFE WIE NL EGIE (W) D EGIE (D) DEVIE DDEE INUIN able 20. NFE D EGIE (D) WIE NL EGIE (W) DEVIE DDEE INUIN able 21. INEMEN (I)/DEEMEN (D) WIE NL EGIE (W) DEVIE DDEE INUIN D I/D I/D... I/D I/D NE: ny write or transfer to the Non-volatile Data egisters is followed by a high voltage cycle after a has been issued. 12

13 5221 able 22. DEING INFMIN rderable art Number esistance (k ) Lead Finish ackage hipping 5221WI WI WI WI YI YI YI YI WI WI WI WI YI YI YI YI Matte in I (b Free) (b Free) I (b Free) (b Free) 1000 / ape & eel 2000 / ape & eel 36 Units / ube 74 Units / ube For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and eel ackaging pecifications Brochure, BD8011/D. 11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the N emiconductor Device Nomenclature document, ND310/D, available at ll packages are oh-compliant (b-free, Halogen-Free). 13. he standard lead finish is Matte-in. 13

14 5221 GE DIMENIN I 20, 300 mils E 751BJ IUE YMBL MIN NM MX b E1 E c D E E e 1.27 B h b IN#1 IDENIFIIN e L θ 0º 8º θ1 5º 15º VIEW D h h 1 2 IDE VIEW 1 L END VIEW 1 c Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M

15 5221 GE DIMENIN b 20, 4.4x6.5 E 948Q IUE YMBL MIN NM MX E1 E b c D E E e 0.65 B L e L1 θ 1.00 EF 0º 8º VIEW D c 2 θ1 IDE VIEW 1 END VIEW L L1 Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M-153. N emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ILL s product/patent coverage may be accessed at Marking.pdf. ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIIN DEING INFMIN LIEUE FULFILLMEN: Literature Distribution enter for N emiconductor.. Box 5163, Denver, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter hone: N emiconductor Website: rder Literature: For additional information, please contact your local ales epresentative 5221/D