CAT24C256. EEPROM Serial 256-Kb I 2 C

Transcription

1 24256 EEPROM erial 256-b I 2 Description he is a EEPROM erial 256 b I 2, internally organized as 32,768 words of 8 bits each. It features a 64 byte page write buffer and supports the tandard (100 khz), Fast (400 khz) and Fast Plus (1 MHz) I 2 protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). External address pins make it possible to address up to eight devices on the same bus. On hip E (Error orrection ode) makes the device suitable for high reliability applications.* Features upports tandard, Fast and Fast Plus I 2 Protocol 1.8 V to 5.5 V upply Voltage Range 64 Byte Page Write Buffer Hardware Write Protection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low Power MO echnology 1,000,000 Program/Erase ycles 100 Year Data Retention Industrial and Extended emperature Range OI, OP and UDFN 8 Pad Packages his Device is Pb Free, Halogen Free/BFR Free, and RoH ompliant V OI 8 WIDE X UFFIX E 751BE OP 8 Y UFFIX E 948L PIN ONFIGURION V OI 8 X UFFIX E 751BE OI 8 W UFFIX E 751BD V WP L D OI (W, X), OP (Y), UDFN (HU4) For the location of Pin 1, please consult the corresponding package drawing. PIN FUNION UDFN 8 HU4 UFFIX E 517Z L Pin Name 0, 1, 2 Function Device ddress 2, 1, D D L erial Data erial lock WP WP Write Protect V Power upply V Figure 1. Functional ymbol V Ground he exposed pad for the UDFN packages can be left floating or connected to Ground. ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. emiconductor omponents Industries, LL, 2014 May, 2018 Rev Publication Order Number: 24256/D

2 24256 able 1. BOLUE MXIMUM RING Parameters Ratings Units torage emperature 65 to +150 Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. RELIBILIY HRERII (Note 2) ymbol Parameter Min Units N END (Notes 3, 4) Endurance 1,000,000 Program/Erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. Page Mode, V = 5 V, he new product revision (E) uses E (Error orrection ode) logic with 6 E bits to correct one bit error in 4 data bytes. herefore, when a single byte has to be written, 4 bytes (including the E bits) are re programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. able 3. D.. OPERING HRERII Mature Product (Rev D) (V = 2.5 V to 5.5 V, = 40 to +125, and V = 1.8 V to 5.5 V, = 40 to +85, unless otherwise specified.) ymbol Parameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz 1 m I Write urrent Write, f L = 400 khz 3 m I B tandby urrent ll I/O Pins at GND or V = 40 to = 40 to I L I/O Pin Leakage Pin at GND or V = 40 to = 40 to V IL Input Low Voltage 0.5 V x 0.3 V V IH Input High Voltage V x 0.7 V V V OL1 Output Low Voltage V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltage V < 2.5 V, I OL = 1.0 m 0.2 V able 4. PIN IMPEDNE HRERII Mature Product (Rev D) (V = 2.5 V to 5.5 V, = 40 to +125, and V = 1.8 V to 5.5 V, = 40 to +85, unless otherwise specified.) ymbol Parameter onditions Max Units IN (Note 5) D I/O Pin apacitance V IN = 0 V 8 pf IN (Note 5) Input apacitance (other pins) V IN = 0 V 6 pf I WP (Note 6) WP Input urrent V IN < V IH, V = 5.5 V 130 V IN < V IH, V = 3.3 V 120 V IN < V IH, V = 1.8 V 80 V IN > V IH 1 5. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. he variable WP input impedance is available only for Die Rev. and higher. 2

3 24256 able 5. D.. OPERING HRERII New Product (Rev E) (Note 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz/1 MHz 1 m I W Write urrent 3 m I B tandby urrent ll I/O Pins at GND or V = 40 to = 40 to I L I/O Pin Leakage Pin at GND or V = 40 to = 40 to V IL1 Input Low Voltage 2.5 V V 5.5 V V V V IL2 Input Low Voltage 1.8 V V < 2.5 V V V V IH1 Input High Voltage 2.5 V V 5.5 V 0.7 V V V V IH2 Input High Voltage 1.8 V V < 2.5 V 0.75 V V V V OL1 Output Low Voltage V 2.5 V, I OL = 3.0 m 0.4 V V OL2 Output Low Voltage V < 2.5 V, I OL = 1.0 m 0.2 V able 6. PIN IMPEDNE HRERII New Product (Rev E) (Note 7) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter onditions Max Units IN (Note 8) D I/O Pin apacitance V IN = 0 V 8 pf IN (Note 8) Input apacitance (other pins) V IN = 0 V 6 pf I WP, I (Note 9) WP Input urrent, ddress Input V IN < V IH, V = 5.5 V 75 urrent ( 0, 1, 2 ) V IN < V IH, V = 3.3 V 50 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 7. he new product Rev E is identified by letter E or a dedicated marking code on top of the package. 8. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 9. When not driven, the WP, 0, 1, 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 3

4 24256 able 7... HRERII Mature Product (Rev D) (Notes 10, 11) (V = 2.5 V to 5.5 V, = 40 to +125, and V = 1.8 V to 5.5 V, = 40 to +85, unless otherwise specified.) ymbol Parameter tandard Fast Fast Plus V = 2.5 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frequency ,000 khz t HD: R ondition Hold ime s t LOW Low Period of L lock s t HIGH High Period of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime s t U:D Data In etup ime ns t R (Note 12) D and L Rise ime 1, ns t F (Note 12) D and L Fall ime ns t U:O OP ondition etup ime s t BUF Bus Free ime Between OP and R Units s t L Low to Data Out Valid s t DH Data Out Hold ime ns i (Note 12) Noise Pulse Filtered at L and D Inputs ns t U:WP WP etup ime s t HD:WP WP Hold ime s t WR Write ycle ime ms t PU (Notes 12, 13) Power-up to Ready Mode ms 10.he product Rev D is identified by letter D or a dedicated marking code on top of the package. 11. est conditions according to.. est onditions table. 12. ested initially and after a design or process change that affects this parameter. 13.t PU is the delay between the time V is stable and the device is ready to accept commands. Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. able 8... E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource: I L = 3 m (V 2.5 V); I L = 1 m (V < 2.5 V); L = 100 pf 4

5 24256 able 9... HRERII New Product (Rev E) (Notes 14, 15) (V = 1.8 V to 5.5 V, = 40 to +85 and V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter tandard V = 1.8 V 5.5 V Fast V = 1.8 V 5.5 V Fast Plus V = 2.5 V 5.5 V = 40 to +85 Min Max Min Max Min Max F L lock Frequency ,000 khz t HD: R ondition Hold ime s t LOW Low Period of L lock s t HIGH High Period of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime s t U:D Data In etup ime ns t R (Note 16) D and L Rise ime 1, ns t F (Note 16) D and L Fall ime ns t U:O OP ondition etup ime s t BUF Bus Free ime Between OP and R Units s t L Low to Data Out Valid s t DH Data Out Hold ime ns i (Note 16) Noise Pulse Filtered at L and D Inputs ns t U:WP WP etup ime s t HD:WP WP Hold ime s t WR Write ycle ime ms t PU (Notes 16, 17) Power-up to Ready Mode ms 14. est conditions according to.. est onditions table. 15.he New product Rev E is identified by letter E or a dedicated marking code on top of the package. 16. ested initially and after a design or process change that affects this parameter. 17.t PU is the delay between the time V is stable and the device is ready to accept commands. 5

6 24256 Power-On Reset (POR) he Die Rev. incorporates Power On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the POR trigger level and will power down into Reset mode when V drops below the POR trigger level. his bi directional POR behavior protects the device against brown out failure, following a temporary loss of power. Pin Description L: he erial lock input pin accepts the erial lock signal generated by the Master. D: he erial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2 : he ddress pins accept the device address. hese pins have on chip pull down resistors. WP: he Write Protect input pin inhibits all write operations, when pulled HIGH. his pin has an on chip pull down resistor. Functional Description he supports the Inter Integrated ircuit (I 2 ) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all R and OP conditions. he acts as a lave device. Master and lave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs 0, 1, and 2. I 2 Bus Protocol he I 2 bus consists of two wires, L and D. he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the 2 wire bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a R or OP condition (Figure 2). R he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake up call to all receivers. bsent a R, a lave will not respond to commands. OP he OP condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. he OP starts the internal Write cycle (when following a Write command) or sends the lave into standby mode (when following a Read command). Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address are set to 1010, for normal Read/Write operations (Figure 3). he next 3 bits, 2, 1 and 0, select one of 8 possible lave devices. he last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. cknowledge fter processing the lave address, the lave responds with an acknowledge () by pulling down the D line during the 9th clock cycle (Figure 4). he lave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the lave shifts out a data byte, and then releases the D line during the 9th clock cycle. If the Master acknowledges the data, then the lave continues transmitting. he Master terminates the session by not acknowledging the last data byte (No) and by sending a OP to the lave. Bus timing is illustrated in Figure 5. 6

7 24256 L D R ONDIION Figure 2. tart/top iming OP ONDIION R/W DEVIE DDRE Figure 3. lave ddress Bits BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EUP ( t U:D ) t F t HIGH t R t LOW t LOW L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming 7

8 24256 WRIE OPERION Byte Write In Byte Write mode the Master sends a R, followed by lave address, two byte address and data to be written (Figure 6). he lave acknowledges all 4 bytes, and the Master then follows up with a OP, which in turn starts the internal Write operation (Figure 7). During internal Write, the lave will not acknowledge any Read or Write request from the Master. Page Write he contains 32,768 bytes of data, arranged in 512 pages of 64 bytes each. two byte address word, following the lave address, points to the first byte to be written. he most significant bit of the address word is don t care, the next 9 bits identify the page and the last 6 bits identify the byte within the page. Up to 64 bytes can be written in one Write cycle (Figure 8). he internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 64 data bytes, then earlier bytes will be overwritten by later bytes in a wrap around fashion (within the selected page). he internal Write cycle starts immediately following the OP. cknowledge Polling cknowledge polling can be used to determine if the is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a elective Read command (see RED OPERION). he will not acknowledge the lave address, as long as internal Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the he state of the WP pin is strobed on the last falling edge of L immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the will not acknowledge the data byte and the Write request will be rejected. Delivery tate he is shipped erased, i.e., all bytes are FFh. 8

9 24256 BU IVIY: MER R LVE DDRE BYE DDRE D O P D LINE * P * = Don t are Bit Figure 6. Byte Write iming L D 8th Bit Byte n t WR OP ONDIION R ONDIION DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE BYE DDRE D D n D n+63 O P D LINE * P * = Don t are Bit Figure 8. Page Write iming DDRE BYE D BYE L D a 7 a 0 d 7 d 0 t U:WP WP t HD:WP Figure 9. WP iming 9

10 24256 RED OPERION Immediate ddress Read In standby mode, the internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that previous byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a R, the is presented with a lave address containing a 1 in the R/W bit position (Figure 10), it will acknowledge () in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. he Master can stop further transmission by issuing a No, followed by a OP condition. elective Read he Read operation can also be started at an address different from the one stored in the internal address counter. he address counter can be initialized by performing a dummy Write operation (Figure 11). Here the R is followed by the lave address (with the R/W bit set to 0 ) and the desired two byte address. Instead of following up with data, the Master then issues a 2nd R, followed by the Immediate ddress Read sequence, as described earlier. equential Read If the Master acknowledges the 1st data byte transmitted by the 24256, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will wrap around to the beginning of memory, etc. equential Read works with either Immediate ddress Read or elective Read, the only difference being the starting byte address. BU IVIY: MER R LVE DDRE O P D LINE P D N O L 8 9 D 8th Bit D OU NO OP Figure 10. Immediate ddress Read iming BU IVIY: MER R LVE DDRE BYE DDRE R LVE DDRE D O P D LINE * P * = Don t are Bit Figure 11. elective Read iming N O BU IVIY: MER LVE DDRE D n D n+1 D n+2 D n+x O P D LINE P Figure 12. equential Read iming N O 10

11 24256 ORDERING INFORMION Device Order Number Device Marking* 24256WI G E OI 8, JEDE I = Industrial ( 40 to +85 ) 24256XI E OI 8, EIJ I = Industrial ( 40 to +85 ) 24256YI G3 56E OP 8 I = Industrial ( 40 to +85 ) 24256HU4IG3 8U UDFN 8 I = Industrial ( 40 to +85 ) Package ype emperature Range Lead Finish hipping NiPdu Matte in NiPdu NiPdu ape & Reel, 3,000 Units / Reel ape & Reel, 2,000 Units / Reel ape & Reel, 3,000 Units / Reel ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8011/D. 18. ll packages are RoH-compliant (Lead-free, Halogen-free). 19. he standard lead finish is NiPdu. 20. For additional package and temperature options, please contact your nearest ON emiconductor ales office. 21. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8011/D. 22. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON emiconductor Device Nomenclature document, ND310/D, available at ON emiconductor is licensed by Philips orporation to carry the I 2 Bus Protocol. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ILL s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor P.O. Box 5163, Denver, olorado U N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: Phone: or oll Free U/anada Phone: ON emiconductor is licensed by the Philips orporation to carry the I Fax: or oll Free U/anada Japan ustomer bus Focus protocol. enter orderlit@onsemi.com Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative 24256/D

12 MEHNIL E OULINE PGE DIMENION 1 LE 2:1 UDFN8, 2x3 EXENDED PD E 517Z IUE DE 23 MR 2015 PIN ONE REFERENE NOE D ÇÇ ÇÇ OP VIEW DEIL B 1 IDE VIEW B E 3 L1 EXPOED u EING PLNE L DEIL LERNE ONRUION ÉÉ MOLD MPD DEIL B LERNE ONRUION L ÉÉÉ 1 3 NOE: 1. DIMENIONING ND OLERNING PER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DIMENION b PPLIE O PLED ERMINL ND I MEURED BEWEEN 0.15 ND 0.25MM FROM HE ERMINL IP. 4. OPLNRIY PPLIE O HE EXPOED PD WELL HE ERMINL. MILLIMEER DIM MIN MX REF b D 2.00 B D E 3.00 B E e 0.50 B L L GENERI MRING DIGRM* DEIL D2 1 4 L 1 XXXXX WLYW 8 5 e BOOM VIEW E2 8X b 0.10 M 0.05 M B NOE 3 XXXXX = pecific Device ode = ssembly Location WL = Wafer Lot Y = Year W = Work Week = Pb Free Package *his information is generic. Please refer to device data sheet for actual part marking. Pb Free indicator, G or microdot, may or may not be present. REOMMENDED OLDERING FOOPRIN* X PIH 8X 0.30 DIMENION: MILLIMEER *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. DOUMEN NUMBER: 98ON42552E U: ON EMIONDUOR NDRD REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: UDFN8, 2X3 EXENDED PD 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

13 DOUMEN NUMBER: 98ON42552E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #UDFN O ON EMION- 23 JUL 2009 DUOR. REQ. BY B. BERGMN. REDREW PGE DRWING O ON EMIONDUOR/JEDE NDRD. REQ. BY B. BEER. 23 MR 2015 ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2015 March, 2015 Rev. ase Outline Number: 517Z

14 MEHNIL E OULINE PGE DIMENION OI 8, 150 mils E 751BD 01 IUE O DE 19 DE 2008 YMBOL MIN NOM MX b E1 E c D E E e 1.27 B h PIN # 1 IDENIFIION L θ 0º 8º OP VIEW D h 1 θ c e b L IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M-012. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34272E ON EMIONDUOR NDRD OI 8, 150 MIL 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

15 DOUMEN NUMBER: 98ON34272E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OI O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 751BD

16 MEHNIL E OULINE PGE DIMENION OI 8, 208 mils E 751BE 01 IUE O DE 19 DE 2008 E1 E YMBOL MIN NOM MX 1 b c D E E e 1.27 B L θ 0º 8º PIN#1 IDENIFIION OP VIEW D e b 1 L c IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with EIJ EDR DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34273E ON EMIONDUOR NDRD OI 8, 208 MIL 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

17 DOUMEN NUMBER: 98ON34273E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OI O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 751BE

18 MEHNIL E OULINE PGE DIMENION OP8, 4.4x3 E 948L 01 IUE O DE 19 DE 2008 b YMBOL MIN NOM MX b E1 E c D E E e 0.65 B L 1.00 REF L1 θ º 8º e OP VIEW D 2 1 c IDE VIEW 1 L1 END VIEW L Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-153. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34428E ON EMIONDUOR NDRD OP8, 4.4X3 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

19 DOUMEN NUMBER: 98ON34428E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OP O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 948L

20 ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor E. 32nd Pkwy, urora, olorado U Phone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative

21 Mouser Electronics uthorized Distributor lick to View Pricing, Inventory, Delivery & Lifecycle Information: ON emiconductor: 24256LI-G 24256HU4IG YI-G WI-G3