N24C Kb I 2 C CMOS Serial EEPROM

Transcription

1 N b I 2 MO erial EEROM Description he N2432 is a 32 b MO erial EEROM device, organized internally as 128 pages of 32 bytes each. his device supports the tandard (100 khz), Fast (400 khz) and Fast lus (1 MHz) I 2 protocol. Data is written by providing a starting address, then loading 1 to 32 contiguous bytes into a age Write Buffer, and then writing all data to non volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight N2432 devices on the same bus. Features upports tandard, Fast and Fast lus I 2 rotocol 1.7 V / 1.6 V to 5.5 V upply Voltage Range 32 Byte age Write Buffer Fast Write ime (4 ms max) Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low ower MO echnology 1,000,000 rogram/erase ycles 100 Year Data Retention Industrial and utomotive Grade 1 emperature Range U 8 lead ackage hese Devices are b Free, Halogen Free/BFR Free, and RoH ompliant XX M U8 U UFFIX E 493 IN ONFIGURION V U8 (U) (op View) MRING DIGRM 8 XX M V W L D 1 = pecific Device ode* = Date ode = b Free ackage (Note: Microdot may be in either location) * ee Ordering Information section for the pecific Device Marking ode ORDERING INFORMION ee detailed ordering, marking and shipping information in the package dimensions section on page 10 of this data sheet. emiconductor omponents Industries, LL, 2016 June, 2016 Rev. 1 1 ublication Order Number: N2432/D

2 N2432 V IN FUNION in Name Function L 0, 1, 2 D Device ddress erial Data 2, 1, 0 W N2432 D L W V erial lock Write rotect ower upply V Ground V Figure 1. Functional ymbol able 1. BOLUE MXIMUM RING arameters Ratings Units torage emperature 65 to +150 Voltage on ny in with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V V, for periods of less than 20 ns. able 2. RELIBILIY HRERII ymbol arameter Max Units N END (Note 2) Endurance 1,000,000 Write ycles (Note 3) DR (Note 2) Data Retention 100 Years 2. = Write ycle refers to writing a Byte or a age. 2

3 N2432 able 3. D.. OERING HRERII (V = 1.7 V / 1.6 V* to 5.5 V, = 40 to +85 and V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol arameter est onditions Min Max Units I R Read urrent Read, f L = 1 MHz 0.4 m I W Write urrent Write 0.6 m I B tandby urrent ll I/O ins at GND or V = 40 to = 40 to I L I/O in Leakage in at GND or V 2 V IL1 Input Low Voltage 2.2 V V 5.5 V V V V IL2 Input Low Voltage 1.6 V V < 2.2 V V V V IH1 Input High Voltage 2.2 V V 5.5 V 0.7 V V V V IH2 Input High Voltage 1.6 V V < 2.2 V 0.8 V V V V OL1 Output Low Voltage V 2.2 V, I OL = 6.0 m 0.4 V V OL2 Output Low Voltage V < 2.2 V, I OL = 2.0 m 0.2 V roduct parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. roduct performance may not be indicated by the Electrical haracteristics if operated under different conditions. able 4. IN IMEDNE HRERII (V = 1.7 V / 1.6 V* to 5.5 V, = 40 to +85 and V = 1.8 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol arameter onditions Max Units IN (Note 4) D I/O in apacitance V IN = 0 V 8 pf IN (Note 4) Input apacitance (other pins) V IN = 0 V 6 pf I W, I (Note 5) W Input urrent, ddress Input urrent (0, 1, 2) V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 1.8 V 25 V IN > V IH 2 *V (min) = 1.6 V for Read operations, = 20 to hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 5. When not driven, the W, 0, 1 and 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 3

4 N2432 able 5... HRERII (V = 1.7 V / 1.6 V* to 5.5 V, = 40 to +85 and V = 1.8 V to 5.5 V, = 40 to +125 unless otherwise noted.) (Note 6) ymbol arameter tandard Fast Fast lus Min Max Min Max Min Max F L lock Frequency ,000 khz t HD: R ondition Hold ime s t LOW Low eriod of L lock s t HIGH High eriod of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime s t U:D Data In etup ime ns t R (Note 7) D and L Rise ime 1, ns t F (Note 7) D and L Fall ime ns t U:O O ondition etup ime s t BUF Bus Free ime Between O and R Units s t L Low to Data Out Valid s t DH (Note 7) Data Out Hold ime ns i (Note 7) Noise ulse Filtered at L and D Inputs ns t U:W W etup ime s t HD:W W Hold ime s t WR Write ycle ime ms t U (Notes 7, 8) ower-up to Ready Mode ms *V (min) = 1.6 V for Read operations, = 20 to est conditions according to.. est onditions table. 7. ested initially and after a design or process change that affects this parameter. 8. t U is the delay between the time V is stable and the device is ready to accept commands. able 6... E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load 0.2 x V to 0.8 x V for V 2.2 V 0.15 x V to 0.85 x V for V < 2.2 V 50 ns 0.3 x V, 0.7 x V 0.3 x V, 0.7 x V urrent ource: I OL = 6 m (V 2.5 V); I OL = 2 m (V < 2.5 V); L = 100 pf 4

5 N2432 ower-on Reset (OR) Each N2432 incorporates ower-on Reset (OR) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the OR trigger level and will power down into Reset mode when V drops below the OR trigger level. his bi-directional OR behavior protects the device against brown-out failure following a temporary loss of power. in Description L: he erial lock input pin accepts the clock signal generated by the Master. D: he erial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2 : he ddress inputs set the device address that must be matched by the corresponding lave address bits. he ddress inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these inputs are pulled LOW internally. W: When pulled HIGH, the Write rotect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Functional Description he N2432 supports the Inter-Integrated ircuit (I 2 ) Bus protocol. he protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and lave devices which execute requests. he N2432 operates as a lave device. Both Master and lave can transmit or receive, but only the Master can assign those roles. I 2 Bus rotocol he 2-wire I 2 bus consists of two lines, L and D, connected to the V supply via pull-up resistors. he Master provides the clock to the L line, and either the Master or the laves drive the D line. 0 is transmitted by pulling a line LOW and a 1 by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, D must remain stable while L is HIGH. R/O ondition n D transition while L is HIGH creates a R or O condition (Figure 2). he R consists of a HIGH to LOW D transition, while L is HIGH. bsent the R, a lave will not respond to the Master. he O completes all commands, and consists of a LOW to HIGH D transition, while L is HIGH. Device ddressing he Master addresses a lave by creating a R condition and then broadcasting an 8-bit lave address. For the N2432, the first four bits of the lave address are set to 1010 (h); the next three bits, 2, 1 and 0, must match the logic state of the similarly named input pins. he R/W bit tells the lave whether the Master intends to read (1) or write (0) data (Figure 3). cknowledge During the 9 th clock cycle following every byte sent to the bus, the transmitter releases the D line, allowing the receiver to respond. he receiver then either acknowledges () by pulling D LOW, or does not acknowledge (No) by letting D stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. L D R ONDIION Figure 2. tart/top iming O ONDIION R/W DEVIE DDRE Figure 3. lave ddress Bits 5

6 N2432 BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R tlow tlow L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming WRIE OERION Byte Write o write data to memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 0. he Master then sends two address bytes and a data byte and concludes the session by creating a O condition on the bus. he lave responds with after every byte sent by the Master (Figure 6). he O starts the internal Write cycle, and while this operation is in progress (t WR ), the D output is tri-stated and the lave does not acknowledge the Master (Figure 7). age Write he Byte Write operation can be expanded to age Write, by sending more than one data byte to the lave before issuing the O condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal age Write Buffer starting at the address provided by the Master. he page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the O, data loaded during the age Write session will be written to memory in a single internal Write cycle (t WR ). cknowledge olling s soon (and as long) as internal Write is in progress, the lave will not acknowledge the Master. his feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a No response from the lave, the Master simply repeats the request until the lave responds with. Hardware Write rotection With the W pin held HIGH, the entire memory is protected against Write operations. If the W pin is left floating or is grounded, it has no impact on the Write operation. he state of the W pin is strobed on the last falling edge of L immediately preceding the 1 st data byte (Figure 9). If the W pin is HIGH during the strobe interval, the lave will not acknowledge the data byte and the Write request will be rejected. Delivery tate he N2432 is shipped erased, i.e., all bytes are FFh. 6

7 N2432 BU IVIY: MER R LVE LVE DDRE *a 15 a 12 are don t care bits. DDRE DDRE * * * * D a 15 a 8 a 7 a 0 d 7 d 0 Figure 6. Byte Write equence O L D 8th Bit Byte n t WR O ONDIION R ONDIION DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE DDRE DDRE D n D n+1 D n+ O LVE n = 1; 31 Figure 8. age Write equence DDRE D L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figure 9. W iming 7

8 N2432 RED OERION Immediate Read o read data from memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 1. he lave responds with and starts shifting out data residing at the current address. fter receiving the data, the Master responds with No and terminates the session by creating a O condition on the bus (Figure 10). he lave then returns to tandby mode. elective Read o read data residing at a specific address, the selected address must first be loaded into the internal address register. his is done by starting a Byte Write sequence, whereby the Master creates a R condition, then broadcasts a lave address with the R/W bit set to 0 and then sends two address bytes to the lave. Rather than completing the Byte Write sequence by sending data, the Master then creates a R condition and broadcasts a lave address with the R/W bit set to 1. he lave responds with after every byte sent by the Master and then sends out data residing at the selected address. fter receiving the data, the Master responds with No and then terminates the session by creating a O condition on the bus (Figure 11). equential Read If, after receiving data sent by the lave, the Master responds with, then the lave will continue transmitting until the Master responds with No followed by O (Figure 12). During equential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. BU IVIY: MER R LVE DDRE N O O LVE D L 8 9 D 8th Bit D OU NO Figure 10. Immediate Read equence and iming O BU IVIY: MER R LVE DDRE DDRE DDRE R LVE DDRE N O O LVE D Figure 11. elective Read equence BU IVIY: MER LVE DDRE N O O LVE D n D n+1 D n+2 D n+x Figure 12. equential Read equence 8

9 N2432 GE DIMENION U8 E 493 IUE D X Y 8 5 B L 1 4 G EING LNE D 0.10 (0.004) M X Y 0.10 (0.004) V R J U DEIL E DEIL E N H F R 0.10 Y M NOE: 1. DIMENIONING ND OLERNING ER NI Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DIMENION DOE NO INLUDE MOLD FLH, RORUION OR GE BURR. MOLD FLH. RORUION ND GE BURR HLL NO EXEED 0.14MM ( ) ER IDE. 4. DIMENION B DOE NO INLUDE INERLED FLH OR RORUION. INERLED FLH ND RORUION HLL NO EXEED 0.14MM ( ) ER IDE. 5. LED FINIH I OLDER LING WIH HINE OF MM ( ). 6. LL OLERNE UNLE OHERWIE EIFIED ±0.0508MM ( ). MILLIMEER INHE DIM MIN MX MIN MX B D F G 0.50 B B H 0.40 REF REF J L M N R U V 0.12 B B REOMMENDED OLDERING FOORIN* 8X X IH DIMENION: MILLIMEER *For additional information on our b Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. 9

10 N2432 ORDERING INFORMION Device Order Number pecific Device Marking ackage ype emperature Range hipping N2432UDG R U = U 8 D = Industrial ( 40 to +85 ) = ape & Reel, 3,000 Units / Reel N2432UVG Y U = U 8 V = utomotive Grade 1 ( 40 to +125 ) 9. ll packages are RoH-compliant (Lead-free, Halogen-free). 10. For additional package and temperature options, please contact your nearest ON emiconductor ales office. = ape & Reel, 3,000 Units / Reel ON emiconductor is licensed by hilips orporation to carry the I 2 Bus rotocol. ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at /site/pdf/atent Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor E. 32nd kwy, urora, olorado U hone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: hone: Japan ustomer Focus enter hone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative N2432/D