NC7SB3157, FSA3157 Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-multiplexer Bus Switch

Transcription

1 NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1Multiplexer / De-multiplexer Bus witch Features Useful in Both nalog and Digital pplications pace-aving, C7 6-Lead urface Mount Package Ultra-mall, MicroPak Leadless Package Low On Resistance: <1Ω on Typical at 3.3 Broad Operating Range: 1.65 to 5.5 Rail-to-Rail ignal Handling Power-Down, High-Impedance Control Over-oltage Tolerance of Control to 7. Break-Before-Make Enable Circuitry 25MHz, 3dB Bandwidth Ordering Information Part Number Description Top Mark Eco tatus Package Description The NC7B3157 / F3157 is a high-performance, single-pole / double-throw (PDT) analog switch or 2:1 multiplexer / de-multiplexer bus switch. The device is fabricated with advanced sub-micron CMO technology to achieve high-speed enable and disable times and low on resistance. The break-beforemake select circuitry prevents disruption of signals on the B Port due to both switches temporarily being enabled during select pin switching. The device is specified to operate over the 1.65 to 5.5 operating range. The control input tolerates voltages up to 5.5, independent of the operating range. NC7B3157P6X B7 RoH 6-Lead, C7, EIJ C88, 1.25mm Wide Package NC7B3157L6X BB RoH 6-Lead, MicroPak 1.mm Wide Package F3157P6X B7 RoH 6-Lead, C7, EIJ C88, 1.25mm Wide Package F3157L6X BB RoH 6-Lead, MicroPak 1.mm Wide Package Packing Method 3 Units on Tape and Reel 5 Units on Tape and Reel 3 Units on Tape and Reel 5 Units on Tape and Reel NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 26 emiconductor Components Industries, LLC. October-217, Rev. 2 Publication Order Number: NC7B3157/D

2 Logic ymbol B 1 nalog ymbol Function Table () Function Logic Level Low B Connected to Logic Level High B 1 Connected to Pin Descriptions Figure 1. Logic ymbol B B 1 B Figure 3. nalog ymbol Pin Names Description, B, B 1 Data Ports Control Connection Diagrams 2. Pin ssignments C7 Figure 4. Pin One Orientation Note: Orientation of top mark determines pin one location. Read the top product code mark left to right and pin one is the lower left pin (see Figure 4). B 1 B Figure 5. Pad ssignments for MicroPak 6 5 NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 2

3 bsolute Maximum Ratings tresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. ymbol Parameter Min. Max. Unit upply oltage DC witch oltage (1) IN DC oltage (1) I IK DC Diode Current at IN < 5 m I OUT DC Output Current 128 m I CC /I DC or Ground Current ±1 m T TG torage Temperature Range C T J Junction Temperature Under Bias +15 C T L Junction Lead Temperature (oldering, 1 seconds) +26 C ML Moisture ensitivity Level (JEDEC J-TD-2) 1 Level P D Power Dissipation at +85 C 18 mw ED Human Body Model, JED Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON emiconductor does not recommend exceeding them or designing to absolute maximum ratings. ymbol Parameter Min. Max. Unit upply oltage Operating IN Control oltage (2) IN witch oltage (2) OUT Output oltage (2) T Operating Temperature C t r, t f Rise and Fall Time Control = ns/ Control = ns/ θ J Thermal Resistance, C7 27 C/W Note: 2. Control input must be held HIGH or LOW; it must not float. NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 3

4 DC Electrical Characteristics ymbol Parameter Conditions () IH IL I IN I OFF R ON I CC R RNGE ΔR ON R flat High Level oltage Low Level oltage Leakage Current Off tate Leakage Current witch On Resistance (3) Quiescent upply Current; ll Channels On or Off nalog ignal Range On Resistance Over (3, 7) ignal Range On Resistance Match Between- (3, 4, 5) Channels On Resistance (3, 4, 6) Flatness T T = +25 C = 4 C to +85 C Min. Typ. Max. Min. Max. Notes: 3. Measured by the voltage drop between and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two ( or B Ports). 4. Parameter is characterized, but not tested in production. 5. ΔR ON = R ON max R ON minimum measured at identical, temperature, and voltage levels. 6. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. 7. Guaranteed by design. Units IN ±.5 ±.1 ±1 µ, B ±.5 ±.1 ±1 µ IN =, I O = 3m IN = 2.4, I O = 3m IN = 4.5, I O = 3m IN =, I O = 24m IN = 3, I O = 24m IN =, I O = 8m IN = 2.3, I O = 8m IN =, I O = 4m IN = 1.65, I O = 4m IN = or I OUT = µ I = 3m, Bn I = 24m, Bn I = 8m, Bn I = 4m, Bn I = 3m, Bn = I = 24m, Bn I = 8m, Bn = I = 4m, Bn = I = 3m, Bn I = 24m, Bn I = 8m, Bn I = 4m, Bn Ω Ω Ω Ω NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 4

5 C Electrical Characteristics ymbol Parameter Conditions Notes: 8. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the 5pF load capacitance, when driven by an ideal voltage source (zero output impedance). 9. Guaranteed by design. 1. Off Isolation = 2 log 1 [ / Bn ]. Capacitance () T = +25 C, f = 1MHz. Capacitance is characterized, but not tested in production. T T = +25 C = 4 C to +85 C Units Figure Number Min. Typ. Max. Min. Max t PHL, Propagation Delay Figure 12 t PLH Bus-to-Bus (8) I = OPEN ns Figure Output Enable Time t PZL, Turn-On Time I = 2 x for t PZL Figure 12 ns t PZH ( to B n ) I = for t PZH Figure Output Disable Time t PLZ, Turn-Off Time I = 2 x for t Figure 12 PLZ ns Figure 13 t PHZ ( Port to B Port) I = for t PHZ t B-M Break-Before-Make Time (9) ns Figure Q Charge Injection (9) C L =.1nF, GEN =, R GEN = Ω pc Figure 15 OIRR Off Isolation (1) R L = 5Ω, f = 1MHz db Figure 16 Xtalk Crosstalk R L = 5Ω, f = 1MHz db Figure 17 BW 3dB Bandwidth R L = 5Ω MHz Figure 2 THD Total Harmonic R L = 6Ω,.5 PP, Distortion (9) f = 6 Hz to 2 KHz % ymbol Parameter Conditions Typ. Max. Units Figure Number C IN Control Pin Capacitance = 2.3 pf C IO-B B Port Off Capacitance = pf Figure 18 C IO-ON Port Capacitance When witch Is Enabled = pf Figure 19 NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 5

6 Typical Characteristics Off Isolation (db) Crosstalk (db) Gain (db) -1 = = Figure 6. Off Isolation, = 1.65 Figure 7. Off Isolation, = = Figure 8. Crosstalk, = 1.65 Figure 9. Crosstalk, = 5.5 C L = pf = Off Isolation (db) Crosstalk (db) Gain (db) -1 = C L = pf = NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch Figure 1. Bandwidth, = 1.65 Figure 11. Bandwidth, = 5.5 6

7 C Loading and Waveforms t r = 2.5ns witch 1% Output IN Logic t PLH 9% 9% B B 1 t W FROM OUTPUT UNDER TET Figure 12. C Test Circuit Figure 13. C Waveforms Figure 14. Break-Before-Make Interval Timing C L I RU RD Notes: driven by 5Ω source terminated in 5Ω C L includes load and stray capacitance PRR = 1. MHz; t W = 5 ns 1% t PHL t r = 2.5ns R L OH OL C L OUT t r = 2.5ns Control Output Output t PZL t PZH 9% 9% 1% 1% Logic OUT t D t r = 2.5ns t PLZ OL +.3 OL t PHZ OH OH.3.9 x OUT TRI TRI NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 7

8 C Loading and Waveforms (continued) R GEN OUT GE R L C L 1MΩ 1pF OUT Logic nalyzer Capacitance Meter f = 1MHz 5Ω 5Ω B N 1nF B N Figure 16. Off Isolation Figure 18. Channel Off Capacitance 1nF B N Logic Figure 15. Charge Injection Test Logic or IH ignal Generator dbm Logic or Logic or 1nF B N ignal Generator dbm nalyzer Capacitance Meter f = 1MHz OFF ON Q = (Δ OUT )(C L ) 5Ω 1nF B B 1 Figure 17. Crosstalk 1nF B N OFF Δ OUT Figure 19. Channel On Capacitance 5Ω Logic or 5Ω NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch Figure 2. Bandwidth 8

9 Physical Dimensions Figure Lead, C7, EIJ C88, 1.25mm Wide Package Package drawings are provided as a service to customers considering ON emiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON emiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON emiconductor s worldwide terms and conditions, specifically the warranty therein, which covers ON emiconductor products. NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 9

10 Physical Dimensions 2X.5 C DETIL Notes:.5 C (.5) 6X 1. CONFORM TO JEDEC TNDRD M-252 RITION UD 2. DIMENION RE IN MILLIMETER 3. DRWING CONFORM TO ME Y14.5M-1994 MC6REC.55MX C 1.45 TOP IEW 1..5 BOTTOM IEW B 2X.5 C 6-Lead, MicroPak 1.mm Wide Package RECOMMENED LND PTTERN Package drawings are provided as a service to customers considering ON emiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON emiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON emiconductor s worldwide terms and conditions, specifically the warranty therein, which covers ON emiconductor products X C (.49) 5X (.52) 1X PIN 1.1 C B.5 C 5X 5X (.13) 4X.75 X 45 CHMFER (1) (.3) 6X.1. 6X.4.3 (.75) DETIL PIN 1 TERMINL NC7B3157, F3157 Low-oltage PDT nalog witch or 2:1 Multiplexer / De-multiplexer Bus witch 1

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