JLC1562B. I 2 C Bus I/O Expander

Size: px

Start display at page:

Download "JLC1562B. I 2 C Bus I/O Expander"

Baldric Booth
6 years ago
Views:

1 JLC562B I 2 C Bus I/O Epander The JLC562B facilitates easy I 2 C Bus epandibility. Multiple devices (up to 8 on the same I 2 C Bus) are easily added as each device has its own selectable 3 bit address. The JLC562B provides an 8 bit bidirectional input/output port and 6 bit resolution Digital to nalog Converter. The voltage on pins P P4 is compared with a controllable threshold voltage and the results are readable through the I 2 C Bus. I 2 C Bus interface pins, and 2 are; erial Data, erial Clock and Device ddress respectively. Eternal interface pins are P P7 and VDC; I/O Port and D/ output. Features Low Power Dissipation I 2 C Bus Format (2 Wire Type;, ) Data Transfer 6 bit DC Bus ddress electable (3 bit) ddress Input Pins are Pulled Up to V DD with Internal Resistor I/O Pins are Open Drain Outputs 5 Comparators at Inputs Inputs Protected from Eternal Bus Currents in Power Down Mode Pb Free Packages are vailable* 2 P P4 P5 P7 VDC 2 P P P2 P3 V V DD VDC P7 P6 P5 P4 Figure. Pin ssignment PIN LIT Chip ddress Input Comparator Input / Open Drain Output Comparator Input / Open Drain Output erial Clock Input I 2 C Data Output DC Output PDIP 6 N UFFIX CE 648 OEIJ 6 F UFFIX CE = ssembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb Free Package ORDERING INFORMTION MRKING DIGRM JLC562BN WLYYWWG JLC562B LYWG Device Package hipping JLC562BN PDIP 6 25 Units/Tube JLC562BNG JLC562BF OEIJ 6 5 Units/Rail JLC562BFG JLC562BFEL OEIJ 6 2/Tape & Reel JLC562BFELG PDIP 6 (Pb Free) OEIJ 6 (Pb Free) OEIJ 6 (Pb Free) 25 Units/Tube 2/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging pecifications Brochure, BRD8/D. 6 5 Units/Rail *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting Techniques Reference Manual, OLDERRM/D. emiconductor Components Industries, LLC, 25 November, 25 Rev. 5 Publication Order Number: JLC562B/D

2 JLC562B Power On Reset P7 2 V DD I2C Bus Controller hift Register (PIO) (IPO) 8 Bit 6 Bit Latch 6 Bit DC /2 V CC 3 Bit (C5 C7) Comp. Latch Write Buffer P6 P5 P4 P3 P2 P P VDC 5 Bit Latch 5 Bit (C C4) Comp. B NOTE: Internal Power On Reset sets P ~ P7 low, sets VDC to /8 V DD and selects /2 V DD for Comparator B threshold. Figure 2. Block Diagram V DD 6 X R 65 Pin VDC R 64 Comparator B V ref R 63 Write Data (2) V ref elector Bit D6 of Write Data (2) D6 V ref Value V ref = VDC R 4 V ref 4 8 V DD R 39 Write Data (2) D5 D4 D3 D2 D D V ref 64 8 V DD GND R 2 R 6:64 De MUX ( of 64 Decoder) Bits D D5 of Write Data (2) LB 8 V DD 2 8 V DD 8 V DD 2

3 JLC562B ÎÎÎ MXIMUM RTING (Referenced to GND) ymbol ÎÎÎÎ ÎÎÎ Value ÎÎÎÎ Unit V dd ÎÎÎÎ DC upply Voltage ÎÎÎ.5 to +7. ÎÎÎÎ V V in ÎÎÎÎ DC Input Voltage ÎÎÎ.5 to V dd +.5 ÎÎÎÎ V V out ÎÎÎÎ DC Output Voltage ÎÎÎ.5 to V dd +.5 ÎÎÎÎ V I ÎÎÎÎ DC Input/Output Current (per Pin) ÎÎÎ 25 ÎÎÎÎ m I DD ÎÎÎÎ DC upply Current (V DD and GND Pins) ÎÎÎ 75 ÎÎÎÎ m T stg ÎÎÎÎ torage Temperature Range ÎÎÎ 65 to +5 ÎÎÎÎ C T L ÎÎÎÎ Lead Temperature, mm from Case for econds ÎÎÎ 3 ÎÎÎÎ C Maimum ratings are those values beyond which device damage can occur. Maimum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are eceeded, device functional operation is not implied, damage may occur and reliability may be affected. RECOMMENDED OPERTING CONDITION ÎÎÎÎ ymbol Min Ma Unit ÎÎÎÎ V dd DC upply Voltage V ÎÎÎ V in, V out DC Input Voltage. V dd V Î ÎÎÎÎ Operating Temperature C T DC CHRCTERITIC (Referenced to V ss ) ymbol Guaranteed Limit V IH Maimum Input Voltage, H.7 V dd V V IL Maimum Input Voltage, L.3 V dd V V OL Maimum Output Voltage, L (I out = 4m).3 V I in Maimum Input Leakage Current (V in = V dd or V ss, pin only) ±. I oz Maimum Output Hi Z Leakage Current (Output = High Impedance; V out = V dd ) ± 5. C in Maimum Input Capacitance (Input Pin) pf C out Maimum Output Capacitance (Output Pin) 5 pf C i/o Maimum I/O Capacitance (I/O Pin) 5 pf V ICR Comparator Common Mode Input Voltage Range V dd.5 V I CC Maimum Quiescent upply Current (per Package) 5. m COMPRTOR C CHRCTERITIC ymbol Test Conditions Min Ma Guaranteed Limit Min Typ Ma t PD Maimum Propagation Delay V ref =.5 V, mv overdrive. Unit Unit V ref =.5 V, mv overdrive.2 3

4 JLC562B D COMPRTOR CHRCTERITIC Guaranteed Limit ymbol Min Typ Ma DNL DC Referential NON Linearity ±/4 LB e F DC Full cale Error ± LB e ZC DC Zero cale Error ± LB Unit TIMING CHRCTERITIC Guaranteed Limit ymbol Min Ma Unit f CL CLOCK Frequency khz t BUF BU Free Time (Between TOP and TRT ) 4.7 s t HD:T HOLD Time for TRT 4. s t LOW HOLD Time at CLOCK LOW 4.7 s t HIGH HOLD Time at CLOCK HI 4. s t HD:DT DT HOLD Time s t U:DT DT ETUP Time 25 ns t R Rise Time ( and ) ns t F Fall Time ( and ) 3 ns t U:TO ETUP Time for TOP 4. s t BUF t LOW t R t F t HD:T t HD:DT t HIGH t U:DT t U:TO 4

5 JLC562B RED / WRITE MODE MODE I/O Epander Master Device lave Device I/O Port RED Receiver Transmitter Input WRITE Transmitter Receiver Output Micro Controller (Master Device) I/O Epander (lave Device) P P7 The JLC562B upports the following types of Bus Cycles.) WRITE MODE () lave ddress & R/W Write Data () P 2.) WRITE MODE (B) lave ddress & R/W Write Data () Write Data (2) P 3.) RED MODE () lave ddress & R/W Read Data MCK P 4.) RED MODE (B) lave ddress & R/W Read Data () MCK Read Data (2) MCK Read Data (3) MCK P = TRT Condition = lave cknowledgement MCK = Master cknowledgement P = TOP Condition 5

6 JLC562B RED WRITE DT FORMT <<RED MODE>> 2 CK D7 D6 D5 D4 D3 D2 D D CK P lave ddress Read Data lave ddress 2 I/O Epander Device ddress (Pins 2) is hard wired as R/W : RED DDRE Read Data D5 D7 Output of Comparator. (V th = /2 V DD ) D D4 Output of Comparator B. (V th = /2 V DD OR V DC ) RED LTCH Bit Controls when Data Will Be Latched. <<WRITE MODE>> 2 CK D7 D6 D5 D4 D3 D2 D D CK D7 D6 D5 D4 D3 D2 D D CK P lave ddress Write Data () Write Data (2) lave ddress 2 I/O Epander Device ddress (Pins 2) is hard wired as R/W : WRITE DDRE Write Data () D D7 Device Pins P to P7 Output Bits. Write Data (2) D7 RED LTCH CONTROL Latch Control of ignals C C4 in the Device BLOCK DIGRM : Data is latched at the CK after a RED COMMND. : Data is latched when Comparator B switches from to. (switch point is controlled by V th.) : Data is reset at the CK after a RED COMMND. D6 COMPRTOR B V ref Control Bit :V ref 4 8 V DD :V ref V DC D D5 DC Input Bits 6

7 JLC562B <<WRITE MODE>> WRITE COMMND DT (I) DT (II) P Write_buffer Latch Pulse I/O Port (P P7) DT (I) valid DC Latch Pulse DC Latch DT (II) valid <<RED MODE>> (RED LTCH = ) RED COMMND DT (I) + (II) P PIO Load Pulse Comp_out (C C4) Comp_out (C5 C7) DT (I) DT (II) <<RED MODE>> (RED LTCH = ) WRITE DT (II) RED COMMND DT (I) P P DC Latch D7 (RED LTCH Bit) LTCH Reset Comp._out Latched Data DT (I) PIO Load Pulse 7

8 JLC562B PCKGE DIMENION PDIP 6 N UFFIX CE IUE T B NOTE:. DIMENIONING ND TOLERNCING PER NI Y4.5M, CONTROLLING DIMENION: INCH. 3. DIMENION L TO CENTER OF LED WHEN FORMED PRLLEL. 4. DIMENION B DOE NOT INCLUDE MOLD FLH. 5. ROUNDED CORNER OPTIONL. H G F D 6 PL C K.25 (.) M T T ETING PLNE M J L M INCHE MILLIMETER DIM MIN MX MIN MX B C D F G. BC 2.54 BC H.5 BC.27 BC J K L M OEIJ 6 CE 966 IUE e 6 9 Z b D H E.3 (.5) M. (.4) 8 E VIEW P M L E Q L DETIL P c NOTE: М. DIMENIONING ND TOLERNCING PER NI Y4.5M, 982. М 2. CONTROLLING DIMENION: MILLIMETER. М 3. DIMENION D ND E DO NOT INCLUDE MOLD FLH OR PROTRUION ND RE MEURED T THE PRTING LINE. MOLD FLH OR PROTRUION HLL NOT EXCEED.5 (.6) PER IDE. М 4. TERMINL NUMBER RE HOWN FOR REFERENCE ONLY. М 5. THE LED WIDTH DIMENION (b) DOE NOT INCLUDE DMBR PROTRUION. LLOWBLE DMBR PROTRUION HLL BE.8 (.3) TOTL IN EXCE OF THE LED WIDTH DIMENION T MXIMUM MTERIL CONDITION. DMBR CNNOT BE LOCTED ON THE LOWER RDIU OR THE FOOT. MINIMUM PCE BETWEEN PROTRUION ND DJCENT LED TO BE.46 (.8). MILLIMETER INCHE DIM MIN MX MIN MX b c D E e.27 BC.5 BC H E L L E M Q Z

9 JLC562B ON emiconductor and are registered trademarks of emiconductor Components Industries, LLC (CILLC). CILLC reserves the right to make changes without further notice to any products herein. CILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does CILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in CILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical eperts. CILLC does not convey any license under its patent rights nor the rights of others. CILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the CILLC product could create a situation where personal injury or death may occur. hould Buyer purchase or use CILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold CILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and epenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that CILLC was negligent regarding the design or manufacture of the part. CILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON emiconductor P.O. Bo 632, Phoeni, rizona U Phone: or Toll Free U/Canada Fa: or Toll Free U/Canada orderlit@onsemi.com N. merican Technical upport: Toll Free U/Canada Japan: ON emiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan 53 5 Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative. JCL562B/D

NUP4302MR6T1G. Schottky Diode Array for Four Data Line ESD Protection

NUP4302MR6T1G. Schottky Diode Array for Four Data Line ESD Protection Schottky Diode Array for Four Data Line ESD Protection The NUP432MR6 is designed to protect high speed data line interface from ESD, EFT and lighting. Features Very Low Forward Voltage Drop Fast Switching