MC14046B. Phase Locked Loop

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MC4046B Phase Locked Loop The MC4046B phase locked loop contains two phase comparators, a voltagecontrolled oscillator (VCO), source follower, and zener diode.

1 MC4046B Phase Locked Loop The MC4046B phase locked loop contains two phase comparators, a voltagecontrolled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, and. Input can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The selfbias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal PC out, and maintains 90 phase shift at the center frequency between and signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2 out and LD, and maintains a 0 phase shift between and signals (duty cycle is immaterial). The linear VCO produces an output signal VCO out whose frequency is determined by the voltage of input and the capacitor and resistors connected to pins C, C B, R, and R2. The sourcefollower output SF out with an external resistor is used where the signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. pplications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltagetofrequency conversion and motor speed control. Features Buffered Outputs Compatible with MHTL and LowPower TTL Diode Protection on ll Inputs Supply Voltage Range = 3.0 to 8 V PinforPin Replacement for CD4046B Phase Comparator is an Exclusive OR Gate and is Duty Cycle Limited Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle Limited PbFree Packages are vailable* MXIMUM RTINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to +8.0 V V in Input Voltage Range (ll Inputs) 0.5 to V DD V I in DC Input Current, per Pin ± 0 m P D Power Dissipation, per Package (Note ) 500 mw T Operating Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to +50 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C WL, L YY, Y WW, W G PDIP6 P SUFFIX CSE 648 SOIC6 DW SUFFIX CSE 75G SOEIJ6 F SUFFIX CSE 966 MRKING DIGRMS MC4046BCP WLYYWWG MC4046B LYWG = ssembly Location = Wafer Lot = Year = Work Week = PbFree Indicator ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet BG WLYYWW This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6 Semiconductor Components Industries, LLC, 2005 ugust, 2005 Rev. 0 Publication Order Number: MC4046B/D

2 MC4046B BLOCK DIGRM PIN SSIGNMENT V DD = PIN 6 V SS = PIN 8 4 INH SELF BIS CIRCUIT V SS PHSE COMPRTOR PHSE COMPRTOR 2 VOLTGE CONTROLLED OSCILLTOR (VCO) SOURCE FOLLOWER 2 PC out 3 PC2 out LD 4 VCO out R 2 R2 6 C 7 C B 0 SF out 5 ZENER LD PC out VCO out INH C C B V SS V DD ZENER PC2 out R2 R SF out ELECTRICL CHRCTERISTICS (Voltages Referenced to V SS ) Î Characteristic Symbol V 55 C 25 C Î 25 C DD Vdc Min Max Min Typ Max Min Max Unit Output Voltage 0 Level V in = V DD Vdc or Level V V in = 0 or V DD OH Vdc Input Voltage (Note 2) 0 Level V IL Vdc (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) (V O = 0.5 or 4.5 Vdc) Level V IH ÎÎ (V O =.0 or 9.0 Vdc) Vdc (V O =.5 or 3.5 Vdc) Output Drive Current I ( = 2.5 Vdc) Source OH mdc (V OH = 4.6 Vdc) ( = 9.5 Vdc) ( = 3.5 Vdc) ( = 0.4 Vdc) Sink I OL mdc (V OL = 0.5 Vdc) ( =.5 Vdc) Input Current Iin 5 ± 0. ± ± 0. ±.0 dc Input Capacitance C in 7.5 pf Quiescent Current I DD dc (Per Package) Inh = PC in = V DD, Zener = = 0 V, = V DD or 0 V, I out = 0 Total Supply Current (Note 3) I T ÎÎ I T = (.46 /khz) f + I DD mdc (Inh = 0, f o = 0 khz, C L = 50 pf, 0 I R =.0 M, R2 = R SF =, 5ÎÎ T = (2.9 /khz) f + I DD I T = (4.37 /khz) f + I DD and 50% Duty Cycle) ÎÎ 2. Noise immunity specified for worstcase input combination. Noise Margin for both and 0 level =.0 Vdc V DD = Vdc 2.0 Vdc V DD = 0 Vdc 2.5 Vdc V DD = 5 Vdc 3. To Calculate Total Current in General:.65 I T 2.2 x V DD + V DD.35 3/4.65 3/4 +.6 x + x 0 3 (C L + 9) V DD f + R R2 R SF x 0 V 00% Duty Cycle of 2 DD + IQ 00 where: I T in, C L in pf,, V DD in Vdc, f in khz, and R, R2, R SF in M, C L on VCO out. 2

3 MC4046B ELECTRICL CHRCTERISTICS (Note 4) (C L = 50 pf, T = 25 C) ÎÎ Minimum V Characteristic Symbol Î DD Maximum Vdc Device Typical Device Units Output Rise Time t TLH Î ns t TLH = (3.0 ns/pf) C L + 30 ns t TLH = (.5 ns/pf) C L + 5 ns t TLH = (. ns/pf) C L + 0 ns Output Fall Time t THL Î ns t THL = (.5 ns/pf) C L + 25 ns t THL = (0.75 ns/pf) C L ns t THL = (0.55 ns/pf) C L ns PHSE COMPRTORS and 2 Input Resistance PC in R in Î M ÎÎ R in Î M Minimum Input Sesitivity C Coupled PC in V in Î mv p p Î C series = 000 pf, f = 50 khz DC Coupled, Î 5 to 5 See Noise Immunity VOLTGE CONTROLLED OSCILLTOR (VCO) Maximum Frequency f max Î ( = V DD, C = 50 pf MHz R = k, and R2 = ) Temperature Frequency Stability 0.2 %/ C (R2 = ) Linearity (R2 = ) Î % (VCO in = 2.5 V ± 0.3 V, R > 0 k ).0 ( = V ± 2.5 V, R > 400 k ) 0.0 ( = 7.5 V ± V, R 000 k ) 5.0 Output Duty Cycle Î 5 to 5 50 % Input Resistance R in Î M SOURCEFOLLOWER Offset Voltage ( minus SF out V Î, RSF > 500 k ) Linearity Î % (VCO in = 2.5 V ± 0.3 V, R SF > 50 k ) 0. ( = V ± 2.5 V, R SF > 50 k ) ( = 7.5 V ± V, R SF > 50 k ) ZENER DIODE Zener Voltage (I z = 50 ) V Z Î V Dynamic Resistance (I z =.0 m) R Z Î The formula given is for the typical characteristics only. 3

4 MC4046B ORDERING INFORMTION Device Package Shipping MC4046BCP PDIP6 500 Units / Rail MC4046BCPG PDIP6 (PbFree) 500 Units / Rail MC4046BDW SOIC6 WB 47 Units / Rail MC4046BDWG SOIC6 WB (PbFree) 47 Units / Rail MC4046BDWR2 SOIC6 WB 000 Units / Tape & Reel MC4046BDWR2G SOIC6 WB (PbFree) 000 Units / Tape & Reel MC4046BF SOEIJ6 50 Units / Rail MC4046BFEL SOEIJ Units / Tape & Reel MC4046BFELG SOEIJ6 (PbFree) 2000 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 4

5 MC4046B PHSE COMPRTOR Input Stage X X PC out 0 Input Stage PHSE COMPRTOR 2 X X State PC2 out 0 Output Disconnected LD (Lock Detect) 0 0 Refer to Waveforms in Figure 3. Figure. Phase Comparators State Diagrams Î Characteristic Î Using Phase Comparator Using Phase Comparator 2 Î No signal on input. Î PLL system adjusts to center PLL system adjusts to minimum Î Î frequency (f 0 ). frequency (f min ). Î Phase angle between and. Î 90 at center frequency (f 0 ), approaching lways 0 in lock (positive rising edges). 0 and 80 at ends of lock range (2f Î Î L ) Î Locks on harmonics of center frequency. Î Yes No Î Signal input noise rejection. Î High Low Î Lock frequency range (2f L ). The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2f L = full VCO frequency range = f max f min. Î Capture frequency range (2f C ). The frequency range of the input signal on which the loop will lock if it was initially out of lock. Î Î Depends on lowpass filter characteristics f C = f L (see Figure 3). f Î Î C f L Î Center frequency (f 0 ). The frequency of VCO out, when = /2 V DD Î VCO output frequency (f). f min = (V CO input = V SS ) R 2 (C + 32 pf) Î Note: These equations are intended to be Î a design guide. Since calculated component f max = + f min (V CO input = V DD ) R (C values may be in error by as much as a + 32 pf) Î factor of 4, laboratory experimentation may Where: 0K R M be required for fixed designs. Part to part 0K R 2 M frequency variation with identical passive 00pF C Î components is typically less than ± 20%..0 F Figure 2. Design Information 5

6 MC4046B 9 SOURCE 0 FOLLOWER R SF SF FREQUENCY f 4 3 PHSE COMPRTOR 2 OR 3 PC out OR PC2 out EXTERNL LOWPSS FILTER EXTERNL N COUNTER 9 VCO CI CI B R R2 CI VCO FREQUENCY Nf = f (a) INPUT R3 C2 OUTPUT 2fC 2 fl R3 C2 Typical LowPass Filters (a) INPUT R3 R4 C2 OUTPUT Typically: R4 C2 6N fmax N 2 f (R3 3, 000 ) C2 00N f fmax2 R 4 C2 f = f max f min NOTE: Sometimes R3 is split into two series resistors each R3 2. capacitor C C is then placed from the midpoint to ground. The value for C C should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the damping, R4 (0.)(R3) for optimum results. Definitions: N = Total division ratio in feedback loop Kφ = V DD /π for Phase Comparator Kφ = V DD /4 π for Phase Comparator 2 KVCO 2 f VCO VDD 2V 2 for a typical design fr n (at phase detector input) 0 ζ Filter n K KVCO NR 3C2 N n 2K KVCO F(s) R 3 C 2 S LOWPSS FILTER Filter B K KVCO n NC 2(R3 R4) 0.5 n (R 3 C 2 N K KVCO ) R3C2S F(s) S(R 3 C 2 R 4 C 2 ) Waveforms Phase Comparator Phase Comparator 2 V DD V SS V DD V SS PC out PC2 out Note: for further information, see: () F. Gardner, PhaseLock Techniques, John Wiley and Son, New York, 966. (2) G. S. Moschytz, Miniature RC Filters Using PhaseLocked Loop, BSTJ, May, 965. (3) Garth Nash, PhaseLock Loop Design Fundamentals, N535, Motorola Inc. (4). B. Przedpelski, PhaseLocked Loop Design rticles, R254, reprinted by Motorola Inc. LD Figure 3. General PhaseLocked Loop Connections and Waveforms 6

7 MC4046B PCKGE DIMENSIONS PDIP6 P SUFFIX PLSTIC DIP PCKGE CSE ISSUE T B NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEDS WHEN FORMED PRLLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLSH. 5. ROUNDED CORNERS OPTIONL. H G F D 6 PL S C K 0.25 (0.00) M T T SETING PLNE M J L M INCHES MILLIMETERS DIM MIN MX MIN MX B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S SOIC6 WB DW SUFFIX PLSTIC SOIC PCKGE CSE 75G03 ISSUE C 8X H 0.25 M B M D 6 9 E 8 6X B B 0.25 M T S B S h X 45 NOTES:. DIMENSIONS RE IN MILLIMETERS. 2. INTERPRET DIMENSIONS ND TOLERNCES PER SME Y4.5M, DIMENSIONS D ND E DO NOT INLCUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE 0.3 TOTL IN EXCESS OF THE B DIMENSION T MXIMUM MTERIL CONDITION. MILLIMETERS DIM MIN MX B C D E e.27 BSC H h L q 0 7 4X e T SETING PLNE C L 7

8 MC4046B PCKGE DIMENSIONS SOEIJ6 F SUFFIX PLSTIC EIJ SOIC PCKGE CSE 9660 ISSUE O e 6 9 Z b D H E 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M L E Q L DETIL P c NOTES: М. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, 982. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D ND E DO NOT INCLUDE MOLD FLSH OR PROTRUSIONS ND RE MESURED T THE PRTING LINE. MOLD FLSH OR PROTRUSIONS SHLL NOT EXCEED 0.5 (0.006) PER SIDE. М 4. TERMINL NUMBERS RE SHOWN FOR REFERENCE ONLY. М 5. THE LED WIDTH DIMENSION (b) DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE 0.08 (0.003) TOTL IN EXCESS OF THE LED WIDTH DIMENSION T MXIMUM MTERIL CONDITION. DMBR CNNOT BE LOCTED ON THE LOWER RDIUS OR THE FOOT. MINIMUM SPCE BETWEEN PROTRUSIONS ND DJCENT LED TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MX MIN MX b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, rizona US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Japan: ON Semiconductor, Japan Customer Focus Center 29 Kamimeguro, Meguroku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MC4046B/D

Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to V

Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to V MC4046B Phase Locked Loop The MC4046B phase locked loop contains two phase comparators, a voltagecontrolled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs,