Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to V
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1 MC4046B Phase Locked Loop The MC4046B phase locked loop contains two phase comparators, a voltagecontrolled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, and. Input can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The selfbias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal PC out, and maintains 90 phase shift at the center frequency between and signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2 out and LD, and maintains a 0 phase shift between and signals (duty cycle is immaterial). The linear VCO produces an output signal VCO out whose frequency is determined by the voltage of input VCO in and the capacitor and resistors connected to pins C A, C B, R, and R2. The sourcefollower output SF out with an external resistor is used where the VCO in signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltagetofrequency conversion and motor speed control. Features Buffered Outputs Compatible with LowPower TTL Diode Protection on All Inputs Supply Voltage Range = 3.0 to 8 V PinforPin Replacement for CD4046B Phase Comparator is an Exclusive OR Gate and is Duty Cycle Limited Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle Limited These Devices are PbFree and are RoHS Compliant NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ00 Qualified and PPAP Capable A WL, L YY, Y WW, W G PDIP6 P SUFFIX CASE 648 SOIC6 WB DW SUFFIX CASE 75G SOEIAJ6 F SUFFIX CASE 966 MARKING DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week = PbFree Indicator MC4046BCP AWLYYWWG MC4046B ALYWG ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. V in Input Voltage Range (All Inputs) 0.5 to V DD V I in DC Input Current, per Pin ±0 ma P D Power Dissipation, per Package (Note ) 500 mw T A Operating Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to +50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C BG AWLYYWW This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. MAXIMUM RATINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to +8.0 V 6 Semiconductor Components Industries, LLC, 203 April, 203 Rev. 3 Publication Order Number: MC4046B/D
2 MC4046B BLOCK DIAGRAM PIN ASSIGNMENT V DD = PIN 6 V SS = PIN 8 4 VCO in INH SELF BIAS CIRCUIT V SS PHASE COMPARATOR PHASE COMPARATOR 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) SOURCE FOLLOWER 2 PC out 3 PC2 out LD 4 VCO out R 2 R2 6 C A 7 C B 0 SF out 5 ZENER LD PC out VCO out INH C A C B V SS V DD ZENER PC2 out R2 R SF out VCO in ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) ÎÎ Characteristic Symbol V 55 C ÎÎ 25 C ÎÎ 25 C DD Vdc Min Î Max Min Î Typ Max Min Max Unit Output Voltage 0 Level V in = V DD Vdc Î or Î 0.05 Î Level V V in = 0 or V DD OH 4.95 Î 4.95 Î 4.95 Vdc Î 4.95 Î Input Voltage (Note 2) 0 Level V IL Î Vdc (V O = 4.5 or 0.5 Vdc) Î.5 Î (V O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) 5 Î 4.0 Î (V O = 0.5 or 4.5 Vdc) Level V IH (V O =.0 or 9.0 Vdc) Î Î 7.0 Î Vdc (V O =.5 or 3.5 Vdc) Output Drive Current I ( = 2.5 Vdc) Source OH madc.2 Î.0 Î ( = 4.6 Vdc) Î (V OH = 9.5 Vdc) ( = 3.5 Vdc) 5.8 Î.5 Î 3.5. ( = 0.4 Vdc) Sink I OL (V OL = 0.5 Vdc) ( Î 0.5 Î madc =.5 Vdc) Input Current Iin 5 Î ± 0. Î ± ± 0. ±.0 Adc Input Capacitance C in Î 7.5 pf Quiescent Current I DD Î Î Adc (Per Package) Inh = = V DD, Zener = VCO in = 0 V, = V DD Î or 0 V, I out = 0 A Î Total Supply Current (Note 3) I T ÎÎ I T = (.46 A/kHz) f + I DD madc (Inh = 0, f o = 0 khz, C L = 50 pf, 0 I R =.0 M, R2 = R SF Î T = (2.9 A/kHz) f + I DD =, 5 I T = (4.37 A/kHz) f + I DD and 50% Duty Cycle) 2. Noise immunity specified for worstcase input combination. Noise Margin for both and 0 level =.0 Vdc V DD = Vdc 2.0 Vdc V DD = 0 Vdc 2.5 Vdc V DD = 5 Vdc 3. To Calculate Total Current in General: VCO in.65 I T 2.2 x V DD + V DD.35 3/4 VCO in.65 3/4 +.6 x + x 0 3 (C L + 9) V DD f + R R2 R SF x 0 V 00% Duty Cycle of 2 DD + IQ 00 where: I T in A, C L in pf, VCO in, V DD in Vdc, f in khz, and R, R2, R SF in M, C L on VCO out. 2
3 MC4046B ELECTRICAL CHARACTERISTICS (Note 4) (C L = 50 pf, T A = 25 C) Î Minimum Î Î Maximum V Characteristic Î Symbol ÎÎ DD Vdc Î Device Î Typical Î Device Units Output Rise Time Î t TLH Î ns t TLH = (3.0 ns/pf) C L + 30 ns t TLH = (.5 ns/pf) C L + 5 ns ÎÎ 0 Î Î 90 Î 50 t TLH = (. ns/pf) C L + 0 ns ÎÎ 5 Î Î 65 Î 0 Output Fall Time Î t THL Î ns t THL = (.5 ns/pf) C L + 25 ns t THL = (0.75 ns/pf) C L ns ÎÎ 0 Î Î 50 Î 75 t THL = (0.55 ns/pf) C L ns ÎÎ 5 Î Î 37 Î 55 PHASE COMPARATORS and 2 Input Resistance PCA in Î R in ÎÎ M Î Î Î 5 Î 0. Î 0.2 Î Î R in ÎÎ 5 Î 50 Î 500 Î M Minimum Input Sesitivity Î AC Coupled PCA in Î V in ÎÎ Î Î 200 Î 300 mv p p Î C series = 000 pf, f = 50 khz DC Coupled, Î Î 5 to 5 See Noise Immunity VOLTAGE CONTROLLED OSCILLATOR (VCO) Maximum Frequency f max Î (VCO in = V DD, C = 50 pf ÎÎ 0 Î.0 Î.4 Î MHz R = k, and R2 = ) Temperature Frequency Stability 0.2 %/ C (R2 = ) ÎÎ 0 Î Î 0.04 Î Î 5 Î Î 0.05 Î Linearity (R2 = ) Î Î % (VCO in = 2.5 V ± 0.3 V, R > 0 k ).0 (VCO in = V ± 2.5 V, R > 400 k ) ÎÎ 0 Î Î.0 Î (VCO in = 7.5 V ± V, R 000 k ) ÎÎ 5 Î Î.0 Î Output Duty Cycle Î ÎÎ 5 to 5 Î Î 50 Î % Input Resistance VCO in Î R in ÎÎ 5 Î 50 Î 500 Î M SOURCEFOLLOWER Offset Voltage Î ÎÎ Î Î.65 Î 2.2 V (VCO in minus SF out, RSF > 500 k ) ÎÎ 5 Î Î.65 Î 2.2 Linearity Î Î % (VCO in = 2.5 V ± 0.3 V, R SF > 50 k ) 0. (VCO in = V ± 2.5 V, R SF Î > 50 k ) (VCO in = 7.5 V ± V, R SF > 50 k ) ÎÎ 5 Î Î 0.8 Î ZENER DIODE Zener Voltage (I z = 50 A) Î V Z ÎÎ Î 6.7 Î 7.0 Î 7.3 V Dynamic Resistance (I z =.0 ma) Î R Z ÎÎ Î Î 00 Î 4. The formula given is for the typical characteristics only. 3
4 MC4046B ORDERING INFORMATION MC4046BCPG MC4046BDWG NLV4046BDWG* MC4046BDWR2G MC4046BFELG MC4046BFG Device Package Shipping PDIP6 (PbFree) SOIC6 WB (PbFree) SOIC6 WB (PbFree) SOEIAJ6 (PbFree) SOEIAJ6 (PbFree) 500 Units / Rail 47 Units / Tube 000 Units / Tape & Reel 2000 Units / Tape & Reel 50 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ00 Qualified and PPAP Capable. 4
5 MC4046B PHASE COMPARATOR Input Stage X X PC out 0 Input Stage PHASE COMPARATOR 2 X X State PC2 out 0 Output Disconnected LD (Lock Detect) 0 0 Refer to Waveforms in Figure 3. Figure. Phase Comparators State Diagrams Î Characteristic Î Using Phase Comparator Using Phase Comparator 2 Î No signal on input. Î VCO in PLL system adjusts to center VCO in PLL system adjusts to minimum Î Î frequency (f 0 ). frequency (f min ). Î Phase angle between and. Î 90 at center frequency (f 0 ), approaching Always 0 in lock (positive rising edges). 0 and 80 at ends of lock range (2f Î Î L ) Î Locks on harmonics of center frequency. Î Yes No Î Signal input noise rejection. Î High Low Î Lock frequency range (2f L Î ). The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2f L = full VCO frequency range = f max f min. Î Capture frequency range (2f C ). Î The frequency range of the input signal on which the loop will lock if it was initially out of lock. Î Î Depends on lowpass filter characteristics f C = f L (see Figure 3). f Î Î C f L Î Center frequency (f 0 ). Î The frequency of VCO out, when VCO in = /2 V DD Î VCO output frequency (f). Î f min = (V CO input = V SS ) R 2 (C + 32 pf) Î Note: These equations are intended to be Î Î a design guide. Since calculated component f Î max = + f min (V CO input = V DD ) R (C values may be in error by as much as a + 32 pf) Î factor of 4, laboratory experimentation mayî Where: 0K R M Î be required for fixed designs. Part to part Î 0K R 2 M frequency variation with identical passive 00pF C Î components is typically less than ± 20%. Î.0 F Figure 2. Design Information 5
6 MC4046B VCO in 9 SOURCE 0 FOLLOWER R SF SF FREQUENCY f 4 3 PHASE COMPARATOR 2 OR 3 PC out OR PC2 out EXTERNAL LOW-PASS FILTER EXTERNAL N COUNTER 9 VCO CI A CI B R R2 CI VCO FREQUENCY Nf = f (a) INPUT R3 C2 OUTPUT 2fC 2 fl R3 C2 Typical LowPass Filters (a) INPUT R3 R4 C2 OUTPUT Typically: R4 C2 6N fmax N 2 f (R3 3, 000 ) C2 00N f fmax2 R 4 C2 f = f max f min NOTE: Sometimes R3 is split into two series resistors each R3 2. A capacitor C C is then placed from the midpoint to ground. The value for C C should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the damping, R4 (0.)(R3) for optimum results. Definitions: N = Total division ratio in feedback loop Kφ = V DD /π for Phase Comparator Kφ = V DD /4 π for Phase Comparator 2 KVCO 2 f VCO VDD 2V 2 fr for a typical design n (at phase detector input) 0 ζ Filter A n K KVCO NR 3C2 N n 2K KVCO F(s) R 3 C 2 S LOWPASS FILTER Filter B K KVCO n NC 2(R3 R4) 0.5 n (R 3 C 2 N K KVCO ) R3C2S F(s) S(R 3 C 2 R 4 C 2 ) Waveforms Phase Comparator Phase Comparator 2 V DD V SS V DD V SS PC out VCO in PC2 out VCO in Note: for further information, see: () F. Gardner, PhaseLock Techniques, John Wiley and Son, New York, 966. (2) G. S. Moschytz, Miniature RC Filters Using PhaseLocked Loop, BSTJ, May, 965. (3) Garth Nash, PhaseLock Loop Design Fundamentals, AN535, Motorola Inc. (4) A. B. Przedpelski, PhaseLocked Loop Design Articles, AR254, reprinted by Motorola Inc. LD Figure 3. General PhaseLocked Loop Connections and Waveforms 6
7 MC4046B PACKAGE DIMENSIONS PDIP6 P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE T 6 A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D 6 PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S
8 MC4046B PACKAGE DIMENSIONS SOIC6 WB CASE 75G03 ISSUE D 8X H 0.25 M B M D 6 9 A E h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 6X B 0.25 M T A S B S A B MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L q 0 7 L 4X e A T SEATING PLANE C SOLDERING FOOTPRINT 6X X PITCH DIMENSIONS: MILLIMETERS 8
9 MC4046B e 6 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P PACKAGE DIMENSIONS M SOEIAJ6 F SUFFIX CASE 9660 ISSUE A L E Q L DETAIL P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4046B/D
10 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: MC4046BCP MC4046BCPG MC4046BDW MC4046BDWR2 MC4046BF MC4046BFEL
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