Device Code Name. Pin Configuration. Features

Transcription

1 Descripions The GM6C55 is an asynchronous communicaions elemen (ACE) ha is funcionally equivalen o he GM6C45, and addiionally incorporaes a 6bye FIFOs are available on boh he ransmier and receiver, and can be acivaed by placing he device in he FIFO mode. Afer a rese, he regisers of he GM6C55 are idenical o hose of he GM6C45. The UART performs serialoparallel conversion on daa characers received from a peripheral device or a MODEM, and parallelo serial conversion on daa characers received from he CPU. The CPU can read he complee saus of he UART a any ime during he funcional operaion. Saus informaion repored includes he ype and condiion of he ransfer operaions being performed by he UART, as well as any error condiions (pariy, overrun, framing, or break inerrup). Feaures Compaible o he Indusry Sandard 6C55 Modem conrol signals include CTS, RTS,DSR DTR, RI and DCD Programmable serial characerisics : 5, 6, 7 or 8bi characers Even, odd, or nopariy bi generaion and deecion, /2 or 2sop bi generaion Baud rae generaion (DC o 256K baud) 6 bye FIFO reduces CPU inerrups. Independen conrol of ransmi, receive, line saus, daa se inerrups, FIFOs. Full saus reporing capabiliies Threesae, TTL drive capabiliies for bidirecional daa bus and conrol bus. 4DIP/44PLCC/48LQFP Device Code Name Pin Configuraion D D D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS CS CS2 BAUDQUT XTAL XTAL2 DOSTR DOSTR VSS 4DIP VCC RI DCD DSR CTS MR OUT DTR RTS OUT2 INTRPT RXRDY A A A2 ADS TXRDY DDIS DISTR DISTR

2 8 389(

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4 GM6C55 AC Characerisics T A = C o + 7 C, VCC = 5V/3.3V Symbol Parameer Min Max Unis Condiions ADS Address Srobe Widh 6 ns AH Address Hold Time ns AR RD, RD Delay from Address 3 ns Noe AS Address Seup Time 6 ns AW WR, WR Delay from Selec 3 ns Noe CH Chip Selec Hold Time ns CS Chip Selec Seup ime 6 ns CSR RD, RD Delay from Chip Selec 3 ns Noe CSW WR, WR Delay from Selec 3 ns Noe DH Daa Hold Time 3 ns DS Dae Seup Time 3 ns HZ RD, RD o Floaing Daa Delay ns pf loading, Noe 3 MR Maser Rese Pulse Widh 5 ns r RA Address Hold Time from RD, RD 2 ns Noe RC Read Cycle Delay 25 ns RCS Chip Selec Hold Time from RD, RD 2 ns Noe RD RD, RD Srobe Widh 25 ns RDD RD, RD o Driver Enable/Disable 6 ns pf loading, Noe 3 RVD Delay from RD, RD o Daa 25 ns pf loading, WA Address Hold Time from WR, WR 2 ns Noe WC Wrie Cycle Delay 5 ns WCA Chip Selec Hold Time from WR, WR 2 ns Noe WR WR, WR Srobe Widh ns XH Duraion of clock High Pulse 55 ns Exernal Clock (8. MHz Max.) XL Duraion of clock Low Pulse 55 ns Exrernal Clock (8.9 MHz Max.) RC Read Cycle= AR+ RD+ RC 28 ns Noe 4 WC Wrie Cycle= AW+ WR+ WC 28 ns Baud Generaor N Baud Divisor 6 2 BHD Baud Oupu Posiive Edge Delay 75 ns pf load BLD Baud Oupu Negaive Edge Delay 75 ns pf load HW Baud Oupu Up Time 75 ns f X = 8.MHz, +2, pf load LW Baud Oupu Down Time ns f X = 8.MHz, +2, pf load 4

5 GM6C55 AC Characerisics T A = C o + 7 C, V CC = 5V/3.3V Symbol Parameer Min Max Unis Condiions Receiver Delay from RD, RD (RD RBR/ or RINT RD LSR) o Rese Inerup SCD SINT Transmier µ s pf load Delay from RCLK o Sample Time 2 µ s Delay from Sop o Se Inerrup HR Delay from WR, WR (WR THR) To Rese Inerrup IR Delay from RD, RD (RD IIR) To Rese Inerrup (THRE) IRS SI STI SXV WXI Modem Conrol Delay from Iniial INTR Rese To Transmi Sar 8 24 Delay from Iniial Wrie o Inerrup 6 24 Delay from Sop o Inerrup (THRE) 8 8 Delay from Sar o TXRDY Acive 8 RCLK Cycles Noe 2 75 ns pf load 25 ns pf load Baudou Cycles Baudou Cycles Baudou Cycles Baudou Cycles Noe 5 Noe 5 pf load Delay from Wrie o TXRDY inacive 95 ns pf load MDO Delay from WR, WR (WR MCR) o Oupu 2 ns pf load RIM Delay o Rese Inerrup from RD, RD (RD MSR) 25 ns pf load SIM Delay o Se Inerrup from MODEM Inpu 25 ns pf load Noes. Applicable only when ADS is ied low. 2. In he FIFO mode (FCRO=) he rigger level inerrups, he receiver daa available indicaion, he acive RXRDY indicaion and he overrun error indicaion will be delayed 3 RCLKs. Saus indicaors (PE, FE, BI) will be delayed 3 RCLKs afer he firs bye has been received. For subsequenly received byes hese indicaors will be updaed immediaely afer RDRBR goes inacive. Timeou inerrup is delayed 8 RCLKs. 3. Change and discharge ime is deermined by VOL, VOH and he exernal loading. 4.In FIFO mode RC=425 ns (minimum) beween reads of he receiver FIFO and he saus regisers (inerrup idenifica ion regiser or line saus regiser). 5. This delay will be lenghened by characer ime, minus he las sop bi ime if he ransmier inerrup delay circui is acive (See FIFO Inerrup Mode Operaione) 5

6 GM6C55 Timing Waveforms (All imings are referenced o valid and valid) 2.4V XIN.4V Exernal Clock Inpu (8. MHz Max.) XH XL 2.2V.8V AT Tes Poins 2.4V 2.2V (Noe ) (Noe 2).8V.4V Noe : The 2.4V and.4v levels are he volages ha he inpus are driven o during AC esing. Noe 2: The 2.2V and.8v levels are he volages a which he iming ess are made. BAUDOUT Timing N XIN BAUD OUT ( ) BAUD OUT ( 2) BAUD OUT ( 3) BAUD OUT ( N.N > 3) BHD BLD BLD BLD BLD BHD HW BHD BHD HW LW LW HW LW HW LW =2 XIN CTLES = (N 2)XIN CYCLES 6

7 GM6C55 Timing Waveforms (Coninued) Wrie Cycle ADS ADS A2,A,A AS VALID AH CS CH WA* CS 2,CS,CS VALID SCW* AW* WR CSW* WC WC WR,WR OR RD,RD DS DH DATA DD7 VALID DATA *Applicable Only When ADS is Tied Low. Read Cycle ADS A2,A,A ADS AS AH VALID CS CH RA* CS 2,CS,CS VALID CSR* AR* RD RC RCS* RC RD,RD OR WR,WR RDD RDD DDIS DATA DD7 RVD VALID DATA HZ *Applicable Only When ADS is Tied Low. 7

8 GM6C55 Receiver Timing RCKK 8 CLKS SAMPLE CLK SIN RECEIVER INPUT DATA START DATA BITS(58) PARITY STOP SAMPLE CLK SINT INTERRUPT (DATA READY OR RCVR ERR DISTR /DOSTR (READ REC DATA BUFFER OR RDLSR) RIN Transmier Timing SERIAL OUT (SOUT) INTERRUPT (THRE) HR SI START DATA(5 irs MR PARITY STOP( START STI DISTR/DISTR (WR, THR) IR DISTR/DISTR MODEM Comrol Timing DISTR/DISTR (WR MCR) RTS. DTR OUT. OUT2 MDO MDO CTS. DSR. DCD INTERRUPT DISTR/DISTR (RD MSR) RI SIM RIM RIM SIM SIM Noe : See Wrie Cycle Timing Noe 2: See Read Cycle Timing 8

9 GM6C55 Timing Waveforms (coninued) RAVR FIFO Firs bye (This Ses RDR) SIN DATA (56) STOP SAMPLE CLOCK TRIGGER LEVEL INTERRUPT (FCR6,7 =.) NOTE 2 SINT RINT FIFO OR ABOVE TRIGGER LEVEL FIFO BELOW TRIGGER LEVEL LSI INTERRUPT RINT RD, RD (RDLS RD, RD (RDRBR) RCVR FIFO Bye Oher Than he Firs Bye (RDR is Already Se) SIN SAMPLE CLOCK TIMEOUT OR TRIGGER LEVEL INTERRUPT LSI INTERRUPT RD, RD (RDLSR) NOTE 2 SINT TOP BYTE OF FIFO SINT RINT RINT FIFO AT OR ABOVE TRIGGER LEVEL (FIFO BELOW TRIGGER LEVEL) RD, RD (RDRBR) PREVIOUS BYTE READ FROM FIFO Receiver Ready (pin 29) FCRO = or FCRO = and FCRO = 3 (Mode ) RD, RD (RDRBR) NOTE (FIRST BYTE) SIN STOP SAMPLE CLK RXRDY SINT NOTE 2 RINT Noe : This is he reading of he las bye in he FIFO Noe 2: If FCRO =, hen Tsin = 3 RCLKs. For a imeou SINT = RCLKs. 9

10 GM6C55 Timing waveforms (Coninued) Receiver Ready (pin 29) FCRO = or FCRO = and FCRO = (Mode ) RD, RD (RDRBR) NOTE (FIRST SIN STOP SAMPLE CLK RXRDY SINT NOTE 2 RINT Noe : This si he reading of he las bye in he FIFO Noe 2 : If FCRO =, Tsin = 3 RCLKs. RCVR FIFO Bye Oher Than Firs Bye (RDR is Already Se) WR, WR (WRTHR) BYTE SOUT DATA PARITY STOP START TXRDY WXI SXA Transmier Ready (pin 24) FCRO = and FCR = (Mode ) WR WR (WRTHR) BYTE 6 SOUT DATA PARITY STOP START TXRDY FIFO FULL WXI SXA

11 GM6C55 INTERNAL BLOCK DIAGRAM D7D (8) DATA BUS BUFFER INTERNAL DATA BUS S E L E C T RECEIVER BUFFER REGISTER RECEIVER FIFO RECEIVER SHIFT REGISTER () SIN (28) (27) LINE CONTROL REGISTER RECEIVER TIMING & CONTROL (9) RCLK (26) CSO CS CS2 ASD MR RD RD WR WR DDIS TXRDY XIN XOUT RXRDY (2) (3) (4) (25) (35) (22) (2) (9) 8 (23) (24) (6) (7) (29) SELENT & CONTROL LOGIC POWER SUPPLY { (4) (2) +5v GND DIVIOR LATCH(LS) DIVISOR LATCH(MS) LINE STATUS REGISTER TRANSTMTTER HOLDING REGISTER MODEM CONTROL REGISTER MODEM STATUS REGISTER INTERRUPT ENABLE REGISTER BAUD GENERATOR TRANSMITTER FIFO INTERRUPT CONTROL LOGIC S E L E C T RECEIVER TIMING & CONTROL TRANSTMTTER HOLDING REGISTER MONDEM CONTROL LOGIC (5) () (32) (36) (33) (37) (38) (39) (34) (3) (3) BAUDIUT SOUT RTS CTS DTR DSR DCD R OUT OUT2 INTR INTERRUPT ID REGISER FIFO CONTROL REGISTER

12 GM6C55 Pin Descripions The following describes he funcion of all UART pins. Some of hese descripions reference inernal circuis. In he following descripions, a low represens a logic (V nominal) and a high represens a logic (+2.4V nominal). INPUT SIGNALS Chip Selec (CS, CS, CS 2 ) Pins 24: When CS and CS are high and CS 2 is low, he chip is seleced. This enable communicaion beween he UART and he CPU. The posiive edge of an acive Address Srobe signal laches he decoded chip selec signals, compleing chip selecion. If ADS is always low, valid chip selecs should sabilize according o he CSW parameer. Read (RD, RD ), Pins 22 and 2: When Rd is high or RD is low while he chip seleced, he CPR can read saus informaion or daa from he seleced UART regiser. Noe: Only an acive RD or RD inpu is required o ransfer daa from he UART during a read operaion. Therefore ie eiher he RD inpu permanenly low or he RD inpu permanenly high, when i is no used. Wrie (WR, WR ), Pin 9 and 8: When WR is high or WR is low while he chip seleced, he CPU can wrie conrol words or daa ino he seleced UART regiser. Noe: Only an acive WR or WR inpu is required o ransfer daa o he UART during a wrie operaion. Therefore, ie eiher he WR inpu permanenly low or he WR inpu permanenly high, when i is no used. Address Srobe ( ADS ), Pin 25: The posiive edge of an acive Address Srobe ( ADS ) signal laches he Regiser Selec (A, A, A2) and Chip Selec (CS, CS, CS2) signals. Noe: An acive ADS inpu is required when he Regiser Selec (A, A, A2) signals are no sable for he duraion of a read or a wrie operaion. If no required, ie he ADS inpu permanenly low. Regiser Selec (A, A, A2), Pins 2628: Address signals conneced o hese 3 inpus selec a UART regiser for he CPU o read from or wrie o during daa ransfer. A able of regisers and addresses is shown below. Noe ha he sae of he Divisor Lach Access Bi (DLAB), which is he mos significan bi of he Line Conrol Regiser, affecs he selecion of cerain UART regisers. The DLAB mus be se high by he sysem sofware o access he Baud Generaor Divisor Laches. Maser Rese (MR), Pin 35: When his inpu is high i clears all he regisers (excep he Receiver Buffer, Transmier Holding, and Divisor Laches), and he conrol logic of he UART. The sae of various oupu signals (SOUT, INTR, OUT, OUT 2, RTS, DTR) are affeced by an acive MR inpu (Refer o Table ). This inpu is buffered wih a TTLcompaible Schmi Trigger wih.5v ypical hyseresis. Receiver Clock (RCLK), Pin 9: This inpu is he 6 X baud rae clock for he receiver secion of he chip. Ring Indicaor ( RI ), Pin 39: When low, his indicaes ha a elephone ringing signal is received by he MODEM or daa se. The RI signal is a MODEM saus inpu Regiser Address DLAB A 2 A A Regiser Receiver Buffer (read) Transmier Holding Regiser (Wrie) Inerrup Enable Inerrup Idenificaion (read) FIFO Conrol (Wrie) Line Conrol MODEM Conrol Line Saus MODEM Saus Scrach Divisor Lach (leas significan bye) Divisor Lach (mos significan bye) Serial Inpu (SIN), Pin : Serial daa inpu from he communicaions link (peripheral device, MODEM, or daa se). Clear o Send ( CTS ), Pin 36: When low, his indicaes ha he MODEM or daa se is ready o exchange daa. The CTS signal is a MODEM saus inpu whose condiions can be esed by he CPU reading bi 4 (CTS) of he MODEM Saus Regiser. Bi 4 is he complemen of he CTS signal. Bi (DCTS) of he MODEM Saus Regiser indicaes wheher he CTS inpu has changed sae since he previous reading of he MODEM Saus Regiser. CTS has no effec on he Transmier. Noe: Whenever he CTS bi of he MODEM Saus Regiser changes sae, an inerrup is generaed if he MODEM Saus Inerrup is enabled. Daa Se Ready ( DSR ), Pin 37: When low, his indicaes ha he MODEM or daa se is ready o esablish he communicaions link wih he UART. The DSR signal is a MODEM saus inpu whose condiion can be esed by he CPU reading bi 5 (DSR) of he MODEM Saus Regiser. Bi 5 is he complemen of he DSR signal. Bi (DDSR) of he MODEM Saus Regiser indicaes wheher he DSR inpu has changed sae since he previous reading of he MODEM Saus Regiser. Noe: Whenever he DSR bi of he MODEM Saus Regiser changes sae, an inerrup is generaed if he MODEM Saus inerrup is enabled. Daa Carrier Deec ( DCD ), Pin 38: When low, indicaes ha he daa carrier has been deeced by he MODEM or daa se. The DCD signal is a MODEM saus inpu whose condiion can be esed by he Regiser. Bi 7 is he complemen of he DCD signal. Bi 3 (DDCD) of he MODEM Saus Regiser indicaes wheher he DCD inpu has changed sae since he previous reading of he MODEM Saus Regiser. DCD has no effec on he receiver. Noe: Whenever he DCD bi of he MODEM Saus Regiser changes sae, an inerrup is generaed if he MODEM Saus Inerrup is enabled. whose condiion can be esed by he CPU reading bi 6 ( RI ) of he MODEM Saus Regiser. Bi 6is he complemen of he RI signal. Bi 2 (TERI) of he MODEM 2

13 GM6C55 Saus Regiser indicaes wheher he RI inpu signal has changed from a low o a high sae since he previous reading of he MODEM Saus Regiser Noe : Whenever he RI bi of he MODEM Saus Regiser changes from a high o a low sae, an inerrup is generaed if he MODEM Saus Inerrup is enabled. Vcc, Pin 4 : +5V supply. Vss, Pin 2 : Ground(V) reference. OUTPUT SIGNALS Daa Terminal Ready ( DTR ), Pin 33: When low, his informs he MODEM or daa se ha he UART is ready o esablish communicaions link. The DTR oupu signal can be se o an acive low by programming bi (DTR) of he MODEM Conrol Regiser o high level. A Maser Rese operaion ses his signal o is inacive (high) sae. Loop mode operaion holds his signal in is inacive sae. Reques o Send ( RTS ), Pin 32: When low, his informs he MODEM and daa se ha he UART is ready o exchange daa. The RTS oupu signal can be se o an acive low by programming bi (RTS) of he MODEM Conrol Regiser. A Maser Rese operaion ses his signal o is inacive sae. Loop node operaion holds his signal in is inacive sae. Oupu ( OUT ), Pin 34: This userdesigned oupu can be se o an acive low by programming bi 2 (OUT) of he MODEM Conrol Regiser o a high level. A Maser Rese operaion ses his signal o is inacive sae. Loop Mode operaion holds his signal o is inacive sae. Oupu 2 ( OUT 2 ), Pin 3: This userdesignaed oupu can be se o an acive low by programming bi 3 (OUT2) of he MODEM Conrol Regiser o a high level. A Maser Rese operaion ses his signal o is inacive (high) sae. Loop mode operaion holds his signal o is inacive sae. TXRDY, RXRDY, Pin 24, 29: Transmier and Receiver DMA signaling is available hrough wo pins (24 and 29). When operaing in he FIFO mode, one of wo ypes DMA signaling per pin can be seleced via FCR3, When operaing as in he GM6C645 Mode., only DMA Mode is allowed. Mode suppors single ransfer DMA where a ransfer is made beween CPU bus cycles. Mode suppors muliransfer DMA where muliple ransfers ard made coninuously unil he RCVR FIFO has been empied or he XMIT FIFO has been filled. RXRDY Mode : When in he GM6C45 Mode (FCR = ) or in he FIFO Mode (FCRO =, RCR3 = ) and here is a leas characer in he RCVR FIFO of RCVR holding regiser, he RXRDY pin (29) will be low acive. Once i is acivaed he RXRCY pin will go inacive when here are no more characers in he FIFO of holding regiser. RXRDY Mode : In he FIFO Mode (FCR = ) when he FRC3 = and he rigger level or he imeou has been reached, he RXRDY pin will go low acive. Once i is acivaed i will go inacive when here are no more characers in he FIFO or holding regiser. TXRDY Mode : in he GM6C45 Mode (FCR = ) or in he FIFO Mode (FCR =, FCR3 = ) and here are no characers in he XMIT FIFO or XMIT hold regiser, he TXRDY pin(24) will be low acive. Once i is acivaed he TXRDY pin will go inacive afer he firs characer is loaded ino he XMIT FIFO or holding regiser. TXRDY Mode : In he FIFO Mode (FCR = ) when FCR3 = and here is a leas one unfilled posiion in he XMIT FIFO, i will go low acive. This pin will become inacive when he XMIT FIFO is compleely full. Driver Disable (DDIS), Pin 23: his goes low whenever he CPU is reading daa from he UART. I can disable or conrol he direcion of a daa bus ransceiver beween he CPU and he UART. Baud Ou ( BAUDOUT ), Pin 23: This is he 6X clock signal from he ransmier secion of he UART. The clock rae is equal o he main reference oscillaor frequency divided by he specified divisor in he Baud Generaor Divisor Laches. The BAUDOUT may also be used for he receiver secion by ying his oupu o he RCLK inpu of he chip. Inerrup (INTR), Pin 3: This pin goes high whenever any one of he following inerrup ypes has an acive high cogniion and is enabled via he IER; Receiver Error Flag; Received Daa Available; imeou (FIFO Mode only); Transmier Holding Regiser Empy; and MODEM Saus, The INTR signal is rese low upon he appropriae inerrup service or a Maser Rese operaion. Serial oupu (SOUT), Pin : Composie serial daa oupu o he communicaions link (peripheral. MODEM or daa se). The SOUT signal is se o he Marking (logic ) sae upon a Maser Rese operaion. INPUT / OUTPUT SIGNALS Daa (D7D) Bus, Pin 8: This bus comprises eigh TRIsae inpu/oupu lines. The bus provides bidirecional communicaions beween he UART and he CPU, Daa, conrol words. And saus informaion are ransferred via he D7D Daa Bus. Exernal Clock Inpu/Oupu (XIN, XOUT), Pins 6 and 7: These wo pins connec he main iming reference (crysal or signal clock) o he UART. 3

14 GM6C55 TABLE I. UART Rese Configuraion Regiser / Signal Rese Conrol Rese Sae Inerrup Enable Regiser Inerrup Idenificaion Regiser FIFO Conrol Line Conrol Regiser MODEM Conrol Regiser Line saus Regiser MODEM Saus Regiser SOUT INTR (RCVR Errs) INTR (RCVR Daa Ready) INTR (THRE) INTR (Modem Saus Changes) OUT 2 RTS DTR OUT RCVR FIFO XMIT FIFO Noe : Boldface bis are Permanenly low. Noe 2 : Bis 74 are driven by he inpu signals. Maser Rese Maser Rese Maser Rese Maser Rese Maser Rese Maser Rese Maser Rese Maser Rese Read LSR/MR Read RBR/MR Read IIR/Wrie THR/MR Read MSR/MR Maser Rese Maser Rese Maser Rese Maser Rese MR/RCRFCR/ FCR MR/RCRFCR/ FCR (Noe ) xxxx (Noe 2) High Low Low Low Low High High High High All Bis Low All Bis Low 4

15 GM6C55 TABLE II. Summary of Regise rs Bi Regiser Address No. DLAB = DLAB = DLAB = Receiver Buffer Regiser (Read Only) Transmier Holding Regiser (Wrie Only) Inerrup Enable Regiser Inerrup Enable Regiser FIFO Conrol Regiser (Wrie Only) Line Conrol Regiser MODEM Conrol Regiser Line Saus Regiser RBR THR IER IIR FCR LCR MCR LSR Daa bi Daa bi Enable Received Daa Available Inerup (ERBFI) if Inerrup Pending FIFO Enable Word Lengh Selec Bi (WLS) Daa Terminal Ready (DTR) Daa Ready (DR) Daa bi Daa bi Enable Transmier Holding Regiser Empy Inerrup (ETBEI) Inerrup ID Bi () RCVR FIFO Rese Word Lengh Selec Bi (WLS) Reques o Send (RTS) Overrun Error (OE) Daa bi 2 Daa bi 3 Daa bi 4 Daa bi 5 Daa bi 2 Daa bi 3 Daa bi 4 Daa bi 5 Enable Receiver Line Saus Enable MODEM Saus Inerrup (EDSSI) Inerrup ID Bi () Inerrup ID Bi (2) (Noe 2) XMIT FIFO Rese DMA Mode selec Reserved Reserved Number of Sop Bis (STB) Pariy Enable (PEN) Even Pariy Selec (EPS) Sick Pariy Ou Ou2 Loop Pariy Error (PE) Framing Error (FE) Break Inerrup (BI) Transmier Holding Regiser (THRE) 6 Daa bi 6 Daa bi 6 FIFO3 enabled (noe 2) RCVR Trigger (LSB) Se Break Transmier Empy (TEMT) 7 Daa bi 7 Daa bi 7 FIFO3 enabled (noe 2) RCVR Trigger (MSB) Divisor Lach Access Bi (DLA3) Error in RCBR FIFO (Noe2) Noe : Bi is he leas significan bi seriously ransmied or received Noe 2:hese bis are always in he GM6C45 Mode 6 MODEM Saus Regiser MSR Dela Clear To Send (DCTS) Dela Daa Se Ready (DDSR) Trading Edge Ring Indicaor (TERI) Dela Daa Camer Delec (DDCD) Clear o Send (CTS) Daa Se Ready (DSR) Ring Indicaor (RI) Daa Camer Deec (DCD) 7 Scrach Regiser SCR Bi Bi Bi 2 Bi 3 Bi 4 Bi 5 Bi 6 Bi 7 DLAB = Divisor Lach (LS) DLL Bi Bi Bi 2 Bi 3 Bi 4 Bi 5 Bi 6 Bi 7 DLAB = Divisor Lach (MS) DLM Bi 8 Bi 9 Bi Bi Bi 2 Bi 3 Bi 4 Bi 5 5

16 GM6C55 Regisers The sysem programmer may be Access any of he UART regisers summarized in Table II via he CPU. These regisers conrol UART operaions including ransmission and recepion of daa. Each regiser bi in Table II has is name and rese sae shown. LINE CONTROL REGISTER The sysem programmer specifies he forma of he asynchronous daa communicaions exchange and se he Divisor Lach Access bi via he Line Conrol Regiser (LCR). The programmer can also read he conens of he Line Conrol Regiser. The read capabiliy simplifies sysem programming and eliminaes he need for separae sorage in sysem memory of he LCR. Deails on each bi follow: Bi and : These wo bis specify he number of bis in each ransmied or received serial characer. The encoding of bis and is as follows. Bi Bi Characer Lengh 5 Bis 6 Bis 7 Bis 8 Bis Bi 2: This bi specifies he number of Sop bis ransmied and received in each serial characer. If bi 2 is a logic, one Sop bi is generaed in he ransmied daa. If Bi 2 is a logic when a 5bi word lengh is seleced via bis and, one and a half Sop bis are generaed. If bi 2 is a logic When eiher a 6, 7, or 8 bi word lengh is seleced, wo Sop bi are generaed. The Receiver checks he firs Sop bi only, regardless of he number of Sop bi seleced. Bi 3: This bi is he Pariy Enable bi. When bi 3 is a logic, a Pariy bi is generaed (ransmi daa) or checked (receive daa) beween he las daa word bi and Sop bi of he serial daa. (The Pariy bi is used o produce an even or odd number of s when he daa word bis and he Pariy bi are summed). Bi 4: This bi is he Even Pariy Selec bi. When bi 3 is a logic and bi 4 is a logic, and odd number of logic s is ransmied or checked in he daa word bis and Pariy bi. When bi 3is a logic and i 4 is a logic, an even number of logic s is ransmied or checked. Bi 5: This bi is he Sick Pariy bi. When bi3, 4 and 5 are logic he Pariy bi is ransmied and checked as a logic. If bi 3 and 5 are and bi 4 is a logic hen he Pariy bi is ransmied and checked as a logic. If bi 5 is a logic Sick Pariy is disabled. Bi 6: This bi is he Break Conrol bi. I causes a break condiion o be ransmied o he received UART. When i is se o logic, The serial oupu (SOUT) is forced o he Spacing (logic ) sae. The break is disabled by seing bi 6 o a logic. The Break Conrol bi acs only on SOUT and has no effec on he ransmied logic. Noe : This feaure enables he CPU o aler a erminal in during he break. The Transmier can be used as a characer imer o accuraely esablish he break duraion. a compuer communicaions sysem. If he following sequence is followed. no erroneous or exraneous characers will be ransmied because of he break.. Load on all Os, pad characer, in response o THRE. 2. Se break afer he nex THRE 3. Wai for he ransmier o be idle. (TEMT = ), and clear break when normal ransmission has o be ired. During he bread, he Transmier can be used as a characer imer o accuraely esablish he break duraion. Bi 7: This bi is he Divisor Lach Access Bi (DLAB). I mus be se high (logic) o access he Divisor Laches of he Baud Generaor during a Read or Wrie operaion. I mus be se low (logic ) o access he Receiver Buffer, he Transmier Holding Regiser, or he Inerrup Enable Regiser. Typical Clock Circuis VCC VCC EXTERNAL CLOCK DRIVER XIN C XIN OPTIONAL OPTIONAL DRIVER CLOCK OUTPUT XOUT OSC CLOCK TO BAUD GEN. LOGIC R P C2 CRYSTAL R 2 XOUT OSC CLOCK TO BAUD GEN. LOGIC 6

17 GM6C55 Typical Crysal Oscillaor Nework Crysal R P R 2 C C 2 3.MHz MΩ.5k 3pF 46pF.8MHz MΩ.5k 3pF 46pF TABLE III. Baud Raes Using.8432 MHz Crysal Desired Baud Rae Decimal Divisor Used o Generae 6 Clock Percen Error Difference Beween Desired and Acual

18 GM6C55 TABLE IV. Baud Raes Using 3.72 MHz crysal Desired Baud Rae Decimal Divisor Used o Generae 6 Clock Percen Error Difference Beween Desired and Acual TABLE V. Baud Rae Using 8MHz Crysal Desired Baud Rae Decimal Divisor Used o Generae 6 Clock Percen Error Difference Beween Desired and Acual

19 GM6C55 TABLE VI.. Inerrup Conrol Funcions FIFO Mode Only Inerrup Idenificaion Bi 3 Bi 2 Bi Bi Priori y Level Inerrup Type None Highes Receiver Line Saus Second Received Daa Available Second Characer Timeou Indicaion Third Transmier Holding Regiser Empy Fourh MODEM Saus Inerrup Se and Rese Funcion Inerrup Source None Overrun Error or Pariy Error or Framing Error or Break Inerrup Receiver Daa Available or Trigger Level Reached No Characers Have Been Removed From or Inpu o he RCVR FIFO During he Las 4 char. Times and There is a Leas char. In i During This Time Transmier Holding Regiser Empy Clear o Send or Daa Se Ready or Ring Indicaor or Daa Carrier Deec Inerrup Rese Conrol Reading he Line Saus Regiser Reading he Receiver Buffer Regiser or he FIFO Drops Below he Trigger Level Reading he Receiver Buffer Regiser Reading he IIR Regiser (if Source of inerrup) or Wriing ino he Transmier Holding Regiser Reading he MODEM Saus Regiser 9

20 GM6C55 PROGRAMMABLE BAUD GENERATOR The UART conains a programmable Baud Generaor ha is capable of aking any clock inpu from 2 o MHz is he highes inpu clock frequency recommended when he divisor =. The oupu frequency of he Baud Generaor is 6 he Baud [divisor # = (frequency inpu) (baud rae 6)] Two 8bi laches sore he divisor in a 6bi binary forma. These Divisor Laches mus be loaded during iniializaion o ensure proper operaion of he Baud Generaor. Upon loading eiher or he Divisor Laches, a 6bi Baud couner is immediaely loaded. Tables III, IV and V provide decimal divisors o use wih crysal frequencies of.8432 MHz 3.72MHz and 8 MHz, respecively. For baud raes of 384 and below, he error obain is minimal. The accuracy of he desired baud rae is dependen on he crysal frequency chosen. Using a divisor of zero is no recommended. LINE STATUS REGISTER This regiser provides saus informaion o he CPU concerning he daa ransfer. Table II shows he conens of he Line Saus Regiser. Deails on each bi follow. Bi : This bi is he receiver Daa Ready (DR) indicaor. Bi is se o logic whenever a complee incoming characer has been received and ransferred ino he Receiver Buffer Regiser or he FIFO. Bi is rese o a logic by reading all of he daa in he Receiver Buffer Regiser or he FIFO. Bi : This bi is he Overrun Error (OE) indicaor. Bi indicaes ha daa in he Receiver Buffer Regiser was no read by he CPU before he nex characer was ransferred ino he Receiver Buffer Regiser, hereby desroying he previous characer. The OE indicaor is se o a logic upon deecion of an overrun condiion and rese whenever he CPU reads he conens of he Line Saus Regiser If he FIFO mode daa coninues o fill he FIFO beyond he rigger level, An overrun error will occur only been compleely received in he shif regiser. OE is indicaed o he CPU as soon as i happens. The characer on he shif regiser is overwrien, bu is no ransferred o he FIFO. Bi 2: This bi is he Pariy Error (PE) indicaor. Bi 2 indicaes ha he received daa characer does no have he correc even or odd pariy. As seleced by he even pariyselec bi. The PE bi is se o a logic upon deecion of a pariy error and is rese o a logic whenever he CPU reads he conens of he Line Saus Regiser. In he FIFO mode his error is associaed wih he paricular characer in he when is associaed characer is a he op of he FIFO. Bi 3: This bi is he Framing Error (FE) indicaor. Bi3 indicaes ha he received characer did no have a valid Sop bi. Bi 3is se o logic whenever he Sop bi following he las daa bi or pariy bi is deeced as a logic bi (Spacing level). The FE indicaor is rese whenever he CPU reads he conens of he Line Saus Regiser. In he FIFO mode his error is associaed wih he paricular characer in he FIFO i applies o. This error is revealed o he CPU when is associaed characer is a he op of he FIFO. The UART will ry o resynchronize afer a framing error. To do his i assumes ha he framing error was due o he nex sar bi so i samples his sar bi wice and hen akes in he daa. Bi 4: This bi is he Break Inerrup (BI) indicaor. Bi 4 is se o a logic when ever he received daa inpu is held in he spacing (logic) sae for longer han a full word ransmission ime (ha is, he oal ime of Sar Bi + daa bis + Pariy + Sop bis). The BI indicaor is rese whenever he CPU reads he conens of he line Saus Regiser. In he FIFO mode his error is associaed wih he paricular characer in he FIFO i applies o. This error is revealed o he CPU when is associaed characer is a he op of he FIFO. When break occurs only one zero characer is loaded ino he FIFO. The nex characer ransfer is enabled afer SIN goes o he marking sae and receives he nex valid sar bi. Noe: Bis hrough 4 are he error condiions ha produce a Receiver Line Saus inerrup whenever any of he corresponding condiions are deeced and he inerrup is enabled. Bi 5: This bi is he Transmier Holding Regiser Empy (THRE) indicaor. Bi 5 indicaes ha he UART is ready o accep a new characer for ransmission. In addiion, his bi causes he UART o issue an inerrup o he CPU when he Transmi Holding Regiser Empy Inerrup enable is se high. The THRE bi is se o logic when a characer is ransferred from he Transmier Holding Regiser ino he Transmier Shif Regiser. The bi is rese o logic concurrenly wih he loading of he Transmier Holding Regiser by he CPU, In he FIFO mode his bi is se when he XMIT FIFO is empy; i is cleared when a leas bye is wrien o he XMIT FIFO. Bi 6: This bi is he Transmier Empy (TEMT) indicaor. Bi 6 is se o a logic whenever he Transmier Holding Regiser (THR) and he Transmier shif regiser (TSR) are boh empy. I is rese o a logic whenever eiher he THR or TSR conains a daa characer. In he FIFO mode his bi is se o one whenever he ransmier FIFO and shif regiser are boh empy. Bi 7: in he GM6C45 Mode his is a. In he FIFO mode LSR7 is se when here is leas one pariy error, framing error or break indicaion in he FIFO. LSR7 is cleared when he CPU reads he LSR, if here are no subsequen errors in he FIFO. Noe: The Line Saus Regiser is inended for read operaions only. Wriing o his regiser is no recommended as his operaion is only used for facory esing. FIFO CONTROL REGISTER This is a wrie only regiser a he same locaion as he IIR (he IIR is a read only regiser). This regiser is used o enable he FIFOs, se he RCVR FIFO rigger level, and selec he ype of DMA signaling. 2

21 GM6C55 Bi : Wriing a o FCR enables boh he XMIT and RCVR FIFOs. Reseing FCR will clear all byes in boh FIFOs. When changing from FIFO Mode o GM6C45 Mode and vice versa, daa is auomaically cleared from he FIFOs. This bi mus be a when oher RCR bis are wrien o or hey will no be programmed. Bi : Wriing a o FCR clears all byes in he RCVR FIFO and reses is couner logic o. The shif regiser is no cleared. The ha is wrien o his bi posiion is selfclearing. Bi 2: Wriing a o FCR2 clears all byes in he XMIT FIFO and reses is couner logic o. The shif regiser is no cleared. The ha is wrien o his bi posiion is selfclearing. Bi 3: Seing FCR 3 o a will cause he RXRDY and TXRDY pins o change from mode o mode if FCR = (see descripion of RXRDY and TXRDY pins). Bi4, 5: FCR4 o FCR5 are reserved for fuure use. Bi6, 7: FCR6 o FCR7 are used o se he rigger level for he RCVR FIFO inerrup. 7 6 INTERRUPT IDENTIFICATION REGISTER RCVR FIFO Trigger Level (Byes) In order o provide minimum sofware overhead during daa characer ransfers, he UART prioriizes inerrups ino four levels and records hese in he inerrup Idenificaion Regiser. The four levels of inerrup condiions in order of prioriy are Receiver Line Saus; Received Daa Ready; Transmier Holding Regiser Empy; and MODEM Saus. When he CPU accesses he IIR, he UART freezes all inerrups and indicaes he highes prioriy pending inerrup o he CPU. While his CPU access is occurring, he UART records niw inerrups, bu access is complee. Table II shows he conens of he IIR. Deails on each bi follow: Bi : This bi can be used in a prioriized inerrup environmen o indicae wheher an inerrup is pending. When bi is a logic, an inerrup is pending and he IIR conens may be used as a poiner o he appropriae inerrup service rouine. When bi is a logic, no inerrup is pending. Bi and 2: These wo of he IIR are used o idenify highes prioriy inerrup pending as indicaed in Table VI. Bi 3: In he GB6C45 Mode his bi is. In he FIFO mode his bi is se along wih bi 2 when a imeou inerrup is pending. Bi 4 and 5: These wo bis of he IIR are always logic. Bi 6 and 7: These wo bis are se when FCR =. INTERRUPT ENABLE REGISTER This regiser enables he five ypes of UART inerrups. Each inerrup can individually acivae he inerrup (INTR) oupu signal. I is possible o oally disable he inerrup sysem by reseing bis hrough 3 of he Inerrup Enable Regiser (IER). Similarly, seing bis of he IER regiser o a logic, enables he seleced inerrup(s). Disabling an inerrup prevens i from being indicaed as acive in he IIR and from acivaing he INTR oupu signal. All oher sysem funcions operae in heir normal manner, including he seing of he Line Saus and MODEM Saus Regisers. Table II shows he conens of he IER. Deails on each bi follow. Bi : This bi enables he Received Daa Available Inerrup (and imeou inerrups in he FIFO mode) when se o logic. Bi 2: This bi enables he Receiver Line Saus inerrup when se o logic Bi 3: This bi enables he MODEM Saus inerrup when se o logic Bi 4 hrough 7: These four bis are always logic. MODEM CONTROL REGISTER This regiser conrols he inerface wih he MODEM or daa se (or peripheral device emulaing a MODEM). The conens of he MODEM Conrol Regiser are indicaed in Table II and are described below. Bi : This bi conrols he Daa Terminal Ready (DTR) oupu. When bi is se o a logic, he DTR oupu is forced o a logic. When bi is rese o a logic, he DTR oupu is forced o a logic. Noe: The DTR oupu of he UART may be applied o an EIA invering line driver (such as he GD75 88) o obain he proper polariy inpu a he succeeding MODEM or daa se. Bi : This bi conrols he Reques o Send (RTS) oupu. Bi affecs he RTS oupu in a manner idenical o ha described above for bi. Bi 2: This bi conrols he oupu (OUT) signal, which is an auxillary userdesignaed oupu. Bi 2 affecs he OUT oupu in a manner idenical o ha described above for bi. Bi 3: This bi conrols he oupu 2(OUT2) signal, which is an auxillary userdesignaed oupu. Bi 3 affecs he OUT2 oupu in a manner idenical o ha described above for bi. Bi 4: This bi provides a local loopback feaure for Diagnosic esing of he UART. When bi 4 is se o logic, he following occur ; he ransmier Serial oupu (SOUT) is se o he Marking (logic ) Sae; he receiver Serial Inpu (SIN) is disconneced; he oupu of he Transmier Shif 2

22 GM6C55 Regiser is looped back ino he Receiver Shif Regiser inpu; he four MODEM Conrol inpus ( CTS, RTS, RI, and DCD ) are disconneced; and he four MODEM Conrol oupus ( DTR, RTS, OUT and OUT 2 ) are inernally conneced o he four MODEM Conrol inpus, and he MODEM Conrol oupu pins are forced o heir inacive sae (high). In he diagnosic mode, daa ha is ransmied is immediaely received. This feaure allows he processor o verify he ransmier and receiveddaa pahs of he UART. In he diagnosic mode, he receiver and ransmier inerrups are fully operaional. Their sources are exernal o he par. The MODEM Conrol Inerrups are also operaional, bu he inerrups sources are now he lower four bis or he MODEM Conrol inpus. The inerrups are sill conrolled by he Inerrup Enable Regiser. Bis 5 hrough 7: These bis are permanenly se o logic. MODEM STATUS REGISTER This regiser provides he curren sae of he conrol lines from he MODEM (or peripheral device) o he CPU. In addiion o his currensae informaion, four bis of he MODEM Saus Regiser provide change informaion. These bis are se o a logic Whenever a conrol inpu from he MODEM changes sae. They are rese o logic whenever he CPU reads he MODEM Saus Regiser. The conens of he MODEM Saus Regiser are indicaed in Table II and described below. Bi : This bi is he Dela Clear o Send (DCTS) indicaor. Bi indicaes ha he CTS inpu o he chip has changed sae since he las ime i was read by he CPU. Bi : This bi is he Dela Daa Se Ready (DDSR) indicaor. Bi indicaes ha he DSR inpu o he chip has changed sae since he las ome i was read by he CPU. Bi 2: This bi is he Trailing Edge of Ring Indicaor (TERI) deecor. Bi 2 indicaes ha he RI inpu o he chip has changed from a low o a high sae. Bi 3: This bi is he Dela Daa Carrier Deec (DDCD) indicaor. Bi 3 indicaes ha he DCD inpu o he chip has changed sae. Noe: Whenever bi,, 2 or 3 is se o logic, a MODEM Saus Inerrup is generaed. Bi 4: This bi is he complemen of he Clear o Send ( CTS ) inpu. If bi 4(loop) of he MCR is se o a, his bi is equivalen o RTS in he MCR. Bi 5: This bi is he complemen of he Daa Se Ready ( DSR ) inpu. If Bi 4 of he MCR is se o a, his bi is equivalen o DTR in he MCR. Bi 6: This bi is he complemen of he Ring Indicaor. ( RI ) inpu. If bi 4 of he MCR is se o a, his bi is equivalen o OUT in he MCR. Bi 7: This bi is he complemen of he Daa Carrier Deec(DCD) inpu. If bu 4 of he MCR is se o a, his bi is equivalen o ou2 in he MCR. SCRATCHPAD REGISTER This 8bi Read/Wrie Regiser does no conrol he UART in anyway. I is inended as a scrachpad regiser o be used by he programmer o hold daa emporarily. FIFO INTERRUPT MODE OPERATION When he RCVR FIFO and receiver inerrups are enabled (FCR =, IER =) RCVR inerrups will occur as follows: A. The receive daa available inerrups will be issued o he CPU when he FIFO has reached is programmed rigger level; i will be cleared as soon as he FIFO drops below is programmed rigger level. B. The IIR receive daa available indicae also occurs when he FIFO rigger level is reached, and like he inerrup i is cleared when he FIFO drops below he rigger level. C. The receiver line saus inerrup (IIR6), as before, has higher prioriy han received daa available (IIR4) inerrup. D. The daa ready bi (LSR)is se as soon as a characer is ransferred from he shif regiser o he RCVR FIFO. I is rese when he FIFO is empy. When RCVR FIFO and receiver inerrups are enabled, RCVR FIFO imeou inerrups will occur as follows: A. A FIFO imeou inerrup will occur, if he following condiions exis: a leas one characer is in he FIFO he mos recen serial characer received was longer han 4 coninuous characer imes ago (if 2 sop bis are programmed he second one is included in his ime delay). The mos recen CPU read if he FIFO was longer han 4coninuous characer imes age. This will cause a maximum characer received o inerrup issued delay of 6ms a 3BAUD wih a 2 bi characer. B. characer imes are calculaed by using he RCLK inpu for a clock signal (This makes he delay proporional o he baudrae). C. When a imeou inerrup has occurred i is cleared and he imer res when he CPU reads one characer from he RCVR FIFO. D. When a imeou inerrup has no occurred he imeou imer is rese afer a new characer is received or afer he CPU reads he RCVR FIFO. When he XMIT FIFO and ransmier inerrups are enabled (FCR=, IER=) XMIT inerrups will occur as follows: A. The ransmier holding regiser inerrup (2) occurs when he XMIT FIFO is empy; i is cleared as soon as he ransmier holding regiser is wrien o ( o 6 characers may be wrien o he XMIT FIFO while servicing his inerrup) or he IIR is read. 22

23 GM6C55 The ransmier FIFO empy indicaions will be delayed characer ime minus he las sop bi ime whenever he following occurs: THRE = and here have no been a leas wo byes a he same ime in he ransmi FIFO, since he las THRE =. The firs ransmier inerrup affec changing FCR will be immediae, if i is enabled. Characer imeou and RCVR FIFO rigger level inerrups have he same prioriy as he curren received daa available inerrup; XMIT FIFO empy has he same prioriy as he curren ransmier holding regiser empy inerrup. FIFO POLLED MODE PRERATION Wih FCRQ = reseing IER, IER, IER2, IER3 or all o zero pus he RCVR and MITTER are conrolled separaely eiher one or boh can be in he polled mode of operaion. In his mode he user s program will check RCVR and XMITTER saus via he LSR. As saed previously: LSR will be se as long as here is one bye in he RCR FIFO. LSR o LSR4 will specify which error(s) has occurred. Characer error saus is handled he same way when in he inerrup mode, he IIR is no affeced since IER2=. LSR5 will indicae when he XMIT FIFO is empy. LSR6 will indicae ha boh he XMIT FIFO and shif regiser are empy. LSR7 will indicae wheher here are any errors in he RCVR FIFO. There is no rigger level reached or imeou condiion indicaed in he FIFO polled Mode, however, he RCVR and XMIT FIFOs sill fully capable of holding characers. Applicaion Circui SYSTEM BUS A A23 LATCH A A2 XTAL ADDRESS DECODER CS2 XTAL2 CPU RESET +5 CS CS MR GM6C55 RCLK SOUT SIN D D5 DATA BUFFER D D7 D D7 RST DTR DSR EIA DRIVERS RS232C D INTERFACE OR CW DISTR DOSTR DISTR DOSTR ADS DCD CTS RI INTRPT TXRDY DDIS RXRDY DD5 23