DS Bit, Programmable, 100kHz Pulse-Width Modulator

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1 FEUE ingle 5-bi, programmable, pulse-widh modulaor (PWM) djusable Duy Cycle: 0% o 100% 2.7V o 5.5V Operaion andard Frequency Value: 100kHz 2-Wire ddressable Inerface Packages: 8-Pin (150-mil) OIC and 8-Pin (118-mil) OP Operaing emperaure: -40 o C o +85 o C ODEING INFOMION D1052Z kHz 8-Pin 150-mil OIC D1052U kHz 8-Pin 118-mil OP D Bi, Programmable, 100kHz Pulse-Widh Modulaor PIN IGNMEN CL D 0 GND PIN DECIPION V CC V CC - 2.7V o 5.5V Power upply PWM O - PWM Oupu 0, 1, 2 - Device ddress D - erial Daa I/O CL - erial Clock Inpu GND - Ground Pin 150-mil OIC 8-Pin 118-mil OP PWM DECIPION he D1052 is a programmable, 5-bi, pulse-widh modulaor feauring a 2-wire addressable conrolled inerface. he D1052 operaes from power supplies ranging from 2.7V up o 5.5V. he PWM oupu provides a signal ha swings from 0V o V CC. he D requires a ypical operaing curren of 100µ and a programmable shudown supply curren of 1µ. One sandard PWM oupu frequency is offered: 100kHz. he 2-wire addressable inerface allows operaion of muliple devices on a single 2-wire bus and provides compaibiliy wih oher Dallas emiconducor 2-wire devices such as real-ime clocks (Cs), digial hermomeers, and digial poeniomeers. he device is ideal for low-cos LCD conras and/or brighness conrol, power supply volage adjusmen, and baery charging or curren adjusmen. he D1052 is offered in sandard inegraed circui packaging, including he 8-pin (150-mil) OIC and space-saving 8-pin (118-mil) OP. 1 of

2 D1052 OPEION Inerface proocol is simplified o an 8-bi conrol bye and 8-bi daa bye. Informaion can be read or wrien o he D1052 including a commanded shudown operaion. Power-Up Configuraion he D1052 powers-up o half-scale (10000B) providing 50% duy-cycle. In his mode, he D1052 can be used as a sandalone oscillaor of he frequency specified. Once powered, he PWM oupu can be changed via he 2-wire addressable serial por. Pin Descripion V cc Power supply erminal. he D1052 will suppor operaion from power supply volages ranging from +2.7 vols o +5.5 vols. GND Ground erminal. PWM O Pulse-widh modulaed oupu. his oupu is a square-wave having ampliudes from 0 vols o V CC. he duy cycle of his oupu is governed by a 5-bi conrol regiser. Oupu duy cycles range from 0% o 96.88%. n addiional command sequence will provide a 100% duy cycle or full-on. CL erial clock inpu. D erial bi-direcional daa I/O. 0, 1, 2 Device address (chip selecs). 2-Wire ddressable erial Por Conrol he 2-wire serial por inerface suppors a bi-direcional daa ransmission proocol wih device addressing. device ha sends daa on he bus is defined as a ransmier, and a device receiving daa as a receiver. he device ha conrols he message is called a maser. he devices ha are conrolled by he maser are slaves. he bus mus be conrolled by a maser device ha generaes he serial clock (CL), conrols he bus access, and generaes he and OP condiions. he D1052 operaes as a slave on he 2-wire bus. Connecions o he bus are made via he open-drain I/O lines D and CL. he following I/O erminals conrol he 2-wire serial por: D, CL, 0, 1, and 2. 2-wire serial por overview and iming diagrams for he 2-wire serial por can be found in Figures 2 and 5, respecively. iming informaion for he 2-wire serial por is provided in he C Elecrical Characerisics able for 2-wire serial communicaions. 2 of 14

3 D1052 he following bus proocol has been defined (ee Figure 2): Daa ransfer may be iniiaed only when he bus is no busy. During daa ransfer, he daa line mus remain sable whenever he clock line is HIGH. Changes in he daa line while he clock line is high will be inerpreed as conrol signals. ccordingly, he following bus condiions have been defined: Bus no busy: Boh daa and clock lines remain HIGH. ar daa ransfer: change in he sae of he daa line from HIGH o LOW while he clock is HIGH, defines a condiion. op daa ransfer: change in he sae of he daa line from LOW o HIGH while he clock line is HIGH defines he OP condiion. Daa valid: he sae of he daa line represens valid daa when, afer a condiion, he daa line is sable for he duraion of he HIGH period of he clock signal. he daa on he line mus be changed during he LOW period of he clock signal. here is one clock pulse per bi of daa. Figure 2 deails how daa ransfer is accomplished on he 2-wire bus. Depending upon he sae of he /W bi, wo ypes of daa ransfer are possible. Each daa ransfer is iniiaed wih a condiion and erminaed wih a OP condiion. he number of daa byes ransferred beween and OP condiions is no limied and is deermined by he maser device. he informaion is ransferred bye-wise and each receiver acknowledges wih a ninh bi. Wihin he bus specificaions, a regular mode (100kHz clock rae) and a fas mode (400kHz clock rae) are defined. he D1052 works in boh modes. cknowledge: Each receiving device, when addressed, is obliged o generae an acknowledge afer he recepion of each bye. he maser device mus generae an exra clock pulse ha is associaed wih his acknowledge bi. device ha acknowledges mus pull down he D line during he acknowledge clock pulse in such a way ha he D line is sable LOW during he HIGH period of he acknowledge-relaed clock pulse. Of course, seup and hold imes mus be aken ino accoun. maser mus signal an end of daa o he slave by no generaing an acknowledge bi on he las bye ha has been clocked ou of he slave. In his case, he slave mus leave he daa line HIGH o enable he maser o generae he OP condiion. 1. Daa ransfer from a maser ransmier o a slave receiver. he firs bye ransmied by he maser is he command/conrol bye. Nex follows a number of daa byes. he slave reurns an acknowledge bi afer each received bye. 2. Daa ransfer from a slave ransmier o a maser receiver. he firs bye (he command/conrol bye) is ransmied by he maser. he slave hen reurns an acknowledge bi. Nex follows a number of daa byes ransmied by he slave o he maser. he maser reurns an acknowledge bi afer all received byes oher han he las bye. he end of he las received bye, a no acknowledge is reurned. 3 of 14

4 D1052 he maser device generaes all serial clock pulses and he and OP condiions. ransfer is ended wih a OP condiion or wih a repeaed condiion. ince a repeaed condiion is also he beginning of he nex serial ransfer, he bus will no be released. he D1052 may operae in he following wo modes: 1. lave receiver mode: erial daa and clock are received hrough D and CL, respecively. fer each bye is received, an acknowledge bi is ransmied. and OP condiions are recognized as he beginning and end of a serial ransfer. ddress recogniion is performed by hardware afer recepion of he slave (device) address and direcion bi. 2. lave ransmier mode: he firs bye is received and handled as in he slave receiver mode. However, in his mode he direcion bi will indicae ha he ransfer direcion is reversed. erial daa is ransmied on D by he D1052 while he serial clock is inpu on CL. and OP condiions are recognized as he beginning and end of a serial ransfer. LVE DDE command/conrol bye is he firs bye received following he condiion from he maser device. he command/conrol bye consiss of a four-bi conrol code. For he D1052, his is se as 0101 binary for read/wrie operaions. he nex hree bis of he command/conrol bye are he device selec bis or slave address (2, 1, 0). hey are used by he maser device o selec which of eigh possible devices is o be accessed. When reading or wriing he D1052, he device selec bis mus mach he device selec pins (2, 1, 0). he las bi of he command/conrol bye (/W) defines he operaion o be performed. When se o a one a read operaion is seleced, and when se o a zero a wrie operaion is seleced. he command conrol bye is presened in Figure 3. Following he condiion, he D1052 moniors he D bus checking he device ype idenifier being ransmied. Upon receiving he 0101 conrol code, he appropriae device address bis, and he read/wrie bi, he slave device oupus an acknowledge signal on he D line. COMMND ND POOCOL he command and proocol srucure of he D1052 allows he user o read or wrie he PWM configuraion regiser or place he device in a low-curren sae (shu-down mode) and recall he device from a low-curren sae. ddiionally, he 2-wire command/proocol srucure of he D1052 will suppor eigh differen devices ha can be uniquely conrolled. Figure 4a, b, c, d, & e show he five differen command and proocol byes for he D1052. hese include he following command operaions: 1) e PWM duy cycle, 2) e PWM duy cycle 100%, 3) e shudown mode, 4) e recall mode, 5) ead PWM configuraion regiser. he command operaion e PWM Duy Cycle is used o configure he oupu duy cycle of he device. he D1052 has a 5-bi resoluion and is capable of seing he duy cycle oupu from 0% up o 96.88% in seps of 3.125%. binary value of (00000B) ses he duy cycle oupu a 0% while a binary value of (11111B) ses he duy cycle oupu a 96.88%. he command operaion e PWM Duy Cycle 100% is used o configure he oupu duy cycle of he device o a full-on. his command is provided in addiion o he e PWM Duy Cycle command for flexibiliy and convenience in oal duy cycle coverage. I allows he user o provide a oal duy cycle range from 0% o 100%. 4 of 14

5 D1052 he command operaion e hudown Mode is used o provide a low-curren (inacive sae) sae for he D1052. When in a low-curren sae he D1052 will draw currens less han or equal o 1. he PWM O oupu will be high impedance. he command operaion e ecall Mode is used o recall he D1052 from a low-curren sae. he value of he PWM O oupu is recalled o ha prior o iniiaing a e shudown mode command. he ead PWM Duy Cycle command is used o read he curren seing of he PWM configuraion regiser. Informaion reurned by his command includes PWM oupu value as well as wheher he device is in a shudown configuraion. PWM daa values and conrol/command values are always ransmied mos significan bi (MB) firs. During communicaions, he receiving uni always generaes he acknowledge. EDING HE D1052 s shown in Figure 4e, he D1052 provides one read command operaion. his operaion allows he user o read he curren seing of he PWM configuraion regiser. pecifically, he /W bi of he command/conrol bye is se equal o a 1 for a read operaion. Communicaion o read he D1052 begins wih a condiion which is issued by he maser device. he command/conrol bye from he maser device will follow he condiion. Once he command/conrol bye has been received by he D1052, he par will respond wih an CKNOWLEDGE. he read/wrie bi of he command/conrol bye, as saed, should be se equal o 1 for reading he D1052. When he maser has received he CKNOWLEDGE from he D1052, he maser can hen begin o receive he PWM configuraion regiser daa. s menioned his daa will be ransmied MB firs. Once he eigh bis of he PWM configuraion regiser have been ransmied, he maser will need o issue an CKNOWLEDGE, unless i is he only bye o be read, in which case he maser issues a NO CKNOWLEDGE. If desired he maser may sop he communicaion ransfer a his poin by issuing he OP condiion. Final communicaion ransfer is erminaed by issuing he OP command. gain, he flow of he read operaion is presened in Figure 4e. WIING HE D1052 daa flow diagram for wriing he D1052 is shown in Figures 4a, b, c, and d. he D1052 has hree wrie commands ha are used o change he PWM configuraion regiser or he shudown and recall mode of he device. ll he wrie operaions begin wih a condiion. Following he condiion, he maser device will issue he command/conrol bye. he read/wrie bi of he command/conrol bye will be se o 0 for wriing he D1052. Once he command/conrol bye has been issued and he maser receives he acknowledgmen from he D1052, PWM configuraion daa is ransmied o he D1052 by he maser device. daa bye for he D1052 will conain PWM configuraion daa and shudown/recall command daa. he five leas significan bis of daa specify he PWM configuraion value while he hree mos significan bis specify he wheher he device is o be shudown or recalled. When he D1052 has received he daa bye, i will respond wih an CKNOWLEDGE. his poin, he new PWM configuraion regiser value and shudown/recall command value will be updaed in he D1052. he maser device, afer he receip of he CKNOWLEDGE, can coninue o ransmi addiional daa byes 5 of 14

6 D1052 or if he ransacion is complee respond wih he OP condiion. he 2-wire serial iming diagram is presened in Figure 5. 6 of 14

7 BOLUE MXIMUM ING* Volage on ny Pin elaive o Ground Operaing emperaure orage emperaure oldering emperaure -0.3V o +6.0V -40 o C o +85 o C -55 o C o +125 o C ee J-D-020 specificaion D1052 * his is a sress raing only and funcional operaion of he device a hese or any oher condiions above hose condiions indicaed in he operaion secion of he specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods of ime may affec reliabiliy. ECOMMENDED DC OPEING CONDIION (-40 C o +85 C; V CC = 2.7V o 5.5V) PMEE YMBOL MIN YP MX UNI NOE upply volage V CC V 1 DC ELECICL CHCEIIC (-40 C o +85 C; V CC =2.7V o 5.5V) PMEE YMBOL CONDIION MIN YP MX UNI NOE cive upply I CC Curren Inpu Leakage I LI +1 Inpu Logic 1 V IH 0.7 V CC V CC +0.3 V 3, 4 Inpu Logic 0 V IL GND V CC V 3, 4 Inpu Curren Each 0.4 V I/O I/O Pin V CC andby Curren I BY LOW Level Oupu Volage (D) V OL1 V OL2 3m ink Curren 6m ink Curren I/O Capaciance C I/O 10 pf PWM Oupu Currens I OH I OL V CC m m V V 7 of 14

8 C ELECICL CHCEIIC D1052 (-40 C o +85 C; V CC = 2.7V o 5.5V) PMEE YMBOL CONDIION MIN YP MX UNI NOE CL Clock f CL Fas Mode khz 6 Frequency andard Mode Bus Free ime Beween OP and Condiion BUF Fas Mode andard Mode s 6 Hold ime (epeaed) Condiion HD: Fas Mode andard Mode Low Period of CL Clock LOW Fas Mode andard Mode High Period of CL HIGH Fas Mode Clock andard Mode Daa Hold ime HD:D Fas Mode andard Mode Daa e-up ime U:D Fas Mode andard Mode ise ime of Boh Fas Mode D and CL andard Mode ignals Fall ime of Boh D and CL ignals e-up ime for OP Condiion Capaciive Load for Each Bus Line PWM Oupu Change F U:O CB PWM Fas Mode andard Mode Fas Mode andard Mode Fas Mode andard Mode Fas Mode andard Mode C ELECICL CHCEIIC s 7, s s s 6, 8, ns C B 300 ns C B ns 10 s 400 pf 10 2 periods 11 (-40 C o +85 C; V CC = 2.7V o 5.5V) PMEE YMBOL CONDIION MIN YP MX UNI NOE Oupu Frequency % 12 olerance Oupu Impedance 200 bsolue Lineariy LB 14 elaive Lineariy LB 15 esoluion 5 Bis 13 Frequency ±200 ppm/ºc emperaure Coefficien Frequency Volage Coefficien 1.5 % per V 8 of 14

9 D1052 NOE: 1. ll volages are referenced o ground. 2. I CC specified wih oupus open. 3. I/O pins of fas mode devices mus no obsruc he D and CL lines if V CC is swiched off. 4. ddress Inpus, 0, 1, and 2, should be ied o eiher V CC or GND depending on he desired address selecions. 5. I BY specified for V CC beween 3.0V and 5.0V, conrol por logic pins are driven o he appropriae logic levels. 6. fas mode device can be used in a sandard mode sysem, bu he requiremen U:D > 250ns mus hen be me. his will auomaically be he case if he device does no srech he LOW period of he CL signal. If such a device does srech he LOW period of he CL signal, i mus oupu he nex daa bi o he D line MX + U:D = =1250ns before he CL line is released. 7. fer his period, he firs clock pulse is generaed. 8. he maximum U:D has only o be me if he device does no srech he LOW period ( LOW ) of he CL signal. 9. device mus inernally provide a hold ime of a leas 300ns for he D signal (referred o he V IH MIN of he CL signal) in order o bridge he undefined region of he falling edge of CL. 10. C B oal capaciance of one bus line in picofarads, iming referenced o (0.9)(V CC ) and (0.1)(V CC ). 11. PWM oupu duy cycle change will occur wih 2 periods of he oupu frequency when a change is iniiaed. 12. he absolue frequency oupu of he PWM can be expeced o fall wihin a 20% range from he nominal specified value of he device. 13. he D1052 is a 5-bi PWM. he oupu duy cycles of he device range from 0% o 100% in sep sizes of 3.125%. he e PWM Duy Cycle 100% allows he PWM oupu o be se o full-on. 14. bsolue Lineariy is used o compare measured duy cycle agains expeced duy cycle as deermined by he DC seing. he D1052 is specified o provide an absolue lineariy of 0.5 LB. 15. elaive Lineariy is used o deermine he change in duy cycle beween adjacen or successive duy cycle seings. he D1052 is specified o provide a relaive lineariy specificaion of 0.25 LB. 9 of 14

10 BLOCK DIGM Figure 1 D1052 vcc OCILLO DIVE PWM CONOL LOGIC CL D erial Por HUDOWN CONOL CICUIY 2-WIE DDEBLE EIL PO OVEVIEW Figure 2 GND D msb slave address r/w direcion bi acknowledgemen signal from receiver acknowledgemen signal from receiver CL ar Condiion CK repeaed if more byes are ransferred CK op Condiion or repeaed ar Condiion COMMND/CONOL BYE Figure 3 msb lsb r/w Device Idenifier Device ddress ead/wrie Bi 10 of 14

11 D1052 COMMND ND POOCOL Figure 4 D1052 E PWM DUY CYCLE (a) MB CONOL BYE LB C K /W=0 MB PWM DBYE PWM Daa LB O P (b) MB CONOL BYE LB C K /W=0 MB PWM DBYE Don' Care LB O P E HU-DOWN MODE (c) MB CONOL BYE LB C K /W=0 MB PWM DBYE Don' Care LB O P ECLL MODE (d) MB CONOL BYE LB C K MB PWM DBYE Don' Care LB O P /W=0 ED PWM DUY CYCLE (e) MB CONOL BYE LB C K MB PWM DBYE PWM-D LB O P /W=1 11 of 14

12 2-WIE EIL DIGM Figure 5 D1052 D BUF LOW F HD: P CL HD: HIGH U: U:O HD: U:D OP EPEED 12 of 14

13 YPICL OPEING CHCEIIC D1052 (V CC = 5.0V; = +25ºC, unless oherwise specified) D1052 D1052 FEQUENCY vs. EMPEUE FEQUENCY (khz) D1052 Freq vs emp, 3.3V D1052 Freq vs emp, 5V EMPEUE (C) 120 D1052 UPPLY CUEN vs. EMPEUE 100 UPPLY CUEN (µ) D1052 upply Curren vs emp, 3.3V D1052 upply Curren vs emp, 5V EMPEUE (C) 13 of 14

14 YPICL OPEING CHCEIIC D1052 (V CC = 5.0V; = +25ºC, unless oherwise specified) D1052 D1052 DUY CYCLE vs. POIION DUY CYCLE (%) D1052 Duy Cycle vs Posiion, 3.3V and 5V POIION EING (DECIML) 14 of 14

ECMA st Edition / June Near Field Communication Wired Interface (NFC-WI)

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