empoweraudio NAU8820 Low Power 24-bit Stereo Audio Codec with High Current Outputs NAU8820 Design Guide Rev 1.3 Page 1 of 23 June 28, 2016

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1 Desciption NAU882 Low Powe 24-bit Steeo Auio Coec with High Cuent Outputs empoweauio The NAU882 is a low powe, high quality CODEC fo potable applications. In aition to pecision 24-bit steeo ADCs an DACs, this evice integates a boa ange of aitional functions to simplify implementation of complete auio system solutions. The NAU882 inclues ives fo heaphones, an iffeential o steeo line outputs, an integates peamps fo steeo iffeential micophones, significantly eucing extenal components. Avance on-chip igital signal pocessing inclues a 5-ban equalize, a 3-D auio enhance, a mixe-signal automatic level contol fo the micophone o line input though the ADC, an a igital limite function fo the playback path. Aitional igital filteing options ae available in the ADC path, to simplify implementation of specific application equiements such as win noise euction. The igital inteface can opeate as eithe a maste o a slave. Aitionally, an intenal factional PLL is available to geneate accuately any esie auio sample ate clock fo the CODEC, using any commonly available system clock fom 8MHz to 33MHz an no extenal pats. The NAU882 opeates with analog supply voltages fom 2.5V to 3.6V, while the igital coe can opeate as low as 1.65V to conseve powe. The two high cuent auxiliay line outputs can opeate using sepaate supply ails fo incease output capability an esign flexibility, an may be use fo cap-less heaphone ive. Intenal egiste contols enable flexible powe saving moes by poweing own sub-sections of the chip une softwae contol. The NAU882 is specifie fo opeation fom -4 C to +85 C. AEC-Q1 & TS16949 compliant evice is available upon equest. Key Featues DAC: 94 SNR an -84 THD ( A weighte) ADC: 9 SNR an -8 THD ( A weighte) Integate hea-phone ive: 4mW into 16Ω Integate pogammable micophone amplifie Integate line input an high cuent line output On-chip PLL Integate DSP with specific functions: 5-ban equalize 3-D auio enhancement Automatic level contol Auio level limite Multiple filteing options Stana auio intefaces: PCM an I 2 S Seial contol intefaces with ea/wite capability Suppots auio sample ates fom 8kHz to 48kHz Applications Pesonal Meia Playes Smatphones Pesonal Navigation Devices Potable Game Playes Camcoes Digital Still Cameas Potable TVs Steeo luetooth Heasets NAU882 Design Guie Rev 1.3 Page 1 of 23 June 28, 216

2 LAUXIN RAUXIN LLIN RLIN LMICN LMICP RMICN Steeo Micophone Inteface Input Mixe LADC RADC ADC Filte Volume Contol High Pass & Notch Filtes 5-ban EQ 3D DAC Filte Volume Contol Limite LDAC RDAC Output Mixe Heaphones/ Line ives AUXOUT2 AUXOUT1 LHP RHP RMICP Micophone ias GPIO PLL Digital Auio Inteface I 2 S PCM Seial Contol Inteface NAU882YG Pinout NC LLIN/GPIO2 RMICP RMICN RLIN/GPIO3 VSSD VDD MICIAS VREF NC LMICP VSSSPK LMICN AUXOUT2 AUXOUT1 RAUXIN LAUXIN FS CLK MODE SDIO ADCOUT DACIN MCLK VDDC CS/GPIO1 SCLK VDDA LHP RHP VSSA VDDSPK 2 Top View WAU882YG 32-lea QFN RoHS ulk Goun Pa Pat Numbe Dimension Package Package Mateial NAU882 Design Guie Rev 1.3 Page 2 of 23 June 28, 216 NAU882YG 5 x 5 mm 32-QFN Pb-Fee

3 Pin Desciptions Pin # Name Type Functionality 1 LMICP Analog Input Left MICP Input (common moe) 2 LMICN Analog Input Left MICN Input 3 LLIN/GPIO2 Analog Input / Left Line Input / altenate Left MICP Input / GPIO2 Digital I/O 4 RMICP Analog Input Right MICP Input (common moe) 5 RMICN Analog Input Right MICN Input 6 RLIN/GPIO3 Analog Input / Digital I/O Right Line Input/ altenate Right MICP Input / Digital Output In 4-wie moe: Must be use fo GPIO3 7 FS Digital I/O Digital Auio DAC an ADC Fame Sync 8 CLK Digital I/O Digital Auio it Clock 9 ADCOUT Digital Output Digital Auio ADC Data Output 1 DACIN Digital Input Digital Auio DAC Data Input 11 MCLK Digital Input Maste Clock Input 12 VSSD Supply Digital Goun 13 VDDC Supply Digital Coe Supply 14 VDD Supply Digital uffe (Input/Output) Supply 15 CS/GPIO1 Digital I/O 3-Wie MPU Chip Select o GPIO1 multifunction input/output 16 SCLK Digital Input 3-Wie MPU Clock Input / 2-Wie MPU Clock Input 17 SDIO Digital I/O 3-Wie MPU Data Input / 2-Wie MPU Data I/O 18 MODE Digital Input Contol Inteface Moe Selection Pin 19 LAUXIN Analog Input Left Auxiliay Input 2 RAUXIN Analog Input Right Auxiliay Input 21 AUXOUT1 Analog Output Heaphone Goun / Mono Mixe Output / Line Output 22 AUXOUT2 Analog Output Heaphone Goun / Line Output 23 NC Not Intenally Connecte 24 VSSSPK Supply AUXOUT Line/Speake Pe-amp Dive Analog Goun 25 NC Not Intenally Connecte 26 VDDSPK Supply AUXOUT Line/Speake Pe-amp Dive Analog Powe Supply 27 VREF Refeence Decoupling fo Miail Refeence Voltage 28 VSSA Supply Analog Goun 29 RHP Analog Output Heaphone Positive Output / Line Output Right 3 LHP Analog Output Heaphone Negative Output / Line Output Left 31 VDDA Supply Analog Powe Supply 32 MICIAS Analog Output Micophone ias Notes 1. The 32-QFN package inclues a bulk goun connection pa on the unesie of the chip. This bulk goun shoul be themally tie to the PC as much as possible, an electically tie to the analog goun (VSSA, pin 28). 2. Unuse analog input pins shoul be left as no-connection. 3. Unuse igital input pins shoul be tie to goun. 4. Pins esignate as NC (Not Intenally Connecte) shoul be left as no-connection NAU882 Design Guie Rev 1.3 Page 3 of 23 June 28, 216

4 LAUXIN LMICN LMICP LLIN RMICN RMICP RLIN RAUXIN VREF MICIAS VDD VDDC VSSD VDDA VSSA VDDSPK VSSSPK LADC MIX/OOST LINMIX - + Σ RADC LDAC HPF - + ALC Contol ALC Notch Filte Limite Σ RADC RDAC VDDA R RADC MIX/OOST 5 an EQ 3D R RINMIX MICROPHONE IAS PLL AUDIO INTERFACE (PCM/IIS) CLK FS ADCOUT DACIN RINMIX LDAC RDAC AUX1 MIXER Σ LMIX Σ LMAIN MIXER RMAIN MIXER Σ RMIX LINMIX LDAC Σ LMIX AUX2 MIXER CONTROL INTERFACE (2-, 3- an 4-wie) MCLK SCLK SDIO CS/ GPIO1 MODE Nomal -6-1.X +1.5X -1.X +1.5X AUXOUT1 AUXOUT2 LHP RHP NC NC NAU882 Design Guie Rev 1.3 Page 4 of 23 June 28, 216 Figue 1: NAU882 lock Diagam

5 Electical Chaacteistics Conitions: VDDC = 1.8V, VDDA = VDD = VDDSPK = 3.3V, MCLK = MHz, T A = +25 C, 1kHz signal, fs = 48kHz, 24-bit auio ata, 64X ovesampling ate, unless othewise state. Paamete Symbol Comments/Conitions Min Typ Max Units Analog to Digital Convete (ADC) Full scale input signal 1 V INFS PGAST = PGAGAIN = 1. Vms V Signal-to-noise atio SNR Gain =, A-weighte tb 9 Total hamonic istotion 2 THD+N Input = -3 FS input -8 tb Channel sepaation 1kHz input signal 13 Digital to Analog Convete (DAC) iving RHP / LHP with 1kΩ / 5pF loa Full-scale output 4 Output boost isable PGA gains = AUX1ST = 1 AUX2ST = 1 Output boost enable PGA gains = AUX1ST = AUX2ST = VDDA / * (VDDA / 3.3) Signal-to-noise atio SNR A-weighte Total hamonic istotion 2 THD+N R L = 1kΩ; full-scale signal -84 tb Channel sepaation 1kHz input signal 96 Output Mixes Maximum PGA gain into mixe +6 Minimum PGA gain into mixe -15 PGA gain step into mixe Guaantee monotonic 3 Analog Outputs (RHP / LHP) Maximum pogammable gain +6 Minimum pogammable gain -57 Pogammable gain step size Guaantee monotonic 1 Mute attenuation 1kHz full scale signal 85 Heaphone Output (RHP / LHP with 32Ω loa) full scale output voltage AVDD / 3.3 V ms Signal-to-noise atio SNR A-weighte 92 Total hamonic istotion 2 THD+N R L = 16Ω, P o = 2mW, VDDA = 3.3V R L = 32Ω, P o = 2mW, VDDA = 3.3V V ms V ms 8 85 AUXOUT1 / AUXOUT2 with 1kΩ / 5pF loa Full scale output 3 AUX1ST = VDDSPK / 3.3 V ms AUX2ST = AUX1ST = 1 (VDDSPK / 3.3) * 1.5 V ms AUX2ST = 1 Signal-to-noise atio SNR 87 Total hamonic istotion 2 THD+N -83 Channel sepaation 1kHz signal 99 Powe supply ejection atio (5Hz - 22kHz) PSRR 53 NAU882 Design Guie Rev 1.3 Page 5 of 23 June 28, 216

6 Electical Chaacteistics, cont. Conitions: VDDC = 1.8V, VDDA = VDD = VDDSPK = 3.3V, MCLK = MHz, T A = +25 C, 1kHz signal, fs = 48kHz, 24-bit auio ata, unless othewise state. Paamete Symbol Comments/Conitions Min Typ Max Units Micophone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) an Pogammable Gain Amplifie (PGA) Full scale input signal 1 PGAST = PGAGAIN = 1. Vms V Pogammable gain Pogammable gain step size Guaantee Monotonic.75 Mute Attenuation 12 Input esistance Inveting Input PGA Gain = PGA Gain = PGA Gain = -12 Non-inveting Input kω kω kω kω Input capacitance 1 pf PGA equivalent input noise Input oost Mixe Gain boost to 2kHz, Gain set to µv oost isable oost enable 2 Gain ange LLIN / RLIN o LAUXIN / RAUXIN to boost/mixe Gain step size to boost/mixe 3 Auxiliay Analog Inputs (LAUXIN, RAUXIN) Full scale input signal 1 Gain = 1. Vms V Input esistance Aux iect-to-out path, only Input gain = +6. Input gain =. Input gain = kω kω kω Input capacitance 1 pf NAU882 Design Guie Rev 1.3 Page 6 of 23 June 28, 216

7 Electical Chaacteistics, cont. Conitions: VDDC = 1.8V, VDDA = VDD = VDDSPK = 3.3V, MCLK = MHz, T A = +25 C, 1kHz signal, fs = 48kHz, 24-bit auio ata, unless othewise state. Paamete Symbol Comments/Conitions Min Typ Max Units Automatic Level Contol (ALC) & Limite: ADC path only Taget eco level FS Pogammable gain Gain hol time 4 t HOLD Doubles evey gain step, / 2.67 / 5.33 / / ms with 16 steps total Gain amp-up (ecay) 4 t DCY ALC Moe 4 / 8 / 16 / / 496 ms ALC = Limite Moe 1 / 2 / 4 / / 124 ms ALC = 1 Gain amp-own (attack) 4 t ATK ALC Moe 1 / 2 / 4 / / 124 ms ALC = Limite Moe.25 /.5 / 1 / / 128 ms ALC = 1 Mute Attenuation 12 Micophone ias ias voltage V MICIAS See Figue 4.5,.6,.65,.7,.75,.85, o.9 VDDA VDDA ias cuent souce I MICIAS 3 ma Output noise voltage V n 1kHz to 2kHz 14 nv/ Hz Digital Input/Output Input HIGH level V IL.7 * V VDDC Input LOW level V IH.3 * V VDDC Output HIGH level V OH I Loa = 1mA.9 * V VDDC Output LOW level V OL I Loa = -1mA.1 * V VDDC Input capacitance 1 pf Notes 1. Full Scale is elative to the magnitue of VDDA an can be calculate as FS = VDDA/ Distotion is measue in the stana way as the combine quantity of istotion poucts plus noise. The signal level fo istotion measuements is at 3 below full scale, unless othewise note. 3. With efault egiste settings, SPKVDD shoul be 1.5xVDDA (but not exceeing maximum ecommene opeating voltage) to optimize available ynamic ange in the AUXOUT1 an AUXOUT2 line output stages. Output DC bias level is optimize fo SPKVDD = 5.Vc (boost moe) an VDDA = 3.3Vc. 4. Time values scale popotionally with MCLK. Complete esciptions an efinitions fo these values ae containe in the etaile esciptions of the ALC functionality. NAU882 Design Guie Rev 1.3 Page 7 of 23 June 28, 216

8 Absolute Maximum Ratings Conition Min Max Units VDD, VDDC, VDDA supply voltages V VDDSPK supply voltage (efault egiste configuation) V VDDSPK supply voltage (optional low voltage configuation) V Coe Digital Input Voltage ange VSSD.3 VDDC +.3 V uffe Digital Input Voltage ange VSSD.3 VDD +.3 V Analog Input Voltage ange VSSA.3 VDDA +.3 V Inustial opeating tempeatue C Stoage tempeatue ange C CAUTION: Do not opeate at o nea the maximum atings liste fo extene peios of time. Exposue to such conitions may avesely influence pouct eliability an esult in failues not covee by waanty. Opeating Conitions Conition Symbol Min Typical Max Units Digital supply ange (Coe) VDDC V Digital supply ange (uffe) VDD V Analog supply ange VDDA V Speake supply (SPKST=) VDDSPK V Speake supply (SPKST=1) VDDSPK V Goun VSSD VSSA VSSSPK V 1. VDDA must be VDDC. 2. VDD must be VDDC. NAU882 Design Guie Rev 1.3 Page 8 of 23 June 28, 216

9 1 Geneal Desciption The NAU882 is a steeo evice with ientical left an ight channels that shae common suppot elements. The left an ight channels ae ientical, except fo the mixing options an gain options available fo each of the two auxiliay outputs. 1.1 Analog Inputs All inputs, except fo the wie ange pogammable amplifie (PGA), have available analog input gain conitioning of -15 though +6 in 3 steps. All inputs also have iniviual muting functions with excellent channel isolation an off-isolation fom all outputs. All inputs ae suitable fo full quality, high banwith signals. Each of the left-ight steeo channels inclues a low noise iffeential PGA amplifie, pogammable fo highgain input. This may be use fo a micophone level though line level souce. Gain may be set fom b though -12 at the analog iffeence-amplifie type pogammable amplifie input stage. A sepaate aitional 2 analog gain is available on this input path, between the PGA output an ADC mixe input. The output of the ADC mixe may be oute to the ADC an/o analog bypass to the analog output sections. Each channel also has a line level input. This input may be oute to the input PGA, an/o iectly to the ADC input mixe. Each channel has a sepaate aitional auxiliay input. This is a line level input which may be oute the ADC input mixe an/o iectly to the analog output mixes. 1.2 Analog Outputs Thee ae fou high cuent analog auio outputs. These ae vey flexible outputs that can be use iniviually o in steeo pais fo a wie ange of en uses. Howeve, these outputs ae optimize fo specific functions an ae escibe in this section using the functional names that ae applicable to those optimize functions. Each output eceives its signal souce fom built-in analog output mixes. These mixes enable a wie ange of signal combinations, incluing muting of all souces. Aitionally, each output has a pogammable gain function, output mute function, an output isable function. The RHP an LHP heaphone outputs ae optimize fo iving a steeo pai of heaphones, an ae powee fom the main analog voltage supply ail, VDDA. These outputs may be couple using taitional DC blocking seies capacitos. Altenatively, these may be configue in a no-capacito DC couple esign using a vitual goun at ½ VDDA povie by an AUXOUT analog output. Gain of each heaphone output can be sepaately vaie in 1 steps fom +6 though -57. The AUXOUT1 an AUXOUT2 analog outputs can be couple to a wie ange of input signal mixing options, an suppot two gain choices. Gain may eithe be unity fo 3.3V opeation, o 1.5x fo 5V opeation. The auxiliay outputs ae powee fom the VDDSPK supply ail an VSSSPK goun etun path. The supply ail may be the same as VDDA, o may be a sepaate voltage up to 5.Vc. These sepaate supply ails enable these outputs to have incease output ange an powe capabilities, an facilitate system esign though enabling powe supply an outing sepaate fom VDDA. Impotant: Fo analog outputs epopping pupose, when poweing up speakes, heaphone, AUXOUTs, cetain elays ae geneate afte enabling sequence. Howeve, the elays ae ceate by MCLK an sample ate egiste. Fo coect opeation, sening I2S signal no ealie than 25ms afte speake o heaphone enable an MCLK appeaing. NAU882 Design Guie Rev 1.3 Page 9 of 23 June 28, 216

10 ADC, DAC, an Digital Signal Pocessing Each left an ight channel has an inepenent high quality ADC an DAC associate with it. These ae high pefomance, 24-bit elta-sigma convetes that ae suitable fo a vey wie ange of applications. The ADC an DAC functions ae each iniviually suppote by poweful analog mixing an outing. The ADC output may be oute to the igital output path an/o to the input of the DAC in a igital passthough moe. The ADC an DAC blocks ae also suppote by avance igital signal pocessing subsystems that enable a vey wie ange of pogammable signal conitioning an signal optimizing functions. All igital pocessing is with 24-bit pecision, as to minimize pocessing atifacts an maximize the auio ynamic ange suppote by the NAU882. The ADCs ae suppote by a wie ange, mixe-moe Automatic Level Contol (ALC), a high pass filte, an a notch filte. All of these featues ae optional an highly pogammable. The high pass filte function is intene fo DC-blocking o low fequency noise euction, such as to euce unwante ambient noise o win noise on a micophone input. The notch filte may be pogamme to geatly euce a specific fequency ban o fequency, such as a 5Hz, 6Hz, o 217Hz unwante noise. The DACs ae suppote by a pogammable limite/drc (Dynamic Range Compesso). This is useful to optimize the output level fo vaious applications an fo use with small louspeakes. This is an optional featue that may be pogamme to limit the maximum output level an/o boost an output level that is too small. Digital signal pocessing is also povie fo a 3D Auio Enhancement function, an fo a 5-an Equalize. These featues ae optional, an ae pogammable ove wie anges. This pai of igital pocessing featues may be applie jointly to eithe the ADC auio path o to the DAC auio path, but not to both paths simultaneously. 1.3 Voltage Refeence an Micophone ias uilt-in powe management inclues a high stability voltage efeence. This is use as an intenal efeence, an to geneate a high quality, pogammable micophone bias supply voltage that is well isolate fom the supply ails. This micophone bias supply is suitable fo both conventional electet (ECM) type micophone, an to powe the newe MEMS all-silicon type micophones. 1.4 Digital Intefaces Comman an contol of the evice is accomplishe using a 2-wie/3-wie/4-wie seial contol inteface. This is a simple, but highly flexible inteface that is compatible with many commonly use comman an contol seial ata potocols an host ives. Digital auio input/output ata steams ae tansfee to an fom the evice sepaately fom comman an contol. The igital auio ata inteface suppots eithe I2S o PCM auio ata potocols, an is compatible with commonly use inusty stana evices that follow eithe of these two seial ata fomats. 1.5 Clock Requiements The clocking signals equie fo the auio signal pocessing, auio ata I/O, an contol logic may be povie extenally, o by optional opeation of a built-in PLL (Phase Locke Loop). An extenal maste clock (MCLK) signal must be active fo analog auio logic paths to align with contol egiste upates, an is equie as the efeence clock input fo the PLL, if the PLL is use. The PLL is povie as a low cost, zeo extenal component count optional metho to geneate equie clocks in almost any system. The PLL is a factional-n ivie type esign, which enables geneating accuate esie auio sample ates eive fom a vey wie ange of commonly available system clocks. The fequency of the system clock povie as the PLL efeence fequency may be any stable fequency in the ange between 8MHz an 33MHz. ecause the factional-n multiplication facto is a vey high pecision 24-bit value, any esie sample ate suppote by the NAU882 can be geneate with vey high accuacy, typically limite by the accuacy of the extenal efeence fequency. Refeence clocks an sample ates outsie of these anges ae also possible, but may involve pefomance taeoffs an incease esign veification. NAU882 Design Guie Rev 1.3 Page 1 of 23 June 28, 216

11 2 Application Infomation R4 ohm R5 22K ohm VSS Jack Switch Detection Example ECM lectet? type Mic R3 ohm ECM lectet? type Mic VDD Analog Inputs: No Connection if R2 22 ohm R1 22 ohm C1 4.7uF C16 1uF C15 1uF C14 1uF C13 1uF C12 1uF C11 1uF MCLK CLK FS DACIN ADCOUT MICIAS NAU882 SCLK SDIO CS/GPIO1 MODE LLIN/GPIO2 RLIN/GPIO3 LAUXIN RAUXIN LMICN LMICP RMICN RMICP VREF 27 C9 4.7uF ot use? V DD V DDC V DDA V DDSPK V SSA V SSSPK V SSD AUXOUT1 AUXOUT2 LHP RHP C5 1uF 22 C6 1uF C7 22uF + + vss vss C8 22uF VDDSPK VSS C1 4.7uF R9 optional R8 R7 optional R6 VDDA C2 4.7uF VDDC C3 4.7uF VDD Left Heaphone ip? on 3.5mm Steeo connecto VSS leeve?on 3.5mm Auio connecto Right Heaphone ing?on 3.5mm Steeo connecto C4 4.7uF VSS 2.1 Typical Application Schematic Figue 2: Schematic with ecommene extenal components fo typical application with AC-couple heaphones an steeo electet (ECM) style micophones. Note 1: All non-pola capacitos ae assume to be low ESR type pats, such as with MLC constuction o simila. If capacitos ae not low ESR, aitional.1uf an/o.1uf capacitos may be necessay in paallel with the bulk 4.7uf capacitos on the supply ails. Note 2: Loa esistos to goun on outputs may be helpful in some applications to insue a DC path fo the output capacitos to chage/ischage to the esie levels. If the output loa is always pesent an the output loa povies a suitable DC path to goun, then the aitional loa esistos may not be necessay. If neee, such loa esistos ae typically a high value, but a value epenent upon the application equiements. Note 3: To minimize pops an clicks, lage polaize output capacitos shoul be a low leakage type. Note 4: Depening on the micophone evice an PGA gain settings, common moe ejection can be impove by choosing the esistos on each noe of the micophone such that the impeance pesente to any noise on eithe micophone wie is equal. Note 5: Unuse analog input pins shoul be left as no-connection. Note 6: Unuse igital input pins shoul be tie to goun. NAU882 Design Guie Rev 1.3 Page 11 of 23 June 28, 216

12 2.2 Powe Consumption The NAU882 has flexible powe management capability which allows sections not being use to be powee own, to aw minimum cuent in battey-powee applications. The following table shows typical powe consumption in iffeent opeating conitions. The off conition is the initial powe-on state with all subsystems powee own, an with no applie clocks. Moe Conitions VDDA = 3V VDDC = 1.8V VDD = 3V Total Powe ma ma ma mw OFF Sleep VREF 3kΩ, no clocks, VREF 75kΩ, no clocks, VREF 5kΩ, no clocks, Steeo 8kHz,.9Vms input signal Reco 8kHz,.9Vms input signal, PLL on Steeo Playback 16Ω HP, 44.1kHz, quiescent Ω HP, 44.1kHz, quiescent, PLL on Ω HP, 44.1kHz,.6 Vms sine wave Ω HP, 44.1kHz,.6Vms sine, PLL on Table 1: Typical Powe Consumption in Vaious Application Moes. NAU882 Design Guie Rev 1.3 Page 12 of 23 June 28, 216

13 2.3 Supply Cuents of Specific locks The NAU882 can be pogamme to enable/isable vaious analog blocks iniviually, an the cuent to some of the majo blocks can be euce with minimum impact on pefomance. The table below shows the change in cuent consume with iffeent egiste settings. Sample ate settings affect cuent consumption of VDDC supply. Lowe sampling ates aw lowe cuent. Registe Function it VDDA cuent incease/ Dec Hex Decease when enable REFIMP[1:] +1μA fo 8kΩ an 3kΩ +26μA fo 3kΩ IOUFEN[2] +1μA 1 1 AIASEN[3] +6μA Powe MICIASEN[4] +54μA Management +2.5 ma +1/5mA fom VDDC with 1 PLLEN[5] clocks applie AUX2MXEN[6] +2μA AUX1MXEN[7] +2μA DCUFEN[8] +14μA LADCEN[] +2.3 ma with 64X OSR +3.3 ma with 128X OSR RADCEN[1] +2.3 ma with 64X OSR +3.3 ma with 128X OSR Powe LPGAEN[2] +3μA 2 2 Management RPGAEN[3] +3μA 2 LSTEN[4] +65μA RSTEN[5] +65μA SLEEP[6] Same as PLLEN (R1[5]) LHPEN[7] +8μA RHPEN[8] +8μA LDACEN[] +1.6 ma with 64X OSR +1.7 ma with 128X OSR ma with 64X OSR Powe RDACEN[1] +1.7 ma with 128X OSR Management LMIXEN[2] +25μA 3 RMIXEN[3] +25μA AUXOUT2EN[7] +225μA AUXOUT1EN[8] +225μA IIADJ[1:] -1.2mA with IIADJ at 11 REGVOLT[2:3] 58 3A Powe Management MICIASM[4] LPADC[6] -1.1mA with no SNR 8kHz 4 LPIPST[7] -6μA with no SNR 8kHz LPDAC[8] -1.1mA with 1.4 SNR 44.1kHz Table 2: VDDA 3.3V Supply Cuent in Vaious Moes NAU882 Design Guie Rev 1.3 Page 13 of 23 June 28, 216

14 3 Appenix A: Digital Filte Chaacteistics Paamete Conitions Min Typ Max Units ADC Filte Passban +/ fs -6.5 fs Passban Ripple +/-.15 Stopban.546 fs Stopban Attenuation f >.546*fs -6 Goup Delay /fs ADC High Pass Filte High Pass Filte Cone Fequency DAC Filte Passban Hz Hz Hz +/ fs -6.5 fs Passban Ripple +/-.35 Stopban.546 fs Stopban Attenuation f >.546*fs -55 Goup Delay 28 1/fs TERMINOLOGY Table 3: Digital Filte Chaacteistics 1. Stop an Attenuation () the egee to which the fequency spectum is attenuate (outsie auio ban) 2. Pass-ban Ripple any vaiation of the fequency esponse in the pass-ban egion 3. Note that this elay applies only to the filtes an oes not inclue othe latencies, such as fom the seial ata inteface NAU882 Design Guie Rev 1.3 Page 14 of 23 June 28, 216

15 Figue 3: DAC Filte Fequency Response Figue 4: DAC Filte Ripple Figue 5: ADC Filte Fequency Response NAU882 Design Guie Rev 1.3 Page 15 of 23 June 28, 216

16 Figue 6: ADC Filte Ripple NAU882 Design Guie Rev 1.3 Page 16 of 23 June 28, 216

17 Figue 7: ADC Highpass Filte Response, Auio Moe Hz Hz 7 9 Figue 8: ADC Highpass Filte Response, HPF enable, FS = 48kHz Hz 7 9 Figue 9: ADC Highpass Filte Response, HPF enable, FS = 24kHz Hz 7 9 Figue 1: ADC Highpass Filte Response, HPF enable, FS = 12kHz NAU882 Design Guie Rev 1.3 Page 17 of 23 June 28, 216

18 k 2k 5k 1k 2k Hz +15 Figue 11: EQ an 1 Gains fo Lowest Cut-Off Fequency k 2k 5k 1k 2k Hz Figue 12: EQ an 2 Peak Filte Gains fo Lowest Cut-Off Fequency with EQ2W = k 2k 5k 1k 2k Hz +15 Figue 13: EQ an 2, EQ2W = vesus EQ2W = k 2k 5k 1k 2k Hz Figue 14: EQ an 3 Peak Filte Gains fo Lowest Cut-Off Fequency with EQ3W = NAU882 Design Guie Rev 1.3 Page 18 of 23 June 28, 216

19 k 2k 5k 1k 2k Hz Figue 15: EQ an 3, EQ3W = vesus EQ3W = T Figue 16: EQ an 4 Peak Filte Gains fo Lowest Cut-Off Fequencies with EQ4W = k 2k 5k 1k 2k Hz +15 Figue 17: EQ an 4, EQ4W = vesus EQ4W = k 2k 5k 1k 2k Hz Figue 18: EQ an 5 Gains fo Lowest Cut-Off Fequency NAU882 Design Guie Rev 1.3 Page 19 of 23 June 28, 216

20 4 Appenix D: Registe Oveview DEC HEX NAME it 8 it 7 it 6 it5 it 4 it 3 it 2 it 1 it Default Softwae Reset RESET (SOFTWARE) 1 1 Powe Management 1 DCUFEN AUX1MXEN AUX2MXEN PLLEN MICIASEN AIASEN IOUFEN REFIMP 2 2 Powe Management 2 RHPEN NHPEN SLEEP RSTEN LSTEN RPGAEN LPGAEN RADCEN LADCEN 3 3 Powe Management 3 AUXOUT1EN AUXOUT2EN Reseve Reseve IASGEN RMIXEN LMIXEN RDACEN LDACEN Geneal Auio Contols 4 4 Auio Inteface CLKP LRP WLEN AIFMT DACPHS ADCPHS MONO Companing Reseve CM8 DACCM ADCCM ADDAP 6 6 Clock Contol 1 CLKM MCLKSEL CLKSEL Reseve CLKIOEN Clock Contol 2 4WSPIEN Reseve SMPLR SCLKEN 8 8 GPIO Reseve GPIO1PLL GPIO1PL GPIO1SEL 9 9 Jack Detect 1 JCKMIDEN JCKDEN JCKDIO Reseve 1 A DAC Contol Reseve SOFTMT Reseve DACOS AUTOMT RDACPL LDACPL 11 Left DAC Volume LDACVU LDACGAIN FF 12 C Right DAC Volume RDACVU RDACGAIN FF 13 D Jack Detect 2 Reseve JCKDOEN1 JCKDOEN 14 E ADC Contol HPFEN HPFAM HPF ADCOS Reseve RADCPL LADCPL 1 15 F Left ADC Volume LADCVU LADCGAIN FF 16 1 Right ADC Volume RADCVU RADCGAIN FF Reseve Equalize EQ1-low cutoff EQM Reseve EQ1CF EQ1GC 12C EQ2-peak 1 EQ2W Reseve EQ2CF EQ2GC 2C 2 14 EQ3-peak 2 EQ3W Reseve EQ3CF EQ3GC 2C EQ4-peak3 EQ4W Reseve EQ4CF EQ4GC 2C EQ5-high cutoff Reseve EQ5CF EQ5GC 2C Reseve DAC Limite DAC Limite 1 DACLIMEN DACLIMDCY DACLIMATK DAC Limite 2 Reseve DACLIMTHL DACLIMST 26 1A Reseve Notch Filte 27 1 Notch Filte 1 NFCU1 NFCEN NFCA[13:7] 28 1C Notch Filte 2 NFCU2 Reseve NFCA[6:] 29 1D Notch Filte 3 NFCU3 Reseve NFCA1[13:7] 3 1E Notch Filte 4 NFCU4 Reseve NFCA1[6:] 31 1F Reseve ALC an Noise Gate Contol 32 2 ALC Contol 1 ALCEN Reseve ALCMXGAIN ALCMNGAIN ALC Contol 2 Reseve ALCHT ALCSL ALC Contol 3 ALCM ALCDCY ALCATK Noise Gate Reseve ALCTLSEL ALCNEN ALCNTH 1 Phase Locke Loop PLL N Reseve PLLMCLK PLLN PLL K 1 Reseve PLLK[23:18] C PLL K 2 PLLK[17:9] PLL K 3 PLLK[8:] E Mic ias Moe Reseve MICIASM Miscellaneous D contol Reseve 3DDEPTH 42 2A Reseve 43 2 Reseve 44 2C Input Contol MICIASV RLINRPGA RMICNRPGA RMICPRPGA Reseve LLINLPGA LMICNLPGA LMICPLPGA D Left Input PGA Gain LPGAU LPGAZC LPGAMT LPGAGAIN E Right Input PGA Gain RPGAU RPGAZC RPGAMT RPGAGAIN F Left ADC oost LPGAST Reseve LPGASTGAIN Reseve LAUXSTGAIN Right ADC oost RPGAST Reseve RPGASTGAIN SPKSTAGE RAUXSTGAIN Output Contol Reseve LDACRMX RDACLMX AUX1ST AUX2ST SPKST TSEN AOUTIMP Left Mixe LAUXMXGAIN LAUXLMX LYPMXGAIN LYPLMX LDACLMX Right Mixe RAUXMXGAIN RAUXRMX RYPMXGAIN RYPRMX RDACRMX LHP Volume LHPVU LHPZC LHPMUTE LHPGAIN RHP Volume RHPVU RHPZC RHPMUTE RHPGAIN Reseve Reseve AUX2 Mixe Reseve AUXOUT2MT Reseve AUX1MIX>2 LADCAUX2 LMIXAUX2 LDACAUX AUX1 Mixe Reseve AUXOUT1MT AUX1HALF LMIXAUX1 LDACAUX1 RADCAUX1 RMIXAUX1 RDACAUX A Powe Management 4 LPDAC LPIPST LPADC Reseve MICIASM REGVOLT IADJ PCM Time Slot an ADCOUT Impeance Option Contol 59 3 Left Time Slot LTSLOT[8:] 6 3C Misc PCMTSEN TRI PCM8IT PUDEN PUDPE PUDPS Reseve RTSLOT[9] LTSLOT[9] D Right Time Slot RTSLOT[8:] Silicon Revision an Device ID 62 3E Device Revision # Reseve REV xxx 63 3F Device ID ID 1A NAU882 Design Guie Rev 1.3 Page 2 of 23 June 28, 216

21 Package Dimensions 32-lea Plastic QFN; 5X5mm 2, 1.mm thickness,.5mm lea pitch NAU882 Design Guie Rev 1.3 Page 21 of 23 June 28, 216

22 5 Oeing Infomation Nuvoton Pat Numbe Desciption NAU882YG Package Mateial: G = Pb-fee Package Package Type: Y = 32-Pin QFN Package Vesion Histoy VERSION DATE PAGE DESCRIPTION A. Febuay, 28 NA Peliminay Revision A.6 May 28 NA Peliminay Revision A.86 Septembe 28 NA Peliminay Revision Rev1. Ma. 5, 29 NA Coect mino eata; mino text impovements Rev 1.1 Jan.15, Upate AECQ1 esciption Rev 1.2 Mach A Impotant Notice Rev 1.3 June 28, Upate package infomation Table 4: Vesion Histoy NAU882 Design Guie Rev 1.3 Page 22 of 23 June 28, 216

23 Impotant Notice Nuvoton Poucts ae neithe intene no waante fo usage in systems o equipment, any malfunction o failue of which may cause loss of human life, boily injuy o sevee popety amage. Such applications ae eeme, Insecue Usage. Insecue usage inclues, but is not limite to: equipment fo sugical implementation, atomic enegy contol instuments, aiplane o spaceship instuments, the contol o opeation of ynamic, bake o safety systems esigne fo vehicula use, taffic signal instuments, all types of safety evices, an othe applications intene to suppot o sustain life. All Insecue Usage shall be mae at custome s isk, an in the event that thi paties lay claims to Nuvoton as a esult of custome s Insecue Usage, custome shall inemnify the amages an liabilities thus incue by Nuvoton. NAU882 Design Guie Rev 1.3 Page 23 of 23 June 28, 216