AKD4556-B AK4556 Evaluation board Rev.1

Transcription

1 [KD4556-] KD4556- K4556 Evaluation boa Rev.1 GENERL DESCRIPTION The KD4556- is an evaluation boa fo the K4556, the 24it /D & D/ convete. The KD4556- can evaluate /D convete an D/ convete sepaately in aition to loopback moe (/D D/). The KD4556- also has the igital auio inteface an can achieve the inteface with igital auio systems via opt-connecto. Oeing guie KD Evaluation boa fo K4556 FUNCTION Digital inteface - DIT (K4114): optical o NC - DIR (K4114): optical o NC 10pin heae fo seial contol inteface 5V Regulato GND NC LIN RIN K4556 K4114 (DIR&DIT) Opt In Opt Out NC LOUT ROUT 10pin Heae DSP Figue 1. KD4556- lock Diagam * Cicuit iagam an PC layout ae attache at the en of this manual

2 [KD4556-] Evaluation oa Manual Opeation sequence 1) Set up the powe supply lines [5V] (e) = +5V (3.3V is supplie to the K4556, the K4114, an the Digital Logic via the egulato.) [GND] (black) = 0V 2) Set up the evaluation moes, jumpe pins an DIP switch. (See the followings.) 3) Powe on The K4556 shoul be eset once binging SW1 (PDN) L upon powe-up. The function of the toggle SW. [SW1] : Resets the K4556 & K4114. Keep H uing nomal opeation

3 [KD4556-] Evaluation moes In case of the K4556 evaluation using the K4114, it is necessay to coespon to the auio inteface fomat. RX an TX use NC connecto at evaluation of Qua Spee with the K4114. pplicable evaluation moes (1) Evaluation of Loopback moe using the K4114 <efault> (2) Evaluation of DC using DIR of the K4114 (3) Evaluation of DC using DIT of the K4114 (4) ll inteface signals incluing maste clock ae fe extenally. (1) Evaluation of Loopback moe using the K4114 X tal oscillato (X1) M is use. (1-1) Slave moe <Default> JP1 : Shot JP2 : Shot SW3-1 (XTL1) : H SW3-2 (XTL0) : L SW3-7 (CM0) : H Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 moe 4 (HPF:ON, uio Fomat: I 2 S) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-3) (SW3-4) (SW3-5) (SW3-6) Nomal L H L L L H H L Double L H L L L H L L Qua L H L L L H H H (1-2) Maste moe JP1 : Shot JP2 : Shot SW3-1 (XTL1) : H SW3-2 (XTL0) : L SW3-3 (DIF1) : H SW3-4 (DIF0) : H SW3-7 (CM0) : H Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 Maste moe (HPF:ON, uio Fomat: I 2 S) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-5) (SW3-6) Nomal H H L H H L Double H H L L L L Qua H H H L H H - 3 -

4 [KD4556-] (2) Evaluation of DC using DIR of the K4114 DIR geneates MCLK, CLK, LRCK, an SDT fom eceive ata via optical (PORT1) o NC connecto (J6). (2-1) Slave moe JP1 : Shot JP2 : Shot JP3 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : H SW3-7 (CM0) : L Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 moe 4 (HPF:ON, uio Fomat: I 2 S) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-3) (SW3-4) (SW3-5) (SW3-6) Nomal L H L L L H H L Double L H L L L H L L Qua L H L L L H H H (2-2) Maste moe JP1 : Shot JP2 : Shot JP3 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : H SW3-3 (DIF1) : H SW3-4 (DIF0) : H SW3-7 (CM0) : L Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 Maste moe (HPF:ON, uio Fomat: I 2 S) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-5) (SW3-6) Nomal H H L H H L Double H H L L L L Qua H H H L H H - 4 -

5 [KD4556-] (3) Evaluation of DC using DIT of the K4114 Optical (PORT2) o NC (J7) connecto is use. DIT geneates auio bi-phase signal. (3-1) Slave moe (3-1-1) When using the K4114 s PLL Optical (PORT1) o NC (J6) connecto povies access to the bi-phase signal geneate by the K4114. JP1 : Shot JP2 : Shot JP3,JP4 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : H SW3-7 (CM0) : L (3-1-2) When using X tal oscillato (X1) M JP1 : Shot JP2 : Shot JP4 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : L SW3-7 (CM0) : H Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 Moe 8 (HPF:ON, uio Fomat:LJ) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-3) (SW3-4) (SW3-5) (SW3-6) Nomal H L L L L L H L Double H L L L L L L L Qua H L L L L L H H - 5 -

6 [KD4556-] (3-2) Maste moe (3-2-1) When using the K4114 s PLL Optical (PORT1) o NC (J6) connecto povies access to the bi-phase signal geneate by the K4114. JP1 : Shot JP2 : Shot JP3,JP4 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : H SW3-3 (DIF1) : H SW3-4 (DIF0) : H SW3-7 (CM0) : L (3-2-2) When using X tal oscillato (X1) M JP1 : Shot JP2 : Shot JP4 : OPT o NC SW3-1 (XTL1) : H SW3-2 (XTL0) : L SW3-3 (DIF1) : H SW3-4 (DIF0) : H SW3-7 (CM0) : H Fo the K4556 s sampling spee an auio inteface fomat, efe to Table 3 on page 8. Fo the K4114 s sampling spee an auio inteface fomat, efe to Table 6 an Table 7 on page 9. Example. Setting of the K4556 Maste Moe (HPF:ON, uio Fomat: I 2 S) SW2 K4556 SW3 K4114 Spee CKS3 CKS2 CKS1 CKS0 OCKS1 OCKS0 (SW2-3) (SW2-4) (SW2-5) (SW2-6) (SW3-5) (SW3-6) Nomal H H L H H L Double H H L L L L Qua H H H L H H - 6 -

7 [KD4556-] (4) ll inteface signals incluing maste clock ae fe extenally. PORT3 is use. (4-1) Slave moe JP1 : Open JP2 : Open SW3-3 (DIF1) : H SW3-4 (DIF0) : H In slave moe, the K4556 s sampling spee an auio inteface fomat is set by SW2. See Table 1 on page 8 fo possible moe setting. (4-2) Maste moe JP1 : Open JP2 : Open SW3-3 (DIF1) : H SW3-4 (DIF0) : H In maste moe, the K4556 s sampling spee an auio inteface fomat is set by SW2. See Table 1 on page 8 fo possible moe setting

8 [KD4556-] Setting of DIP SW 1. Evaluation moe setting of SW2 (K4556) No. Name Default 1 DEM1 L 2 DEM0 H 3 CKS3 L 4 CKS2 H 5 CKS1 L 6 CKS0 L Table 1. SW2 K4556 Moe Setting DEM1 DEM0 Moe L L 44.1k L H OFF H L 48k H H 32k Table 2. De-emphasis filte contol Moe CKS3 CKS2 CKS1 CKS0 HPF M/S MCLK uio I/F 0 L L L L ON Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) LJ/RJ 512/768fs (Nomal Spee) 1 L L L H ON Slave 256/384/512/768fs (Nomal Spee) LJ/RJ 2 L L H L OFF Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) LJ/RJ 512/768fs (Nomal Spee) 3 L L H H OFF Slave 256/384/512/768fs (Nomal Spee) LJ/RJ 4 L H L L ON Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) I 2 S 512/768fs (Nomal Spee) 5 L H L H ON Slave 256/384/512/768fs (Nomal Spee) I 2 S 6 L H H L OFF Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) I 2 S 512/768fs (Nomal Spee) 7 L H H H OFF Slave 256/384/512/768fs (Nomal Spee) I 2 S 8 H L L L ON Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) LJ 512/768fs (Nomal Spee) 9 H L L H ON Slave 256/384/512/768fs (Nomal Spee) LJ 10 H L H L OFF Slave 128/192fs (Qua Spee) 256/384fs (Double Spee) LJ 512/768fs (Nomal Spee) 11 H L H H OFF Slave 256/384/512/768fs (Nomal Spee) LJ 12 H H L L ON Maste 256fs (Double Spee) I 2 S 13 H H L H ON Maste 512fs (Nomal Spee) I 2 S 14 H H H L ON Maste 128fs (Qua Spee) I 2 S 15 H H H H ON Maste 256fs (Nomal Spee) I 2 S Table 3. K4556 Moe Settting In case of the K4556 evaluation using the K4114, LJ/RJ (Moe 0 ~ Moe 3) in uio I/F oes not suppot

9 [KD4556-] 2. Evaluation moe setting of SW3 (K4114) No. Name Default 1 XTL1 H 2 XTL0 L 3 DIF1 L 4 DIF0 H 5 OCKS1 L 6 OCKS0 L 7 CM0 H Table 4. SW3 K4114 Moe Setting XTL1 XTL0 X tal Fequency L L M L H M H L M H H OFF Table 5. Refeence X tal Fequency DIF1 DIF0 DUX SDTO LRCK,CLK L L 24bit LJ 24bit LJ O L H 24bit I 2 S 24bit I 2 S O H H 24bit I 2 S 24bit I 2 S I Table 6. uio Data Fomat OCKS1 OCKS0 MCKO1 X tal fs Max Spee L L 256fs 256fs 96k Double H L 512fs 512fs 48k Nomal H H 128fs 128fs 192k Qua Table 7. Maste Clock Output Fequency CM0 PLL Clock Souce SDTO L ON PLL RX H OFF X tal DUX Table 8. Clock Opeation Moe Jumpe pins set up [JP1] : MCLK Shot Open [JP2] : SDTI Shot Open : MCLK is supplie fom the K4114. : MCLK is supplie fom PORT3. : SDTI is supplie fom the K4114. : SDTI is supplie fom PORT3. [JP3] : RX (DIR) OPT : Optical connecto (PORT1) is use. NC : NC connecto (J5) is use. [JP4] : TX (DIT) OPT : Optical connecto (PORT2) is use. NC : NC connecto (J6) is use

10 [KD4556-] nalog input cicuit J1 RIN C7 10u + RIN J2 LIN C8 10u + LIN Figue 2. nalog Input Cicuit nalog output cicuit ROUT + C9 22u R9 10k R8 220 J3 ROUT LOUT + C10 22u R10 10k R J4 LOUT Figue 3. nalog Output Cicuit

11 [KD4556-] MESUREMENT RESULTS [Measuement conition] Measuement unit: uio Pecision, System two Cascae Slave Moe CLK: 64fs it: 24bit Measuement Fequency: Nomal Spee : 20 20k, Double & Qua Spee : 20 40k Powe Supply: V=VD=3.3 V Tempeatue: Room Input Fequency: 1k Sampling Fequency: 48k, 96k, 192k [Measuement Results] DC (LIN/RIN) chaacteistics Sampling Fequency Paamete Conition Filte L ch R ch Units S / (N+D) -1 Input 20kLPF k DR Input 20kLPF DR Input -weighte S/N No Signal -weighte k 192k S / (N+D) -1 Input 40kLPF DR Input 40kLPF DR Input -weighte S/N No Signal -weighte S / (N+D) -1 Input 40kLPF DR Input 40k LPF DR Input -weighte S/N No Signal -weighte DC (LOUT/ROUT) chaacteistics Sampling Fequency Paamete Conition Filte L [] R [] Units S / (N+D) 0 Input 20kLPF k DR Input 20kLPF DR Input -weighte S/N No Signal -weighte k 192k S / (N+D) 0 Input 40kLPF DR Input 40kLPF DR Input -weighte S/N No Signal -weighte S / (N+D) 0 Input 40kLPF DR Input 40k LPF DR Input -weighte S/N No Signal -weighte

12 [KD4556-] [Plots] DC fs=48k F S K4556 DC FFT fs=48k, -1 Input k 2k 5k 10k 20k Figue 4. FFT (fin=1k, Input Level=-1FS) F S K4556 DC FFT fs=48k, Input k 2k 5k 10k 20k Figue 5. FFT (fin=1k, Input Level=FS)

13 [KD4556-] F S K4556 DC FFT fs=48k, No Signal k 2k 5k 10k 20k Figue 6. FFT (fin=1k, No Signal) K4556 DC THD + N vs Input Level fs=48k F S Figue 7. THD+N vs Input Level (fin=1k)

14 [KD4556-] K4556 DC THD + N vs Input Fequency fs=48k F S k 2k 5k 10k 20k Figue 8. THD+N vs Input Fequency (Input Level =-1FS) K4556 DC Lineaity fs=48k F S Figue 9. Lineaity (fin=1k)

15 [KD4556-] K4556 DC Feqency Response fs=48k F S k 2k 5k 10k 20k Figue 10. Fequency Response -85 K4556 DC Cosstalk fs=48k k 2k 5k 10k 20k Figue 11. Cosstalk

16 [KD4556-] fs=96k F S K4556 DC FFT fs=96k, -1 Input k 2k 5k 10k 20k 40k Figue 12. FFT (fin=1k, Input Level=-1FS) F S K4556 DC FFT fs=96k, Input k 2k 5k 10k 20k 40k Figue 13. FFT (fin=1k, Input Level=FS)

17 [KD4556-] F S K4556 DC FFT fs=96k, No Signal k 2k 5k 10k 20k 40k Figue 14. FFT (fin=1k, No Signal) K4556 DC THD + N vs Input Level fs=96k F S Figue 15. THD+N vs Input Level (fin=1k)

18 [KD4556-] K4556 DC THD + N vs Input Fequency fs=96k F S k 2k 5k 10k 20k 40k Figue 16. THD+N vs Input Fequency (Input Level =-1FS) K4556 DC Lineaity fs=96k F S Figue 17. Lineaity (fin=1k)

19 [KD4556-] K4556 DC Feqency Response fs=96k F S k 2k 5k 10k 20k 40k Figue 18. Fequency Response -85 K4556 DC Cosstalk fs=96k k 2k 5k 10k 20k 40k Figue 19. Cosstalk

20 [KD4556-] fs=192k F S K4556 DC FFT fs=192k, -1 Input k 2k 5k 10k 20k 50k 80k Figue 20. FFT (fin=1k, Input Level=-1FS) F S K4556 DC FFT fs=192k, Input k 2k 5k 10k 20k 50k 80k Figue 21. FFT (fin=1k, Input Level=FS)

21 [KD4556-] F S K4556 DC FFT fs=192k, No Signal k 2k 5k 10k 20k 50k 80k Figue 22. FFT (fin=1k, No Signal) K4556 DC THD + N vs Input Level fs=192k F S Figue 23. THD+N vs Input Level (fin=1k)

22 [KD4556-] K4556 DC THD + N vs Input Fequency fs=192k F S k 2k 5k 10k 20k 50k 80k Figue 24. THD+N vs Input Fequency (Input Level =-1FS) K4556 DC Lineaity fs=192k F S Figue 25. Lineaity (fin=1k)

23 [KD4556-] K4556 DC Feqency Response fs=192k F S k 2k 5k 10k 20k 50k 80k Figue 26. Fequency Response -85 K4556 DC Cosstalk fs=192k k 2k 5k 10k 20k 50k 80k Figue 27. Cosstalk

24 [KD4556-] DC fs=48k K4556 DC FFT fs=48k 0 Input k 2k 5k 10k 20k Figue 28. FFT (fin=1k, Input Level=0FS) K4556 DC FFT fs=48k, Notch Filte k 2k 5k 10k 20k Figue 29. FFT (fin=1k, Input Level=0FS, Notch Filte)

25 [KD4556-] K4556 DC FFT fs=48k, Input k 2k 5k 10k 20k Figue 30. FFT (fin=1k, Input Level=FS) K4556 DC FFT fs=48k, No Signal k 2k 5k 10k 20k Figue 31. FFT (fin=1k, No Signal)

26 [KD4556-] K4556 DC THD + N vs Input Level fs=48k FS Figue 32. THD+N vs Input Level (fin=1k) K4556 DC THD + N vs Input Fequency fs=48k k 2k 5k 10k 20k Figue 33. THD+N vs Input Fequency (Input Level =0FS)

27 [KD4556-] K4556 DC Lineaity fs=48k FS Figue 34. Lineaity (fin=1k) +2 K4556 DC Fequency Response fs=48k k 2k 5k 10k 20k Figue 35. Fequency Response

28 [KD4556-] -85 K4556 DC Cosstalk fs=48k k 2k 5k 10k 20k Figue 36. Cosstalk

29 [KD4556-] fs=96k K4556 DC FFT fs=96k, 0 Input k 2k 5k 10k 20k 40k Figue 37. FFT (fin=1k, Input Level=0FS) K4556 DC FFT fs=96k, Notch Filte k 2k 5k 10k 20k 40k Figue 38. FFT (fin=1k, Input Level=0FS, Notch Filte)

30 [KD4556-] K4556 DC FFT fs=96k, Input k 2k 5k 10k 20k 40k Figue 39. FFT (fin=1k, Input Level=FS) K4556 DC FFT fs=96k, No Signal k 2k 5k 10k 20k 40k Figue 40. FFT (fin=1k, No Signal)

31 [KD4556-] K4556 DC THD + N vs Input Level fs=96k FS Figue 41. THD+N vs Input Level (fin=1k) K4556 DC THD + N vs Input Fequency fs=96k k 2k 5k 10k 20k 40k Figue 42. THD+N vs Input Fequency (Input Level =-1FS)

32 [KD4556-] K4556 DC Lineaity fs=96k FS Figue 43. Lineaity (fin=1k) +2 K4556 DC Fequency Response fs=96k k 2k 5k 10k 20k 40k Figue 44. Fequency Response

33 [KD4556-] -85 K4556 DC Cosstalk fs=96k k 2k 5k 10k 20k 40k Figue 45. Cosstalk

34 [KD4556-] fs=192k K4556 DC FFT fs=192k, 0 Input k 2k 5k 10k 20k 50k 80k Figue 46. FFT (fin=1k, Input Level=0FS) K4556 DC FFT fs=192k, Notch Filte k 2k 5k 10k 20k 50k 80k Figue 47. FFT (fin=1k, Input Level=0FS, Notch Filte)

35 [KD4556-] K4556 DC FFT fs=192k, Input k 2k 5k 10k 20k 50k 80k Figue 48. FFT (fin=1k, Input Level=FS) K4556 DC FFT fs=192k, No Signal k 2k 5k 10k 20k 50k 80k Figue 49. FFT (fin=1k, No Signal)

36 [KD4556-] K4556 DC THD + N vs Input Level fs=192k FS Figue 50. THD+N vs Input Level (fin=1k) K4556 DC THD + N vs Input Fequency fs=192k k 2k 5k 10k 20k 40k Figue 51. THD+N vs Input Fequency (Input Level =0FS)

37 [KD4556-] K4556 DC Lineaity fs=192k FS Figue 52. Lineaity (fin=1k) +2 K4556 DC Fequency Response fs=192k k 2k 5k 10k 20k 50k 80k Figue 53. Fequency Response

38 [KD4556-] -85 K4556 DC Cosstalk fs=192k k 2k 5k 10k 20k 40k Figue 54. Cosstalk

39 [KD4556-] Revision Histoy Date (YY/MM/DD) Manual Revision oa Revision Reason 06/05/18 KM Fist Eition 06/08/25 KM Change evice evision Contents K4556 Rev. Rev. Table Data & Plot Data wee upate. IMPORTNT NOTICE These poucts an thei specifications ae subject to change without notice. efoe consieing any use o application, consult the sahi Kasei Micosystems Co., Lt. () sales office o authoize istibuto concening thei cuent status. assumes no liability fo infingement of any patent, intellectual popety, o othe ight in the application o use of any infomation containe heein. ny expot of these poucts, o evices o systems containing them, may equie an expot license o othe official appoval une the law an egulations of the county of expot petaining to customs an taiffs, cuency exchange, o stategic mateials. poucts ae neithe intene no authoize fo use as citical components in any safety, life suppot, o othe haza elate evice o system, an assumes no esponsibility elating to any such use, except with the expess witten consent of the Repesentative Diecto of. s use hee: (a) haza elate evice o system is one esigne o intene fo life suppot o maintenance of safety o fo applications in meicine, aeospace, nuclea enegy, o othe fiels, in which its failue to function o pefom may easonably be expecte to esult in loss of life o in significant injuy o amage to peson o popety. (b) citical component is one whose failue to function o pefom may easonably be expecte to esult, whethe iectly o iniectly, in the loss of the safety o effectiveness of the evice o system containing it, an which must theefoe meet vey high stanas of pefomance an eliability. It is the esponsibility of the buye o istibuto of an pouct who istibutes, isposes of, o othewise places the pouct with a thi paty to notify that paty in avance of the above content an conitions, an the buye o istibuto agees to assume any an all esponsibility an liability fo an hol hamless fom any an all claims aising fom the use of sai pouct in the absence of such notification

40 C D E VCC T1 LT E + C17 47u 3 C14 0.1u IN GND 1 OUT 2 C16 0.1u + C15 47u V DGND GND E 3 T2 LT IN GND OUT 2 fo 74HC V C13 0.1u 1 C11 0.1u + C12 47u C18 0.1u VDD D D J1 RIN C7 10u + R8 220 J3 ROUT + U1 C9 22u R9 10k C J2 LIN C8 10u + V R C3 10u C5 10u + + C4 0.1u C6 0.1u RIN LIN VSS V VD ROUT 20 LOUT 19 VCOM 18 PDN 17 CLK 16 C1 0.1u + C2 2.2u R1 51 PDN CLK + C10 22u R10 10k R J4 LOUT C DEM0 6 DEM0 MCLK 15 R2 51 MCLK DEM1 7 DEM1 LRCK 14 R3 51 LRCK SDTO R SDTO SDTI 13 R5 51 SDTI CKS0 9 CKS0 CKS3 12 CKS3 CKS1 10 CKS1 CKS2 11 CKS2 K4556 C D Title KD4556- Size Document Numbe Rev 3 K Date: Fiay, ugust 25, 2006 Sheet 1 of 2 E

41 MCLK D PORT1 VCC 3 GND 2 OUT 1 TORX141 J5 NC RX RX L1 (shot) V C20 + C24 0.1u 10u R13 +10u C25 + OPT C u JP3 JP1 RX MCLK R14 NC 18k C22 C23 R15 0.1u 0.47u JP2 75 SDTI R24 R25 220k 220k RX3 48 VSS 47 RX2 46 TEST1 45 RX1 44 VSS 43 RX0 42 VSS 41 VCOM 40 R 39 VDD INT1 VDD R26 220k R27 220k MCLK ICK LRCK SDTI VCC PORT SDTO DSP CLK LRCK SDTI SDTO D C C26 5p C27 5p PORT2 IN 3 VCC 2 GND 1 TOTX141 J6 NC TX TX 1 2 XTI XTO M 1:1 X1 T4 D02 C28 0.1u +3.3V R R V DIF0/RX5 DIF1/RX6 XTL0 XTL1 +3.3V JP4 OPT TX NC 1 IPS0/RX4 2 VSS 3 DIF0/RX5 4 TEST2 5 DIF1/RX6 6 VSS 7 DIF2/RX7 8 IPS1/IIC 9 P/SN 10 XTL0 11 XTL1 12 VIN R XTI XTO +3.3V OCKS0 OCKS1 CM0 PDN XTL1 XTL0 DIF1 DIF0 OCKS1 OCKS0 CM0 +3.3V +3.3V DEM1 DEM0 CKS3 CKS2 CKS1 CKS0 +3.3V C L 0.1u C33 PDN XTL1 XTL0 DIF1/RX6 DIF0/RX5 OCKS1 OCKS0 CM0 DEM1 DEM0 CKS3 CKS2 CKS1 CKS0 14 U3F C29 10u + U2 K4114 TVDD DVSS TX0 TX1 OUT COUT UOUT VOUT DVDD DVSS MCKO1 LRCK C30 0.1u INT0 36 OCKS0/CSN 35 OCKS1/CCLK 34 CM1/CDTI 33 CM0/CDTO 32 PDN XTI 30 XTO 29 DUX 28 MCKO2 27 ICK 26 SDTO 25 C31 0.1u C32 10u U3C 74HC14 K4114 Moe Setting SW R20 10k K4556 Moe Setting SW V 1S1588 H SW1 PDN D1 R16 10k V U U3 74HC14 74HC U3D HC14 U3E 74HC14 RP2 47K RP1 47k Title KD4556- Size Document Numbe Rev 3 1 DIT/DIR Date: Fiay, ugust 25, 2006 Sheet 2 of 2 1

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