8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC AD8842

Transcription

1 a FEATUES Low Cost eplaces 8 Potentiometers 5 khz -Quadrant Multiplying Bandwidth Low Zero Output Error Eight Individual Channels 3-Wire Serial Input 5 khz Update Data Loading ate ±3 V Output Swing Midscale Preset, Zero Volts Out APPLICATIONS Automatic Adjustment Trimmer eplacement Vertical Deflection Amplitude Adjustment Waveform Generation and Modulation V DD 8-Bit Octal, -Quadrant Multiplying, CMOS TrimDAC AD88 8 FUNCTIONAL BLOCK DIAGAM DECODED ADDESS LOGIC DATA 8 SEIAL EGISTE GND SDO 8 X 8 DAC E G I S T E S P 8 8 DAC A DAC H G AD88 G V SS A V OUTA H V OUTH GENEAL DESCIPTION The AD88 provides eight general purpose digitally controlled voltage adjustment devices. The TrimDAC capability allows replacement of the mechanical trimmer function in new designs. The AD88 is ideal for ac or dc gain control of up to 5 khz bandwidth signals. The four-quadrant multiplying capability is useful for signal inversion and modulation often found in video vertical deflection circuitry. Internally the AD88 contains eight voltage output digital-toanalog converters, each with separate voltage inputs. A new current conveyor amplifier design performs the four-quadrant multiplying function with a single amplifier at the output of the current steering digital-to-analog converter. This approach offers an improved constant input resistance performance versus previous voltage switched DACs used in TrimDAC circuits, eliminating the need for additional input buffer amplifiers. Each DAC has its own DAC register that holds its output state. These DAC registers are updated from an internal serial-toparallel shift register that is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded where the first bits determine the address of the DAC register to be loaded with the last 8 bits of data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple DAC applications without additional external decoding logic. TrimDAC is a registered trademark of Analog Devices, Inc. The current conveyor amplifier is a patented circuit belonging to Analog Devices, Inc. The AD88 consumes only 95 mw from ±5 V power supplies. For single 5 V supply applications consult the DAC-88. The AD88 is pin compatible with the MHz multiplying bandwidth DAC88. The AD88 is available in -pin plastic DIP and surface mount SOL- packages. V OUT = (D/8 ) V OUT Figure. Functional Circuit of One -Quadrant Multiplying Channel EF D 56 (- D) 56 CUENT CONVEYO AMPLIFIE V OUT I = (D/8 ) Figure. Actual Current Conveyor Implementation of Multiplying DAC Channel I EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood. MA 6-96, U.S.A. Tel: 78/39-7 Fax: 78/6-33

2 SPECIFICATIONS ELECTICAL CHAACTEISTICS Parameter Symbol Conditions Min Typ Max Units STATIC ACCUACY All Specifications Apply for DACs A, B, C, D, E, F, G, H esolution N 8 Bits Integral Nonlinearity Error INL ±. ± LSB Differential Nonlinearity DNL All Devices Monotonic ±. ± LSB Full-Scale Gain Error G FSE LSB Output Offset V BZE P =, Sets D = 8 H 5 5 mv Output Offset Drift TCV BZ P =, Sets D = 8 H 5 µv/ C VOLTAGE INPUTS Applies to All Inputs x Input Voltage ange IV ±3 ± V Input esistance IN 9 kω Input Capacitance C IN 9 pf DAC OUTPUTS Applies to All Outputs V OUT x Voltage ange OV L = kω ±3 ± V Output Current I OUT V OUT <.5 LSB ±3 ma Capacitive Load C L No Oscillation 5 pf DYNAMIC PEFOMANCE Applies to All DACs Full Power Gain Bandwidth GBW x = ±3 V P, L = kω, C L = pf 5 khz Slew ate Measured % to 9% Positive S+ V OUT x = +5.5 V.5. V/µs Negative S V OUT x = 5.5 V..8 V/µs Total Harmonic Distortion THD x = V p-p, D = FF H, f = khz,. % f LPF = 8 khz, L = kω Spot Noise Voltage e N f = khz, = V 78 nv/ Hz Output Settling Time t S ± LSB Error Band, D = H to FF H.9 µs D = FF H to H 5. µs Channel-to-Channel Crosstalk C T Measured Between Adjacent Channels, f = khz 7 db Digital Feedthrough Q x = V, D = to 55 5 nv-s POWE SUPPLIES Positive Supply Current I DD P = V ma Negative Supply Current I SS P = V 9 3 ma Power Dissipation P DISS mw Power Supply ejection PS P = V, V DD = ± 5%.. %/% Power Supply ange PS V DD, V SS V DIGITAL INPUTS Logic High V IH. V Logic Low V IL.8 V Input Current I L ± µa Input Capacitance C IL 7 pf Input Coding Offset Binary DIGITAL OUTPUT Logic High V OH I OH =. ma 3.5 V Logic Low V OL I OL =.6 ma. V TIMING SPECIFICATIONS Input Clock Pulse Width t CH, t CL 6 ns Data Setup Time t DS ns Data Hold Time t DH ns to SDO Propagation Delay t PD 8 ns DAC egister Load Pulse Width t 7 ns Preset Pulse Width t P 5 ns Clock Edge to Load Time t CK 3 ns Load Edge to Next Clock Edge t CK 6 ns NOTES Guaranteed by design, not subject to production test. Calculated limit = 5 V (I DD + I SS ). Specifications subject to change without notice. (V DD = +5 V, V SS = 5 V, All x = +3 V, T A = C to +85 C, unless otherwise noted.) EV. A

3 A3 A A A D7 D6 D5 D D3 D D D DAC EGISTE LOAD +3V V OUT V DETAIL SEIAL DATA INPUT TIMING (P = ) (DATA IN) Ax or Dx t DS tdh SDO (DATA OUT) t CH t PD t CL t CK t t CK t S +3V ± LSB V OUT V ± LSB EO BAND PESET TIMING P +3V V OUT V t P t S ± LSB EO BAND ± LSB Figure 3. Timing Diagram ABSOLUTE MAXIMUM ATINGS (T A = +5 C unless otherwise noted) V DD to GND V, +7 V V SS to GND V, 7 V x to GND V DD, V SS V OUT x to GND V DD, V SS Short Circuit I OUT x to GND Continuous Digital Input & Output Voltage to GND V DD, V Operating Temperature ange C to +85 C Maximum Junction Temperature (T J Max) C Storage Temperature C to +5 C Lead Temperature (Soldering, sec) C Package Power Dissipation (T J Max T A )/θ JA Thermal esistance θ JA, SOIC (SOL-) C/W P-DIP (N-) C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD88 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WANING! ESD SENSITIVE DEVICE EV. A 3

4 V OUTC V OUTD V OUTB 3 C V OUTA 3 D B V DD A GND P E F V OUTE 5 6 AD88 TOP VIEW 9 7 (Not to Scale) V SS SDO H V OUTF G V OUTG 3 V OUTH

5 Table I. Serial Input Decode Table LAST LSB D D D D3 D D5 D6 MSB D7 LSB A FIST A A MSB A3 DATA ADDESS MSB LSB A3 A A A DAC UPDATED NO OPEATION DAC A DAC B DAC C DAC D DAC H NO OPEATION NO OPEATION MSB LSB D7 D6 D5 D D3 D D D DAC OUTPUT VOLTAGE V OUT = (D/8 ) x (/8 ) x (7/8 ) x (8/8 ) x = V; (PESET VALUE) (9/8 ) x (5/8 ) x (55/8 ) x Table II. Input Logic Control Truth Table P Input Shift egister Operation L L H No Operation L H Shift One Bit in from (Pin ), Shift One Bit* Out from SDO (Pin 8) X L L All DAC egisters = 8 H X Η H Load Serial egister Data into DAC(X) egister X H X Serial Data Input egister Loading Disabled *Data shifted into the pin appears twelve clocks later at the SDO pin. EV. A 5

6 Typical Performance Characteristics. LINEAITY EO LSB +/ / +/ / DACs A, B, C, D SUPEIMPOSED T A = +5 C V DD = +5V V SS = 5V X = +3V DACs E, F, G, H SUPEIMPOSED LINEAITY EO LSB T A = +5 C T A = +5 C T A = 55 C DAC A V DD = +5V V SS = 5V X = +3V VOUT HALF SCALE mv X = +3V X = 3V V DD = +.75V V SS =.75V DIGITAL INPUT CODE Decimal DIGITAL INPUT CODE Decimal TEMPEATUE C Figure. Linearity Error vs. Digital Code Figure 5. Linearity Error vs. Digital Code vs. Temperature Figure 6. V OUT Half Scale (8 H ) vs. Temperature EFEENCE INPUT ESISTANCE kω 9 8 AVG +σ AVG AVG σ = +3V 7 V DD = +.75V V SS =.75V TEMPEATUE C TOTAL HAMONIC DISTOTION %.. = +Vp-p f LPF = 8kHz CODE = FF H 3 L = kω. k k k FEQUENCY Hz VOUT SLEW ATE V/µs V DD = +.75V V SS =.75V = ±3V S+ S TEMPEATUE C Figure 7. Input esistance ( ) vs. Temperature Figure 8. Total Harmonic Distortion vs. Frequency Figure 9. V OUT Slew ate vs. Temperature PHASE Degrees PHASE CODE = ALL ONES GAIN PHASE CODE = ALL ZEOS = ± mv T A = +5 C k k M FEQUENCY Hz FS +FS M 3 GAIN db COSSTALK db INPUT A db OUTPUT B A = mv pp B = V T A = +5 C k k k M M FEQUENCY Hz en NOISE VOLTAGE (µv/ Hz) T A = +5 C = V k k k FEQUENCY Hz Figure. Gain and Phase vs. Frequency (Code = H or FF H ) Figure. DAC Crosstalk vs. Frequency Figure. Voltage Noise Density vs. Frequency 6 EV. A

7 5µs 5µs 5V 9 9 % % V 5µS 5µs V 5µs Figure 3. Pulse esponse Upper V/Div Lower Trace V V/Div Figure 6. Settling Time Upper 5 V/Div, Lower Trace V V/Div 5V 5µs 5µs mv 9 9 % % 5mVV 5µS 5ns 5ns Figure. Worst Case LSB Step Change Code 8 H to 7F H, Upper 5 V/Div, Lower Trace V 5 mv/div Figure 7. Digital Feedthrough V mv/div, = V; Code 7F H to 8 H 5V 5µs 5µs 9 9 % % 5mV V 5µS 5ns 5mV µs Figure 5. Crosstalk V 5 mv/div Figure 8. Clock Feedthrough V 5 mv/div EV. A 7

8 8 V 6 3dB FEQUENCY 9 % V µs OUTPUT AMPLITUDE mv 8 mvp-p INPUT AMPLITUDE 3 5 FEQUENCY MHz Figure 9. khz Sawtooth Waveform, Upper Trace, Lower Trace V OUT Figure. AC Sweep Frequency mv p-p Amplitude esponse OUTPUT AMPLITUDE mv 3 3 3dB FEQUENCY 5 mvp-p INPUT AMPLITUDE SUPPLY CUENT ma 9 8 I V DD = +6V AND V SS = 5V I V DD = +V AND V SS = 5V I V DD = +5V AND V SS = V O 6V X = +3V POWE SUPPLY EJECTION db 3 PS + PS: V DD = +5V±5mV PS: V SS = 5V±5mV + PS 3 FEQUENCY MHz TEMPEATUE C k k k M FEQUENCY Hz Figure. AC Sweep Frequency 5 mv p-p Amplitude esponse Figure. Supply Current vs. Voltage and Temperature Figure 3. PS vs. Frequency GAIN db k k DATA = ØØ H CØ H AØ H 9Ø H 88 H 8 H 8 H 8 H 8 H k FEQUENCY Hz = mv AC T A = +5 C V DD = +5V V SS = 5V M M IOUT ma T A = +5 C V DD = +5V V SS = 5V CODE = 8 H SHOT CICUIT CUENT LIMITING SHOT CICUIT CUENT LIMITING 3 3 V OUTX Volts HALF SCALE OFFSET mv 6 5 = +3V χ + σ χ χ σ T = HOUS OF OPEATION AT 5 C Figure. Gain (V OUT / ) and Feedthrough vs. Frequency Figure 5. Short Circuit Limit Output Current vs. Voltage Figure 6. Output Voltage Drift Accelerated by Burn-In 8 EV. A

9 CICUIT OPEATION The AD88 is a general purpose 8-channel ac or dc signallevel adjustment device designed to replace potentiometers used in the three-terminal connection mode. Eight independent channels of programmable signal level control are available in this -pin package device. The outputs are completely buffered providing up to 3 ma of output drive-current to drive external loads. The functional equivalent DAC and amplifier combination shown in Figure 7 produces four-quadrant multiplication of the signal inputs applied to times the digital input control word. In addition the AD88 provides a 5 khz full power bandwidth in each four-quadrant multiplying channel. Operating from plus and minus 5 V power supplies, analog inputs and outputs of ±3 V are easily accommodated. can be activated at any time to force the DAC registers to the half-scale code 8 H. This is generally the most convenient place to start general purpose adjustment procedures. Achieving -Quadrant Multiplying with a Current Conveyor Amplifier The traditional current output CMOS digital-to-analog converter requires two amplifiers to perform the current-to-voltage translation and the half-scale offset to achieve four-quadrant multiplying capability. The circuit shown in Figure 8 shows one such traditional connection. I / A EF CUENT OUT DAC / V OUT GND A V DAC I V O V DAC = D/56 V OUT = V DAC = (D/56) = (D/8 ) AD88 INPUT-OUTPUT VOLTAGE ANGE D = FFH Figure 8. One Traditional Technique to Achieve Four- Quadrant Multiplying with a Complementary Current Output DAC A single new current conveyor amplifier design emulates amplifiers A and A shown in Figure 8. Figure 9 shows the connection and equations that define this new circuit that achieves four-quadrant multiplication with only one amplifier. D = CH V OUT Volts D = 8H D = H D = H EF D 56 (- D) 56 V EF V EF I I CUENT CONVEYO AMPLIFIE V OUT X V OUT = (D/8 ) Volts V OUT = (D/8 ), WHEE D = TO 55 Figure 7. Functional Equivalent Circuit to the AD88 esults in a -Quadrant Multiplying Channel In order to simplify use with a controlling microprocessor a PCB space saving three-wire serial data interface was chosen. This interface can be easily adapted to almost all microcomputer and microprocessor systems. A clock (), serial data input () and a load () strobe pins make up the three-wire interface. The -bit input data word used to change the value of the internal DAC registers contains a -bit address and 8-bits of data. Using this word combination any DAC register can be changed at a given time without disturbing the other channels. A serial data output SDO pin simplifies cascading multiple AD88s without adding address decoder chips to the system. During system power up a logic low on the preset P pin forces all DAC registers to 8 H which in turn forces all the buffer amplifier outputs to zero volts. This asynchronous input pin P Figure 9. Current Conveyor Amplifier Using the equations given in Figure 9 one can calculate the final output equation as follows: V O = D 56 D 56 D 56 V IN + D 56 = D 56 D = 8 EV. A 9

10 ADJUSTING AC O DC SIGNAL LEVELS The four-quadrant multiplication operation of the AD88 is shown in Figure 7. For dc operation the equation describing the relationship between, digital inputs and V OUT is: V OUT (D) = (D/8-) () where D is a decimal number between and 55 The actual output voltages generated with a fixed 3 V dc input applied to are summarized in this table. Table III. Decimal Comments Input (D) V OUT (D) ( = 3 V) 3. V Inverted FS Zero Output Full Scale (FS) Notice that the output polarity is the same as the input polarity when the DAC register is loaded with 55 (in binary = all ones). Also note that the output does not exactly equal the input voltage. This is a result of the - ladder DAC architecture chosen. When the DAC register is loaded with, the output polarity is inverted and exactly equals the magnitude of the input voltage. The actual voltage measured when setting up a DAC in this example will vary within the ± LSB linearity error specification of the AD88. The calculated voltage error would be ±.3 V (= ±3 V/8). If is an ac signal such as a sine wave, then we can use Equation to describe circuit performance. V OUT (t, D) = (D/8-) A sin (ωt) () where ω = πf, A = sine wave amplitude, and D = decimal input code. This transfer characteristic Equation lends itself to amplitude and phase control of the incoming signal. When the DAC is loaded with all zeros, the output sine wave is shifted by 8 with respect to the input sine wave. This powerful multiplying capability can be used for a wide variety of modulation, waveform adjustment and amplitude control. SIGNAL INPUTS ( A, B, C, D, E, F, G, H) The eight independent inputs have a constant inputresistance nominal value of 9 kω as specified in the electrical characteristics table. These signal-inputs are designed to receive not only dc, but ac input voltages. The signal-input voltage range can operate to within one volt of either supply. That is, the operating input-voltage-range is: V SS + V < x < (V DD V) (3) DAC OUTPUTS (V OUT A, B, C, D, E, F, G, H) The eight D/A converter outputs are fully buffered by the AD88 s internal amplifier. This amplifier is designed to drive up to kω loads in parallel with pf. However, in order to minimize internal device power consumption, it is recommended whenever possible to use larger values of load resistance. The amplifier output stage can handle shorts to GND; however, care should be taken to avoid continuous short circuit operation. The low output impedance of the buffers minimizes crosstalk between analog input channels. A graph (Figure ) of analog crosstalk between channels is provided in the typical performance characteristics section. At khz 7 db of channel-tochannel isolation exists. It is recommended to use good circuit layout practice such as guard traces between analog channels and power supply bypass capacitors. A. µf ceramic in parallel with a µf µf tantalum capacitor provides a good power supply bypass for most frequencies encountered. DIGITAL INTEFACING The four digital input pins (,,, P) of the AD88 were designed for TTL and 5 V CMOS logic compatibility. The SDO output pin offers good fanout in CMOS logic applications and can easily drive several AD88s. The Logic Contro Input Truth Table II describes how to shift data into the internal -bit serial input register. Note that the is a positive-edge sensitive input. If mechanical switches are used for breadboard evaluation, they should be debounced by a flipflop or other suitable means. The basic three-wire serial data interface setup is shown in Figure 3. ZEO VOLTAGE OUTPUT PESET SEIAL DATA CLOCK LOAD STOBE AD88 Figure 3. Basic Three-Wire Serial Interface The required address plus data input format is defined in the serial input decode Table I. Note there are 8 address states that result in no operation (NOP) or activity in the AD88 when the positive edge triggered load-strobe () is activated. This NOP can be used in cascaded applications where only one DAC out of several packages needs updating. The packages not requiring data changes would receive the NOP address, that is, all zeros. It takes clocks on the pin to fully load the serialinput shift-register. Data on the input pin is subject to the timing diagram (Figure 3) data setup and data hold time requirements. After the twelfth clock pulse the processor needs to activate the strobe to have the AD88 decode the serialregister contents and update the target DAC register with the 8- bit data word. This needs to be done before the thirteenth positive clock edge. The timing requirements are provided in the electrical characteristic table and in the Figure 3 timing diagram. After twelve clock edges, data initially loaded into the shift register at appears at the shift register output SDO. A multiple package interface circuit is shown in Figure 3. In this topology all the devices are clocked with the new data; however, only the decoded package address signal updates the target package strobe which is being used as a chip select P +5V 6 9 5V EV. A

11 CLOCK DATA CODED PACKAGE ADDESS W ADDESSS DECODE EN AD88 # Figure 3. Addressing Multiple AD88 Packages There is some digital feedthrough from the digital input pins. Operating the clock only when the DAC registers require updating minimizes the effect of the digital feedthrough on the analog signal channels. Measurements of DAC switch feedthrough shown in the electrical characteristics table were accomplished by grounding the x inputs and cycling the data codes between all zeros and all ones. Under this condition 5 nv-s of feedthrough was measured on the output of the switched DAC channel. An adjacent channel measured less than nv-s of digital crosstalk. The digital feedthrough and crosstalk photographs shown in the typical performance characteristics section display these characteristics (Figures 5 and 7). ANALOG CONNECTIONS OMITTED FO CLAITY AD88 # AD88 #N Figure 3 shows a three-wire interface for a single AD88 that easily cascades for multiple packages. This circuit topology often called daisy chaining requires preformating all the serial data for each package in the chain. In the case of the 3 packages shown a 36 bit data word must be completely clocked into all the AD88 serial data input registers then the strobe would transfer the data bits into the DAC registers updating one DAC in each package. µc PA PA PA DATA CLOCK AD88 # SDO AD88 # SDO AD88 #3 SDO DAC A DAC H DAC A DAC H DAC A DAC H V OU V O Figure 3. Three-Wire Interface Updates Multiple AD88s EV. A

12 OUTLINE DIMENSIONS.8 (3.5).5 (3.75).3 (3.). (5.33) MAX.5 (3.8).3 (3.3).5 (.9). (.56).8 (.6). (.36). (.5) BSC.7 (.78).6 (.5).5 (.) 3.8 (7.).5 (6.35). (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.5) MAX.5 (.38) GAUGE PLANE.35 (8.6).3 (7.87).3 (7.6).3 (.9) MAX.95 (.95).3 (3.3).5 (.9). (.36). (.5).8 (.) COMPLIANT TO JEDEC STANDADS MS- CONTOLLING DIMENSIONS AE IN INCHES; MILLIMETE DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF INCH EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. CONE LEADS MAY BE CONFIGUED AS WHOLE O HALF LEADS. Figure 33. -Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N--) Dimensions shown in inches and (millimeters) 76-A 5.6 (.6) 5. (.598) (.99) 7. (.93).65 (.93). (.3937).3 (.8). (.39) COPLANAITY.65 (.3).35 (.95)..7 (.5).5 (.) SEATING.33 (.3) BSC PLANE.3 (.). (.79) 8.75 (.95).5 (.98) 5.7 (.5). (.57) COMPLIANT TO JEDEC STANDADS MS-3-AD CONTOLLING DIMENSIONS AE IN MILLIMETES; INCH DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF MILLIMETE EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure 3. -Lead Standard Small Outline Package [SOIC_W] Wide Body (W-) Dimensions shown in millimeters and (inches) -9--A EV. A

13 ODEING GUIDE Model Temperature ange Package Description Package Option AD88AN C to +85 C -Lead PDIP N-- AD88ANZ C to +85 C -Lead PDIP N-- AD88A C to +85 C -Lead SOIC_W W- AD88A-EEL C to +85 C -Lead SOIC_W W- AD88AZ C to +85 C -Lead SOIC_W W- AD88AZ-EEL C to +85 C -Lead SOIC_W W- Z = ohs Compliant Part. EVISION HISTOY / ev. to ev. A Changes to Pin 3 Mnemonic... Updated Outline Dimensions... Changes to Ordering Guide... 3 /9 evision : Initial Version 99 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--/(A) EV. A 3