Minimizing Ringing and Crosstalk

Transcription

1 Minimizing Ringing and Cosstalk By Glen Dash, Ampyx LLC, GlenDash at alum.mit.edu Copyight 1998, 26 Ampyx LLC When viewed on a schematic, a wie is just a wie. Howeve, when isetimes shink to a few nanoseconds o less, wies become adiatos. To conduct signals with good fidelity at these speeds, wies should be paied with thei etuns, foming tansmission lines. A wie ove a etun plane foms a kind of tansmission line known as a micostip. A tace between two plans foms a stipline. Both must be well designed to avoid inging and cosstalk. To avoid inging, impedances must be matched. To avoid cosstalk, spacings must be selected with cae. Even in an age of automated outing checks and signal integity softwae, contolling inging and cosstalk is pat science, pat at. Tansmission line effects become significant when the tace is long enough, o the isetime is fast enough, fo popagation times to be significant. One oft-cited ule of thumb states the following (Refeence 4): Whee: Maximum Length fo a Micostip = 9 t MaximumLength fo a Stipline = 7 t Maximum Length = Maximum length of the tace in centimetes befoe tansmission line effects must be consideed. t = Risetime in nanoseconds Fo a isetime of.9 nsec, this tanslates to 8.1 cm fo micostips and 6.3 cm fo stiplines. Since it is aely possible to keep all taces so shot, impedances need to be matched to contol inging. One of these fou impedance-matching methods ae geneally applied: 1) Seies temination in standad o sta topogaphy, 2) DC paallel temination, 3) AC paallel temination, o 4) Diode temination. Of these, seies temination is the clea favoite among digital hadwae designes. Its advantage is in its simplicity. Its chief disadvantage is in its implementation. Accuately calculating a ealwold tansmission line s impedance can be ticky.

2 Figue 1: Of the topologies available to designes, the seies temination is a clea favoite among digital designes. A sta topology can be used to dive widely spaced loads. DC paallel temination is a moden name fo the taditional impedance matching topology used by communications enginees. Conceptually, it is the most staight-fowad. A load impedance is chosen to match the impedance of the tansmission line. Fo logic cicuits, howeve, DC

3 paallel temination has significant disadvantages and is aely used. It lowes the impedance as seen fom the dive and inceases powe dissipation. AC paallel temination solves some of these poblems. Its chief disadvantage is in its need fo a capacito at the load end. Diode temination woks as follows. Since the impedance of a diode changes dynamically with cuent, it is possible to dynamically match the impedance of a tansmission line. In pactice, howeve, diode temination can be difficult to implement. Vey fast diodes ae equied and nonlinea effects can be geneated. Fo topologies othe than diode temination, pope implementation equies that the tansmission line impedance be known. Handbook fomulas such as those shown in the table povide insight, but in pactice ae often inadequate. Fo example, autho Douglas Books points out that the fomula fo an embedded micostip shown below can only be consideed eliable if the same dielectic mateial is used both above and below the signal tace, and if the dielectic above the tace is moe than 4 mils thick. Simila limitations apply to othe the fomulas.

4 Table 1: Chaacteistic Impedances of Micostips and Stiplines Fo a Micostip: Z C Z = H ln ε W + T ( ε ).67 = 5.98H ln.8w + T H = ln ε '.8W + T Fo an Embedded Micostip: Whee : ' = 1 e 1.55H1 H Fo a Stipline: C Z C 1.41' = 5.98H ln.8w + T 6 1.9(2H + T) = ln ε.8w + T 1.41ε = 3.81H ln.8w + T Notes: Z is in ohms, C is in pf/inch. See Figue 2 fo dimensions. Afte Refeence 2.

5 Figue 2: Tansmission line types commonly used in PCB designs. Fo chaacteistic impedance and capacitance pe unit length, see Table 1. (Afte Refeence 2.) Fotunately, softwae is widely available that takes such mattes into consideation. Fo feewae vesions, check out Pola Instument s site at designe Bay Olney s site at o UltaCad Design s site at Once the chaacteistic impedance has been established, the topology best suited fo implementing seies temination depends on (1) the numbe of loads diven and (2) thei physical poximity. When a single dive is diving a single load o a goup of loads placed in close poximity the matching esisto (R) should be equal to the chaacteistic impedance (Z) minus the esistance of the dive (RO). (Typical tace impedances ae 6 to 1 ohms, and dive impedances, 2 to 2 ohms.) Whee loads ae widely sepaated, a scheme known as sta outing can be used which places a sepaate esisto in each line (Figue 1). Note that the impedance as

6 seen by the dive is equal to impedance of all the connections in paallel. In ode to pevent excessive loading, the paallel impedance of all these taces must be much geate than the output impedance of the dive. Dive limitations can cop up even when elatively few banches ae used, and well befoe the device s fan out is eached. Pedicting exactly what happens to a tansmitted pulse when seies temination is used can be complex. Motoola povides a useful efeence (Refeence 6 below). Since seies temination matches the souce end of the line, pulses sent down the line ae eflected and absobed at the souce end. Because of that, a type of distotion known as stai casing is inheent in the design and must be kept within acceptable limits. Cosstalk is a pimaily a nea field phenomenon. Depending on the elative placement of souce and victim taces, it can be analyzed pimaily as an electic field poblem (voltage diven, capacitive in natue) o a magnetic field poblem (cuent diven, inductive in natue). As a geneal ule, taces placed one ove anothe will pimaily exhibit capacitive coupling, wheeas two taces placed side by side pimaily couple magnetically. We will efe to the two as examples of capacitive and inductive cosstalk espectively. Capacitive cosstalk is the easiest gasp. The two taces fom a capacito. Minimizing poblems means minimizing the size of the capacito. Theefoe, high-speed taces on adjacent layes of a pinted cicuit boad should not be un one on top of the othe. Such taces, if cossed at all, should coss at ight angles, limiting the aea of the capacito fomed. Figue 3: Two taces placed one on top of the othe as in (a) pimaily couple capacitively. Taces placed side by side as in (b) pimaily couple inductively.

7 Figue 4: A diven tace placed side by side with a victim tace poduces both fowad and backwad moving signals on the victim line. Of these, the backwad moving signal is geneally consideed the most toublesome. Two taces placed side-by-side as in Figue 3(b) fom a kind of tansfome. The magnetic field poduced by one couples to the othe. The coupled signals tavel down the victim line both towad the load and backwads towad the souce. In pactice, it is the backwad cosstalk that geneally poves to be the most toublesome. The degee of inductive cosstalk expeienced is lagely due to thee factos: (1) the common length of the two taces, (2) the edge-to-edge sepaation between taces, and (3) the distance between the taces and the neaest powe plane. Obviously, the most staightfowad method of educing inductive cosstalk is to shoten the common length among any two taces. But this solution is often not as pactical as it at fist might seem. To see why this is so, think of the two taces as two windings on a tansfome. The coupling between the diven and victim line is analogous to the coupling coefficient of a tansfome. As a pactical matte, this coupling coefficient gets nea unity fo closely spaced, paallel taces even if they un paallel fo only a few inches. Once the coupling is at unity, making the taces longe will not hut much. Convesely, making them slightly shote will not help much eithe. The common length at which coupling appoaches unity is known as the citical length o the satuation point.

8 Figue 5: The citical length fo two closely spaced paallel taces is the common length at which the coupling coefficient is close to one. Beyond this point, making the common length longe will not make things wose, no will shotening the taces slightly make things much bette. Theefoe, it is often bette to concentate on the tace-to-tace spacing and the distance above the neaest powe plane as illustated in Figue 6. (Afte Refeence 3.)

9 Figue 6: Once the height above the neaest powe plane is known, tace to tace spacing can be selected to educe coupling to an acceptable level. (Afte Refeence 3.) Because the citical point is eached so eadily, it is often moe pactical to focus on two othe factos which affect inductive cosstalk, the spacing between the taces and thei height above the neaest powe plane. We will want to keep coupling below a pemissible level, say 5% fo TTL to TTL coupling. Figue 6 can be used as a guide. Fo example, if the height above the neaest gound plane is 5 mils, use a tace-to-tace sepaation of appoximately 15 mils. If the height is 1 mils, the tace-to-tace sepaation will have to be close to 3 mils. The amount of coupling allowed should be tailoed to the technology used. Five pecent is usually sufficient when both the victim line and the diven line ae MOS, o both ae TTL. In the case of mixed logic, such as when a MOS line uns paallel to an ECL o PCI bus, less coupling should be allowed. See Refeence 3.

10 Refeences: 1. S. Kaufe and K. Cisafulli, Teminating Taces on High Speed PCBs. Pinted Cicuit Design, Mach 1998, Page D. Books, High Speed PCB Impedance Contol, Pinted Cicuit Design, Mach 1998, Page L. Ritchey, Cosstalk o Coupling, A Silent Poblem, Pinted Cicuit Design, Mach 1998, Page M. Montose, Pinted Cicuit Boad Design Techniques fo EMC Compliance, IEEE Pess, 1996, Page Design Guidelines Fo Electonic Packaging Utilizing High Speed Techniques, IPC-D-317, Apil 199, Pages MECL System Design Handbook, Revision 1, Motoola Semiconducto Poducts 1988, Page 157.