24-Bit, 96 khz Stereo DAC for Audio

Transcription

1 Featues 24it, 96 k Steeo DC fo uio l Complete Steeo DC System: Intepolation, D/, Output nalog Filteing l 101 Dynamic Range l 91 THD+N l Low Clock Jitte Sensitivity l +3 V to +5 V Powe Supply l Filtee Line Level Outputs l OnChip Digital Deemphasis fo 32, 44.1, an 48 k l 30 mw with 3 V supply l Popgua Technology fo Contol of Clicks an Pops Desciption CS4340 The CS4340 is a complete steeo igitaltoanalog system incluing igital intepolation, fouthoe eltasigma igitaltoanalog convesion, igital eemphasis an switche capacito analog filteing. The avantages of this achitectue inclue: ieal iffeential lineaity, no istotion mechanisms ue to esisto matching eos, no lineaity ift ove time an tempeatue an a high toleance to clock jitte. The CS4340 accepts ata at auio sample ates fom 2 k to 100 k, consumes vey little powe, an opeates ove a wie powe supply ange. The featues of the CS4340 ae ieal fo DVD playes, CD playes, settop box an automotive systems. I ORDERING INFORMTION CS4340KS 16pin SOIC, 10 to 70 C CS4340S 16pin SOIC, 40 to 85 C CD4340 Evaluation oa SCLK/DEM1 DEM0 MUTEC RST Deemphasis Extenal Mute Contol LRCK SDT Seial Input Inteface Intepolation Filte Intepolation Filte Σ DC Σ DC nalog Filte nalog Filte OUTL OUTR DIF0 DIF1 MCLK Peliminay Pouct Infomation This ocument contains infomation fo a new pouct. Cius Logic eseves the ight to moify this pouct without notice. P.O. ox 17847, ustin, Texas (512) FX: (512) Copyight Cius Logic, Inc (ll Rights Reseve) NOV 00 DS297PP3 1

2 TLE OF CONTENT 1. CHRCTERISTICS ND SPECIFICTIONS... 5 NLOG CHRCTERISTICS... 5 NLOG CHRCTERISTICS... 6 NLOG CHRCTERISTICS... 7 POWER ND THERML CHRCTERISTICS... 8 DIGITL CHRCTERISTICS... 8 RECOMMENDED OPERTING CONDITIONS... 9 SWITCHING CHRCTERISTICS TYPICL CONNECTION DIGRM PIN DESCRIPTION PPLICTIONS Gouning an Powe Supply Decoupling Ovesampling Moes Recommene Poweup Sequence Popgua Tansient Contol INTERPOLTION FILTER RESPONSE PLOTS DIGITL INTERFCE FORMTS NLOG PERFORMNCE PLOTS PRMETER DEFINITIONS Total Hamonic Distotion + Noise (THD+N) Dynamic Range Intechannel Isolation Intechannel Gain Mismatch Gain Eo Gain Dift REFERENCES PCKGE DIMENSIONS Contacting Cius Logic Suppot Fo a complete listing of Diect Sales, Distibuto, an Sales Repesentative contacts, visit the Cius Logic web site at: Peliminay pouct infomation escibes poucts which ae in pouction, but fo which full chaacteization ata is not yet available. vance pouct infomation escibes poucts which ae in evelopment an subject to evelopment changes. Cius Logic, Inc. has mae best effots to ensue that the infomation containe in this ocument is accuate an eliable. Howeve, the infomation is subject to change without notice an is povie S IS without waanty of any kin (expess o implie). No esponsibility is assume by Cius Logic, Inc. fo the use of this infomation, no fo infingements of patents o othe ights of thi paties. This ocument is the popety of Cius Logic, Inc. an implies no license une patents, copyights, taemaks, o tae secets. No pat of this publication may be copie, epouce, stoe in a etieval system, o tansmitte, in any fom o by any means (electonic, mechanical, photogaphic, o othewise) without the pio witten consent of Cius Logic, Inc. Items fom any Cius Logic website o isk may be pinte fo use by the use. Howeve, no pat of the pintout o electonic files may be copie, epouce, stoe in a etieval system, o tansmitte, in any fom o by any means (electonic, mechanical, photogaphic, o othewise) without the pio witten consent of Cius Logic, Inc.Futhemoe, no pat of this publication may be use as a basis fo manufactue o sale of any items without the pio witten consent of Cius Logic, Inc. The names of poucts of Cius Logic, Inc. o othe venos an supplies appeaing in this ocument may be taemaks o sevice maks of thei espective ownes which may be egistee in some juisictions. list of Cius Logic, Inc. taemaks an sevice maks can be foun at 2 DS297PP3

3 LIST OF FIGURES Figue 1. Extenal Seial Moe Input Timing Figue 2. Intenal Seial Moe Input Timing Figue 3. Intenal Seial Clock Geneation Figue 4. Typical Connection Diagam Figue 5. aserate Stopban Rejection Figue 6. aserate Tansition an Figue 7. aserate Tansition an (Detail) Figue 8. aserate Passban Ripple Figue 9. HighRate Stopban Rejection Figue 10. HighRate Tansition an Figue 11. HighRate Tansition an (Detail) Figue 12. HighRate Passban Ripple Figue 13. Output Test Loa Figue 14. Maximum Loaing Figue 15. Powe vs. Sample Rate (V = 5V) Figue 16. CS4340 Fomat 0 (I 2 S) Figue 17. CS4340 Fomat Figue 18. CS4340 Fomat Figue 19. CS4340 Fomat Figue 20. DeEmphasis Cuve Figue 21. FFT 0 input, RM, V = 3V Figue 22. FFT 60 input, RM, V = 3V Figue 23. FFT Ile Noise, RM, V = 3V Figue 24. FaetoNoise Lineaity, RM, V = 3V Figue 25. THDN vs mpl, RM, V = 3V Figue 26. THDN vs Feq, RM, V = 3V Figue 27. FFT 0 input, RM, V = 5V Figue 28. FFT 60 input, RM, V = 5V Figue 29. FFT Ile Noise, RM, V = 5V Figue 30. FaetoNoise Lineaity, RM, V = 5V Figue 31. THDN vs mpl, RM, V = 5V Figue 32. THDN vs Feq, RM, V = 5V Figue 33. FFT 0 input, HRM, V = 3V Figue 34. FFT 60 input, HRM, V = 3V Figue 35. FFT Ile Noise, HRM, V = 3V Figue 36. FaetoNoise Lineaity, HRM, V = 3V Figue 37. THDN vs mpl, HRM, V = 3V Figue 38. THDN vs Feq, HRM, V = 3V Figue 39. FFT 0 input, HRM, V = 5V Figue 40. FFT 60 input, HRM, V = 5V Figue 41. FFT Ile Noise, HRM, V = 5V Figue 42. FaetoNoise Lineaity, HRM, V = 5V Figue 43. THDN vs mpl, HRM, V = 5V Figue 44. THDN vs Feq, HRM, V = 5V DS297PP3 3

4 LIST OF TLES Table 1. Intenal Seial Clock Moe Table 2. Extenal Seial Clock Moe Table 3. Common Maste Clock Fequencies Table 4. Digital Inteface Fomat DIF1 an DIF DS297PP3

5 1. CHRCTERISTICS ND SPECIFICTIONS NLOG CHRCTERISTICS (Test conitions (unless othewise specifie): T = 25 C; Logic "1" = V = 5 V; Logic "0" = GND;FullScale Output Sine Wave, 997 ; MCLK = M; Fs fo aseate Moe = 48 k, SCLK = M, Measuement anwith 10 to 20 k, unless othewise specifie; Fs fo High Rate Moe = 96 k, SCLK = M, Measuement anwith 10 to 40 k, unless othewise specifie. Test loa R L = 10 kω, C L = 10 pf (see Figue 13) aseate Moe HighRate Moe Paamete Symbol Min Typ Max Min Typ Max Unit CS4340KS Dynamic Pefomance fo V = 5 V (Note 1) Specifie Tempeatue Range T C Dynamic Range (Note 2) 18 to 24it unweighte Weighte 16it unweighte Weighte Total Hamonic Distotion + Noise (Note 2) 18 to 24it it THD+N Intechannel Isolation (1 k) CS4340KS Dynamic Pefomance fo V = 3 V (Note 1) Specifie Tempeatue Range T C Dynamic Range (Note 2) 18 to 24it unweighte Weighte 16it unweighte Weighte Total Hamonic Distotion + Noise (Note 2) 18 to 24it it THD+N Intechannel Isolation (1 k) Notes: 1. CS4340KS pats ae teste at 25 C an Min/Max pefomance numbes ae guaantee acoss the specifie tempeatue ange, T. 2. Onehalf LS of tiangula PDF ithe is ae to ata DS297PP3 5

6 NLOG CHRCTERISTICS (Continue) aseate Moe HighRate Moe Paamete Symbol Min Typ Max Min Typ Max Unit CS4340S Dynamic Pefomance fo V = 5 V (Note 3) Specifie Tempeatue Range T C Dynamic Range (Note 2) 18 to 24it unweighte Weighte 16it unweighte Weighte Total Hamonic Distotion + Noise (Note 2) 18 to 24it it THD+N Intechannel Isolation (1 k) CS4340S Dynamic Pefomance fo V = 3 V (Note 3) Specifie Tempeatue Range T C Dynamic Range (Note 2) 18 to 24it unweighte Weighte 16it unweighte Weighte Total Hamonic Distotion + Noise (Note 2) 18 to 24it it THD+N Intechannel Isolation (1 k) Notes: 3. CS4340S pats ae teste at the extemes of the specifie tempeatue ange an Min/Max pefomance numbes ae guaantee acoss the specifie tempeatue ange, T. Typical numbes ae taken at 25 C. TD TD TD TD TD TD TD TD TD TD TD TD 6 DS297PP3

7 NLOG CHRCTERISTICS (Continue) nalog Output Paametes Symbol Min Typ Max Units Full Scale Output Voltage 0.63 V 0.7 V 0.77 V Vpp Quiescent Voltage V Q 0.5 V VDC Intechannel Gain Mismatch 0.1 Gain Dift 100 ppm/ C CLoa Resistance (Note 4) R L 3 kω Loa Capacitance (Note 4) C L 100 pf aseate Moe HighRate Moe Paamete Symbol Min Typ Max Min Typ Max Unit Combine Digital an Onchip nalog Filte Response (Note 5) Passban (Note 6) to 0.05 cone to 0.1 cone to 3 cone Notes: 4. Refe to Figue Filte esponse is guaantee by esign. 6. Response is clock epenent an will scale with Fs. Note that the esponse plots (Figues 512) have been nomalize to Fs an can be enomalize by multiplying the Xaxis scale by Fs. 7. Fo aserate Moe, the measuement banwith is Fs to 3 Fs. Fo HighRate Moe, the measuement banwith is Fs to 1.4 Fs. 8. Deemphasis is not available in HighRate Moe Fequency Response 10 to 20 k Stopan Fs Stopan ttenuation (Note 7) Goup Delay tg 9/Fs 4/Fs s Passban Goup Delay Deviation 0 40 k 0 20 k Deemphasis Eo (Relative to 1 k) Fs = 32 k Fs = 44.1 k Fs = 48 k ±0.36/Fs +.2/ /.14 /.22 ±1.39/Fs ±0.23/Fs (Note 8) Fs Fs Fs s s DS297PP3 7

8 POWER ND THERML CHRCTERISTICS CS4340KS CS4340S Paametes Symbol Min Typ Max Min Typ Max Units Powe Supplies Powe Supply Cuent nomal opeation I TD m V = 5 V poweown state I µ Powe Dissipation (Note 9) V = 5 V nomal opeation poweown TD mw mw Powe Supply Cuent nomal opeation I TD m V = 3 V poweown state I µ Powe Dissipation (Note 9) V = 3 V nomal opeation poweown TD mw mw Package Themal Resistance θ J C/Watt Powe Supply Rejection Ratio (1 k) (Note 10) (60 ) PSRR Notes: 9. Refe to Figue Vali with the ecommene capacito values on FILT+ an VQ as shown in Figue 4. Inceasing the capacitance will also incease the PSRR. DIGITL CHRCTERISTICS (fo KS pats T = 10 to 70 C; fo S pats T = 40 to 85 C; V = 2.7 V 5.5 V) Paametes Symbol Min Typ Max Units HighLevel Input Voltage V = 5 V V IH 2.0 V V = 3 V 2.0 V LowLevel Input Voltage V = 5 V V = 3 V V IL Input Leakage Cuent I in ±10 µ Input Capacitance 8 pf Maximum MUTEC Dive Cuent 3 m V V 8 DS297PP3

9 SOLUTE MXIMUM RTINGS (GND = 0 V; all voltages with espect to goun.) Paametes Symbol Min Max Units DC Powe Supply V V Input Cuent, ny Pin Except Supplies I in ±10 m Digital Input Voltage V IND 0.3 V.4 V mbient Opeating Tempeatue (powe applie) T C Stoage Tempeatue T stg C WRNING: Opeation at o beyon these limits may esult in pemanent amage to the evice. Nomal opeation is not guaantee at these extemes. RECOMMENDED OPERTING CONDITIONS (GND = 0V; all voltages with espect to goun.) Paametes Symbol Min Typ Max Units DC Powe Supply V V DS297PP3 9

10 SWITCHING CHRCTERISTICS (V = 2.7 V 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = V, CL = 20 pf; fo KS pats T = 10 to 70 C; fo S pats T = 40 to 85 C) Input Sample Rate Paametes Symbol Min Typ Max Units aserate Moe HighRate Moe Fs 2 50 MCLK Pulse With High MCLK/LRCK = ns MCLK Pulse With Low MCLK/LRCK = ns MCLK Pulse With High MCLK / LRCK = 384 o ns MCLK Pulse With Low MCLK / LRCK = 384 o ns MCLK Pulse With High MCLK / LRCK = 256 o ns MCLK Pulse With Low MCLK / LRCK = 256 o ns Extenal SCLK Moe LRCK Duty Cycle (Extenal SCLK only) % SCLK Pulse With Low t sclkl 20 ns SCLK Pulse With High t sclkh 20 ns SCLK Peio MCLK / LRCK = 512, 256 o 384 t sclkw 1 ( 128)Fs ns SCLK Peio MCLK / LRCK = 128 o 192 t sclkw 1 ( 64)Fs ns SCLK ising to LRCK ege elay t sl 20 ns SCLK ising to LRCK ege setup time t sls 20 ns SDT vali to SCLK ising setup time t sls 20 ns SCLK ising to SDT hol time t sh 20 ns Intenal SCLK Moe LRCK Duty Cycle (Intenal SCLK only) (Note 11) 50 % SCLK Peio (Note 12) t sclkw 1 ns SCLK SCLK ising to LRCK ege t sclk tsclkw µs 2 SDT vali to SCLK ising setup time t sls 1 ns ( + 512)Fs 10 SCLK ising to SDT hol time MCLK / LRCK = 512, 256 o k k t sh 1 ns ( + 512)Fs 15 SCLK ising to SDT hol time MCLK / LRCK = 384 o 192 t sh 1 ns ( + 384)Fs 15 Notes: 11. In Intenal SCLK Moe, the Duty Cycle must be 50% +/ 1/2 MCLK Peio. 12. The SCLK / LRCK atio may be eithe 32, 48, o 64. This atio epens on pat type an MCLK/LRCK atio. (See figues 1619) 10 DS297PP3

11 LRCK t sl t sls t sclkl t sclkh SCLK t sls t sh SDT Figue 1. Extenal Seial Moe Input Timing LRCK t sclk SDT t sclkw t sls tsh *INTERNL SCLK Figue 2. Intenal Seial Moe Input Timing *The SCLK pulses shown ae intenal to the CS4340. LRCK MCLK 1 N 2 N *INTERNL SCLK SDT Figue 3. Intenal Seial Clock Geneation * The SCLK pulses shown ae intenal to the CS4340. N equals MCLK ivie by SCLK DS297PP3 11

12 2. TYPICL CONNECTION DIGRM µf + 1µF +5Vto+3V V uio Data Pocesso SDT SCLK/DEM1 LRCK OUTL µf 560 Ω + 10 kω C Left uio Output R L CS4340 Extenal Clock 5 MCLK MUTEC FILT OPTIONL MUTE CIRCUIT VQ µf 1µF 0.1 µf 1µF + 7 Moe Configuation DIF1 DIF0 DEM0 RST REF_GND OUTR µf + 10 kω 560 Ω C Right uio Output R L GND 13 C= R L πF S R L 560 Figue 4. Typical Connection Diagam 12 DS297PP3

13 3. PIN DESCRIPTION Reset RST 1 16 MUTEC Mute Contol Seial Data SDT 2 15 OUTL Left nalog Output Seial Clock / Deemphasis SCLK/DEM V nalog Powe Left/Right Clock LRCK 4 13 GND nalog Goun Maste Clock MCLK 5 12 OUTR Right nalog Output Digital Inteface Fomat DIF REF_GND Refeence Goun Digital Inteface Fomat DIF VQ Quiescent Voltage Deemphasis DEM0 8 9 FILT+ Positive Voltage Refeence RST 1 Reset (Input) The evice entes a low powe moe an all intenal state machines ae eset to the efault settings when low. RST shoul be hel low uing poweup until the powe supply, maste an left/ight clocks ae stable. SDT 2 Seial uio Data (Input) Two s complement MSfist seial ata is input on this pin. The ata is clocke into SDT via the seial clock an the channel is etemine by the Left/Right clock. The equie elationship between the Left/Right clock, seial clock an seial ata is efine by the DIF10 pins. The options ae etaile in Figues SCLK 3 Seial Clock (Input) Clocks the iniviual bits of the seial ata into the SDT pin. The equie elationship between the Left/Right clock, seial clock an seial ata is efine by the DIF10 pins. The options ae etaile in Figues The CS4340 suppots both intenal an extenal seial clock geneation moes. Intenal SCLK moe is use to gain access to exta eemphasis moes. Intenal Seial Clock Moe In the Intenal Seial Clock Moe, the seial clock is intenally eive an synchonous with the maste clock an left/ight clock. The SCLK/LRCK fequency atio is eithe 32, 48, o 64 epening upon the DIF10 pins as shown in Figues Opeation in this moe is ientical to opeation with an extenal seial clock synchonize with LRCK. Extenal Seial Clock Moe The CS4340 will ente the Extenal Seial Clock Moe wheneve 16 low to high tansitions ae etecte on the SCLK pin uing any phase of the LRCK peio. The evice will evet to Intenal Seial Clock Moe if no low to high tansitions ae etecte on the SCLK pin fo 2 consecutive peios of LRCK. DS297PP3 13

14 DEM1 an DEM0 3 & 8 Deemphasis Contol (Input) Implementation of the stana 15µs/50µs igital eemphasis filte esponse, Figue 20, equies econfiguation of the igital filte to maintain the pope filte esponse fo 32, 44.1 o 48 k sample ates. When using Intenal Seial Clock Moe, as escibe above, Pin 3 is available fo eemphasis contol, DEM1, an all eemphasis filtes ae available, Table 3. When using Extenal Seial Clock Moe, as escibe above, Pin 3 is not available fo eemphasis use an only the 44.1 k eemphasis filte is available, Table 4. NOTE: Deemphasis is not available in HighRate Moe. DEM1 DEMO DESCRIPTION 0 0 Disable k k k Table 1. Intenal Seial Clock Moe DEMO DESCRIPTION 0 Disable k Table 2. Extenal Seial Clock Moe LRCK 4 Left/Right Clock (Input) The Left/Right clock etemines which channel is cuently being input on the seial auio ata input, SDT. The fequency of the Left/Right clock must be at the input sample ate. uio samples in Left/Right sample pais will be simultaneously output fom the igitaltoanalog convete wheeas Right/Left pais will exhibit a one sample peio iffeence. The equie elationship between the Left/Right clock, seial clock an seial ata is efine by the DIF10 pins. The options ae etaile in Figues MCLK 5 Maste Clock (Input) The maste clock fequency must be eithe 256x, 384x o 512x the input sample ate in ase Rate Moe (RM) an eithe 128x o 192x the input sample ate in High Rate Moe (HRM). Table 3 illustates seveal stana auio sample ates an the equie maste clock fequencies. MCLK (M) Sample HRM RM Rate (k) 128x 192x 256x 384x 512x Table 3. Common Maste Clock Fequencies 14 DS297PP3

15 DIF1 an DIF0 6 & 7 Digital Inteface Fomat (Input) The equie elationship between the Left/Right clock, seial clock an seial ata is efine by the Digital Inteface Fomat an the options ae etaile in Figues DIF1 DIF0 DESCRIPTION FORMT FIGURE 0 0 I 2 S, up to 24bit ata Left Justifie, up to 24bit ata Right Justifie, 24bit Data Right Justifie, 16bit Data 3 19 Table 4. Digital Inteface Fomat DIF1 an DIF0 FILT+ 9 Positive Voltage Refeence (Output) Positive efeence fo intenal sampling cicuits. n extenal capacito is equie fom FILT+ to analog goun, as shown in Figue 4. The ecommene value will typically povie 60 of PSRR at 1 k an 40 of PSRR at 60. FILT+ is not intene to supply extenal cuent. FILT+ has a typical souce impeance of 250 kω an any cuent awn fom this pin will alte evice pefomance. VQ 10 Quiescent Voltage (Output) Filte connection fo intenal quiescent efeence voltage, typically 50% of V. Capacitos must be connecte fom VQ to analog goun, as shown in Figue 4. VQ is not intene to supply extenal cuent. VQ has a typical souce impeence of 250 kω an any cuent awn fom this pin will alte evice pefomance. REF_GND 11 Refeence Goun (Input) Goun efeence fo the intenal sampling cicuits. Must be connecte to analog goun. OUTR an OUTL 12 & 15 nalog Outputs (Output) The full scale analog output level is specifie in the nalog Chaacteistics specifications table. GND 13 Goun (Input) Goun Refeence. V 14 nalog Powe (Input) nalog powe supply. Typically 3 to 5 VDC. MUTEC 16 Mute Contol (Output) The Mute Contol pin goes high uing poweup initialization, eset, muting, maste clock to left/ight clock fequency atio is incoect o poweown. This pin is intene to be use as a contol fo an extenal mute cicuit to pevent the clicks an pops that can occu in any single supply system. Use of Mute Contol is not manatoy but ecommene fo esigns equiing the absolute minimum in extaneous clicks an pops. DS297PP3 15

16 4. PPLICTIONS 4.1 Gouning an Powe Supply Decoupling s with any high esolution convete, the CS4340 equies caeful attention to powe supply an gouning aangements to optimize pefomance. Figue 4 shows the ecommene powe aangement with V connecte to a clean supply. Decoupling capacitos shoul be locate as close to the evice package as possible. 4.2 Ovesampling Moes The CS4340 opeates in one of two ovesampling moes. ase Rate Moe suppots input sample ates up to 50 k while High Rate Moe suppots input sample ates up to 100 k. The evices opeate in ase Rate Moe (RM) when MCLK/LRCK is 256, 384 o 512 an in High Rate Moe (HRM) when MCLK/LRCK is 128 o Recommene Poweup Sequence RST shoul be hel low until the powe supply, maste an left/ight clocks ae stable. 4.4 Popgua Tansient Contol The CS4340 uses Popgua technology to minimize the effects of output tansients uing poweup an poweown. This technique, when use with extenal DCblocking capacitos in seies with the auio outputs, minimizes the auio tansients commonly pouce by singleene singlesupply convetes. When the evice is initially poweeup, the auio outputs, OUTL an OUTR, ae clampe to GND. Following a elay of appoximately 1000 sample peios, each output begins to amp towa the quiescent voltage. ppoximately 10,000 left/ight clock cycles late, the outputs each V Q an auio output begins. This gaual voltage amping allows time fo the extenal DCblocking capacito to chage to the quiescent voltage, minimizing the poweup tansient. To pevent tansients at poweown, the evice must fist ente its poweown state by setting the RST pin low. When this occus, auio output ceases an the intenal output buffes ae isconnecte fom OUTL an OUTR. In thei place, a softstat cuent sink is substitute which allows the DCblocking capacitos to slowly ischage. Once this chage is issipate, the powe to the evice may be tune off an the system is eay fo the next poweon. To pevent an auio tansient at the next poweon, it is necessay to ensue that the DCblocking capacitos have fully ischage befoe tuning off the powe o exiting the poweown state. If not, a tansient will occu when the auio outputs ae initially clampe to GND. The time that the evice must emain in the poweown state is elate to the value of the DCblocking capacitance. Fo example, with a 3.3 µf capacito, the minimum poweown time will be appoximately 0.4 secons. Use of the Mute Contol function is ecommene fo esigns equiing the absolute minimum in extaneous clicks an pops. lso, use of the Mute Contol function can enable the system esigne to achieve ile channel noise/signaltonoise atios which ae only limite by the extenal mute cicuit. See the CD4340/41 ata sheet fo a suggeste mute cicuit. 16 DS297PP3

17 5. INTERPOLTION FILTER RESPONSE PLOTS Figue 5. aserate Stopban Rejection Figue 6. aserate Tansition an Figue 7. aserate Tansition an (Detail) Figue 8. aserate Passban Ripple Figue 9. HighRate Stopban Rejection Figue 10. HighRate Tansition an DS297PP3 17

18 Figue 11. HighRate Tansition an (Detail) Figue 12. HighRate Passban Ripple OUTx 3.3 µf + V out R L C L GND Figue 13. Output Test Loa Capacitive Loa C L (pf) Safe Opeating Region Powe (mw) RM HRM Resistive Loa R L (kω ) Sample Rate (k) Figue 14. Maximum Loaing Figue 15. Powe vs. Sample Rate (V = 5V) 18 DS297PP3

19 6. DIGITL INTERFCE FORMTS LRCK Left Channel Right Channel SCLK SDT MS LS MS LS Intenal SCLK Moe I 2 S, 16it ata an INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 o 128 I 2 S, up to 24it ata an INT SCLK = 48 Fs if MCLK/LRCK = 384 o 192 Extenal SCLK Moe I 2 S, up to 24it Data Data Vali on Rising Ege of SCLK Figue 16. CS4340 Fomat 0 (I 2 S) LRCK Left Channel Right Channel SCLK SDT MS LS MS LS Intenal SCLK Moe Left Justifie, up to 24it Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 o 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 o 192 Extenal SCLK Moe Left Justifie, up to 24it Data Data Vali on Rising Ege of SCLK Figue 17. CS4340 Fomat 1 DS297PP3 19

20 LRCK Left Channel Right Channel SCLK SDT clocks Intenal SCLK Moe Right Justifie, 24it Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 o 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 o 192 Extenal SCLK Moe Right Justifie, 24it Data Data Vali on Rising Ege of SCLK SCLK Must Have at Least 48 Cycles pe LRCK Peio Figue 18. CS4340 Fomat 2 LRCK Left Channel Right Channel SCLK SDT clocks Intenal SCLK Moe Right Justifie, 16it Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 o 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 o 192 Extenal SCLK Moe Right Justifie, 16it Data Data Vali on Rising Ege of SCLK SCLK Must Have at Least 32 Cycles pe LRCK Peio Figue 19. CS4340 Fomat 3 20 DS297PP3

21 Gain 0 T1=50 µs 10 T2 = 15 µs F1 F k k Fequency Figue 20. DeEmphasis Cuve 7. NLOG PERFORMNCE PLOTS The following CS4340 nalog Pefomance Plots wee taken fom the CD4340 evaluation boa using the uio Pecision Dual Domain System Two Cascae. ll ase Rate Moe (RM) plots wee taken at a 48 k sample ate with a 20 to 20 k banwith using a 20 k lowpass bickwall filte in the DSP nalyze. ll High Rate Moe (HRM) plots wee taken at a 96 k sample ate with a 20 to 40 k banwith using a 40 k bickwall filte in the DSP nalyze. DS297PP3 21

22 k 4k 6k 8k 10k 12k 14k 16k 18k Figue 21. FFT 0 input, RM, V = 3V 20k 140 2k 4k 6k 8k 10k 12k 14k 16k 18k Figue 22. FFT 60 input, RM, V = 3V 20k k 4k 6k 8k 10k 12k 14k 16k 18k Figue 23. FFT Ile Noise, RM, V = 3V 20k FS Figue 24. FaetoNoise Lineaity, RM, V = 3V FS k 2k 5k 10k 20k Figue 25. THDN vs mpl, RM, V = 3V Figue 26. THDN vs Feq, RM, V = 3V 22 DS297PP3

23 k 4k 6k 8k 10k 12k 14k 16k 18k Figue 27. FFT 0 input, RM, V = 5V 20k 140 2k 4k 6k 8k 10k 12k 14k 16k 18k Figue 28. FFT 60 input, RM, V = 5V 20k k 4k 6k 8k 10k 12k 14k 16k 18k 20k FS Figue 29. FFT Ile Noise, RM, V = 5V Figue 30. FaetoNoise Lineaity, RM, V = 5V FS k 2k 5k 10k 20k Figue 31. THDN vs mpl, RM, V = 5V Figue 32. THDN vs Feq, RM, V = 5V DS297PP3 23

24 k 10k 15k 20k 25k 30k 35k Figue 33. FFT 0 input, HRM, V = 3V 40k 140 5k 10k 15k 20k 25k 30k 35k Figue 34. FFT 60 input, HRM, V = 3V 40k k 10k 15k 20k 25k 30k 35k 40k FS Figue 35. FFT Ile Noise, HRM, V = 3V Figue 36. FaetoNoise Lineaity, HRM, V = 3V FS k 2k 5k 10k 20k 40k Figue 37. THDN vs mpl, HRM, V = 3V Figue 38. THDN vs Feq, HRM, V = 3V 24 DS297PP3

25 k 10k 15k 20k 25k 30k 35k Figue 39. FFT 0 input, HRM, V = 5V 40k 140 5k 10k 15k 20k 25k 30k 35k Figue 40. FFT 60 input, HRM, V = 5V 40k k 10k 15k 20k 25k 30k 35k 40k FS Figue 41. FFT Ile Noise, HRM, V = 5V Figue 42. FaetoNoise Lineaity, HRM, V = 5V FS k 2k 5k 10k 20k 40k Figue 43. THDN vs mpl, HRM, V = 5V Figue 44. THDN vs Feq, HRM, V = 5V DS297PP3 25

26 8. PRMETER DEFINITIONS Total Hamonic Distotion + Noise (THD+N) measue of cosstalk between the left an ight channels. Measue fo each channel at the convete s output with all zeos to the input une test an a fullscale signal applie to the othe channel. Units in ecibels. Dynamic Range The atio of the full scale ms value of the signal to the ms sum of all othe spectal components ove the specifie banwith. Dynamic ange is a signaltonoise measuement ove the specifie banwith mae with a 60 FS signal. 60 is then ae to the esulting measuement to efe the measuement to full scale. This technique ensues that the istotion components ae below the noise level an o not effect the measuement. This measuement technique has been accepte by the uio Engineeing Society, ES171991, an the Electonic Inusties ssociation of Japan, EIJ CP307. Intechannel Isolation measue of cosstalk between the left an ight channels. Measue fo each channel at the convete s output with all zeos to the input une test an a fullscale signal applie to the othe channel. Units in ecibels. Intechannel Gain Mismatch The gain iffeence between left an ight channels. Units in ecibels. Gain Eo The eviation fom the nominal full scale analog output fo a full scale igital input. Gain Dift The change in gain value with tempeatue. Units in ppm/ C. 9. REFERENCES 1) "How to chieve Optimum Pefomance fom DeltaSigma /D & D/ Convetes" by Steven Hais. Pape pesente at the 93 Convention of the uio Engineeing Society, Octobe ) CD4340 Evaluation oa Datasheet 26 DS297PP3

27 10. PCKGE DIMENSIONS 16L SOIC (150 MIL ODY) PCKGE DRWING E H 1 b D c SETING PLNE e 1 L INCHES MILLIMETERS DIM MIN NOM MX MIN NOM MX b C D E e H L JEDEC #: MS012 Contoling Dimension is Millimetes DS297PP3 27

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