STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7
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1 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 N-channel 100 V, Ω typ., 80 A, STripFET VII DeepGATE Power MOSFET in D 2 PAK, DPAK, TO-220FP and TO-220 Datasheet - production data TAB TAB Features 1 3 D 2 PAK TAB DPAK 1 3 Order codes V DS R DS(on) max I D P TOT STB100N10F7 80 A 120 W STD100N10F7 80 A 120W 100 V Ω STF100N10F7 45 A 30 W STP100N10F7 80A 150 W TO-220FP TO-220 Figure 1. Internal schematic diagram Ultra low on-resistance 100% avalanche tested Applications Switching applications Description These devices utilize the 7 th generation of design rules of ST s proprietary STripFET technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R DS(on) in all packages. Table 1. Device summary Order codes Marking Packages Packaging STB100N10F7 D 2 PAK Tape and reel STD100N10F7 DPAK Tape and reel 100N10F7 STF100N10F7 TO-220FP Tube STP100N10F7 TO-220 Tube November 2013 DocID Rev 4 1/23 This is information on a product in full production. 23
2 Contents STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package mechanical data Packaging mechanical data Revision history /23 DocID Rev 4
3 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Value Symbol Parameter DPAK TO-220FP TO-220 D 2 PAK Unit V DS Drain-source voltage 100 V V GS Gate-source voltage ± 20 V I D Drain current (continuous) at T C = 25 C (1) 80 A I D Drain current (continuous) at T C = 100 C (1) 70 A (2) I DM Drain current (pulsed) A P (1) TOT Total dissipation at T C = 25 C W T J Operating junction temperature C -55 to 175 T stg Storage temperature C 1. This value is limited by package.. 2. Pulse width limited by safe operating area. Table 3. Thermal resistance Symbol Parameter Value D 2 PAK DPAK TO-220FP TO-220 Unit R thj-case Thermal resistance junction-case C/W R thj-amb R thj-pcb (1) Thermal resistance junctionambient C/W Thermal resistance junction-pcb C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Table 4. Avalanche characteristics Symbol Parameter Value Unit E AS Single pulse avalanche energy (T J = 25 C, L = 3.5 mh, I AS = 15 A, V DD = 50 V, V GS = 10 V) 400 mj DocID Rev 4 3/23
4 Electrical characteristics STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 2 Electrical characteristics (T CASE =25 C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-source breakdown voltage (V GS = 0) Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) I D = 250 μa V V DS = 100 V V DS = 100 V; T C =125 C μa μa V GS = 20 V 100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 μa V R DS(on) Static drain-source onresistance For D 2 PAK, DPAK and TO-220 V GS = 10 V, I D = 40 A For TO-220-FP V GS = 10 V, I D = 22.5 A Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS =50 V, f=1 MHz, pf C rss V GS =0 Reverse transfer capacitance pf Q g Total gate charge V DD =50 V, I D = 80 A nc Q gs Gate-source charge V GS =10 V nc Q gd Gate-drain charge Figure nc Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time ns t V DD =50 V, I D = 40 A, r Rise time ns R G =4.7 Ω, V GS = 10 V t d(off) Turn-off delay time Figure ns t f Fall time ns 4/23 DocID Rev 4
5 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min Typ. Max Unit I SD Source-drain current - 80 A I (1) SDM Source-drain current (pulsed) A V (2) SD Forward on voltage I SD = 80 A, V GS =0-1.2 V t rr Reverse recovery time I SD = 80 A, - 77 ns Q rr Reverse recovery charge di/dt = 100 A/μs, nc I RRM Reverse recovery current V DD =80 V, T j =150 C - 4 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 μs, duty cycle 1.5% DocID Rev 4 5/23
6 Electrical characteristics STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for DPAK Figure 3. Thermal impedance for DPAK ID (A) Operation in this area is Limited by max RDS(on) AM15754v1 100µs 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP ID (A) Operation in this area is Limited by max RDS(on) AM15755v1 100µs 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Figure 6. Safe operating area for D 2 PAK and TO-220 Figure 7. Thermal impedance for D 2 PAK and TO-220 ID (A) Operation in this area is Limited by max RDS(on) AM15756v1 100µs K 10-1 δ= AM15761v1 1 Tj=175 C Tc=25 C Single pulse VDS(V) 1ms 10ms Single pulse tp(s) 6/23 DocID Rev 4
7 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Electrical characteristics Figure 8. Output characteristics Figure 9. Transfer characteristics ID (A) 300 VGS=10V 9V AM15757v1 ID (A) 300 VDS=5V AM15745v V V V 50 5V VDS(V) VGS(V) Figure 10. Normalized V (BR)DSS vs temperature Figure 11. Static drain-source on-resistance V(BR)DSS (norm) ID=1mA AM15747v1 RDS(on) (mω) 14.0 VGS=10V AM15748v TJ( C) ID(A) Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations VGS (V) VDD=50V ID=80A AM15758v1 C (pf) AM15759v1 Ciss Qg(nC) Coss Crss VDS(V) DocID Rev 4 7/23
8 Electrical characteristics STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Figure 14. Normalized gate threshold voltage vs temperature VGS(th) (norm) ID= 250 µa TJ( C) AM15746v1 Figure 15. Normalized on-resistance vs temperature RDS(on) (norm) ID=40A TJ( C) AM15760v1 Figure 16. Source-drain diode forward characteristics VSD (V) 1.1 TJ=-55 C AM15749v TJ=25 C TJ=150 C ISD(A) 8/23 DocID Rev 4
9 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Test circuits 3 Test circuits Figure 17. Switching times test circuit for resistive load Figure 18. Gate charge test circuit VDD VGS VD RG RL D.U.T μf 3.3 μf VDD Vi=20V=VGMAX 2200 μf 12V IG=CONST 2.7kΩ 47kΩ 100Ω 100nF D.U.T. 1kΩ VG PW 47kΩ PW 1kΩ AM01468v1 AM01469v1 Figure 19. Test circuit for inductive load switching and diode recovery times Figure 20. Unclamped inductive load test circuit 25 Ω G A D D.U.T. S B A FAST DIODE B A B D L=100μH μf μf VDD VD ID L 2200 μf 3.3 μf VDD G RG S Vi D.U.T. AM01470v1 Pw AM01471v1 Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf ID IDM 0 90% 10% VDS 10% 90% VDD VDD VGS 90% AM01472v1 0 10% AM01473v1 DocID Rev 4 9/23
10 Package mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. Figure 23. D²PAK (TO-263) drawing _T 10/23 DocID Rev 4
11 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Package mechanical data Figure 24. D²PAK footprint (a) Footprint a. All dimension are in millimeters DocID Rev 4 11/23
12 Package mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Table 9. DPAK (TO-252) mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e 2.28 e H L (L1) 2.80 L L R 0.20 V /23 DocID Rev 4
13 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Package mechanical data Figure 25. DPAK (TO-252) drawing _K DocID Rev 4 13/23
14 Package mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Figure 26. DPAK footprint (b) Footprint_REV_K b. All dimensions are in millimeters 14/23 DocID Rev 4
15 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Package mechanical data Table 10. TO-220FP mechanical data Dim. mm Min. Typ. Max. A B D E F F F G G H L2 16 L L L L L Dia DocID Rev 4 15/23
16 Package mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Figure 27. TO-220FP drawing _Rev_K_B 16/23 DocID Rev 4
17 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Package mechanical data Table 11. TO-220 type A mechanical data Dim. mm Min. Typ. Max. A b b c D D E e e F H J L L L L P Q DocID Rev 4 17/23
18 Package mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Figure 28. TO-220 type A drawing _typeA_Rev_S 18/23 DocID Rev 4
19 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Packaging mechanical data 5 Packaging mechanical data Table 12. D²PAK (TO-263) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 D C D D 20.2 E G F N 100 K T 30.4 P P Base qty 1000 P Bulk qty 1000 R 50 T W Table 13. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty DocID Rev 4 19/23
20 Packaging mechanical data STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Table 13. DPAK (TO-252) tape and reel mechanical data (continued) Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. P R 40 T W Figure 29. Tape 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 20/23 DocID Rev 4
21 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Packaging mechanical data REEL DIMENSIONS Figure 30. Reel 40mm min. T Access hole At slot location D B C A N Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 DocID Rev 4 21/23
22 Revision history STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 6 Revision history Table 14. Document revision history Date Revision Changes 05-Oct First release. 07-Feb Apr Nov Inserted device in TO-220FP. Updated title and features on the cover page, Table 1: Device summary, Table 2: Absolute maximum ratings, Table 3: Thermal resistance and Table 5: On/off states accordingly. Updated Table 6: Dynamic, Table 7: Switching times, Table 8: Source drain diode and Section 4: Package mechanical data. Added Section 5: Packaging mechanical data. Modified: the entire typical values in Table 6, t f typical value intable 7, V SD and typical values for t rr, q rr, I RRM Inserted:Table 4: Avalanche characteristics and Section 2.1: Electrical characteristics (curves) Minor text changes Inserted device in D 2 PAK. Updated title and features on the cover page, Table 1: Device summary, Table 2: Absolute maximum ratings, Table 3: Thermal resistance and Table 5: On/off states accordingly. Updated Table 6: Dynamic, Section 4: Package mechanical data and Section 5: Packaging mechanical data. 22/23 DocID Rev 4
23 STB100N10F7, STD100N10F7, STF100N10F7, STP100N10F7 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America DocID Rev 4 23/23
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N-channel 650 V, 0.98 Ω typ., 5 A MDmesh M2 Power MOSFET in a DPAK package Features Datasheet - production data TAB Order code V DS R DS(on) max STD7N65M2 650 V 1.15 Ω 5 A I D DPAK 1 3 Extremely low gate
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STB24N60DM2, STP24N60DM2, STW24N60DM2 N-channel 600 V, 0.175 Ω typ., 18 A FDmesh II Plus low Q g Power MOSFETs in D 2 PAK, TO-220 and TO-247 packages Datasheet production data TAB TAB Features D 2 PAK
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