4.1 THE 45nm TECHNOLOGY

Transcription

1 CHAPTER 4 DEEP SUBMICRON & THE NANOMETER MOS Considerations and characteristics of the deep sub-micron and nanometer MOS, especially the 45nm MOS, their characteristic degradation are discussed. 63

2 MOSFETs are already scaled to nanometer size. Proposals have already come for MOSFETs in 6nm, but 45nm Technology is adopted here for the present work. Reasons include the commercialization. Furthermore, the technology is expected to be a turning point for a number of challenges faced by the conventional CMOS Technology. Below is given a discussion on the characteristics of the 45nm MOSFETs along with some of their important sources of degradation. This chapter also includes the behaviour of HSPICE with the parasites of the CMOS circuits. 4.1 THE 45nm TECHNOLOGY It is the latest technology. This technology is important in itself as it appears to be a turning point for a number of effects which were either absent or were ignorable in earlier technology nodes. CPU manufacturers, being the leading application group, have already started working on the 45nm technology [50,52,56]. TABLE4.1: 45nm technology key points [46, 47] Parameter Packing Density Switching Power Switching Speed S D Leakage Gate Leakage Target Frequency Bulk Defects Quantitative Figure Doubles 30% 20% 05% 10% GHz Reducing This technology is expected to offer an improved performance on per Watt power dissipation basis. Intel came with it s two 45nm based Penryn Processors the Dual Core with 410 million transistors on chip and Quad Core with 820 million transistors on chip in 64

3 2007. The key points of the technology are given in table below. Arrows show the trend, upward for increasing and downward for decreasing. Also these figures are obtained for transistors with high k metal gate technology [51]. Intel and other leading microprocessors have adopted silicon bulk process for the 45nm and the other upcoming technologies of future because the rival SOI shows inconsistency in V TH etc. 4.2 SOME OF THE DEEP SUBMICRON CHALLENGES The advancing technology as usual, invokes a number of problems and puts challenges to the design. A hard constraint to design a product in target time so that it gets sufficient time in the market before it gets obsolete [130]. The parameter variability increases with technology. This enhances the probability of mismatch among the designs, the devices used in a design etc. and hence may affect the yield [133]. The degradation mechanisms like NBTI, hot carrier injection etc increase with each advancement of the technology. This disturbance is of permanent nature [89]. The sources that cause disturbance in the functioning of the systems may include the Electromagnetic Interference, electromagnetic coupling, substrate noise coupling. These effects are of temporary nature and increase reliability concerns [108]. 65

4 4.2.1 CIRCUIT NON-IDEALITIES Analog circuit non-idealities originate from the random and systematic errors. These errors represent time-independent reliability problems. Random errors, usually denoted as variability, are the result of the stochastic nature of many physical processes that take place during the fabrication. In analog circuits device mismatch between identical devices is a key limitation to the accuracy of the circuit. The V TH mismatch, VT, among identical transistors of WL active area can be given by [49]: A 2 2 VTH 2 2 σ ( VTH ) = + S V D (4.1) TH WL where and are process-dependent constants and D is the distance A V TH S V TH between the devices. Unfortunately, as can be seen from Eq.4.1, this mismatch is inversely proportional to the area of the devices and therefore can only be improved by making the devices larger, that is, more chip area and more power for the same speed [53,54]. Mismatch is, in fact, a big problem for the 45nm and more advanced technologies. These may include the quantum mismatch, which is usually not a concern in analog design because here, the non minimum sized devices are used. Similarly, the stress induced mismatch, antenna effect mismatch, high frequency mismatch are some important yet subtle effects that might play significant role in certain specific applications. However, they all are process related and therefore can be relieved by choosing an appropriately engineered process. 66

5 4.2.2 TIME-DEPENDENT DEGRADATION The time-dependent degradation occurs due to ageing of the transistors and results in the circuit performance changing over time. a. Time-Dependent Degradation Effects Such effects cause a change in VTH, β and of a transistor and cause a circuit to become non functional over time [55]. This degradation depends upon the stress applied to the device. Figure below compares the performance of a device over time for such a degradation. r o FIGURE 4.1: Time-dependent variation of the characteristics of a transistor due to Hot-Carrier and NBTI degradation [49] b. Large Field Across Gate Oxide In deep submicron, a large field across a thin oxide causes a trap generation randomly distributed in the oxide layer which leads to the stress induced oxide or gate leakage and leads to degrading the MOSFET performance. 67

6 c. Excessive Large Field Across Oxide A large field across the gate oxide causes oxide tarp density becomes so large that the oxide breakdown occurs and the oxide loses it s insulation properties. Breakdown is a local phenomenon, in which an extra current flows through a small region of the gate oxide [56,57]. d. Hot Carrier Injection Hot carriers impinge into the oxide and are trapped by it. Presence of these carriers in the gate oxide degrades the MOS threshold voltage. It is a time dependent process and causes a shift in the V TH, mobility degradation of carriers and a change of output resistance [58,59]. A large electric field near the drain end of a saturated transistor causes hot carriers. These carriers introduce both oxide and interface traps near the drain and a substrate current exists. This effect is more pronounced in nmos [60]. e. Negative Bias Temperature Instability (NBTI) NBTI results into a threshold voltage shift after a negative bias has been applied to a PMOS gate at elevated temperature [61]. It has an increasingly adverse impact on deep submicron and nanometer CMOS technologies. Degradation of channel carrier mobility is also observed. 68

7 4.2.3 TEMPORARY DEGRADATION CAUSES Some disturbance sources such as electromagnetic interference (EMI) or substrate noise coupling may turn functional analog circuits into nonfunctional circuits, but normally these sources do not cause a permanent change in performance. 4.3 DEEP SUBMICRON MOSFET MODEL According to channel length, MOSFET s my be defined as Long Channel ( L 1µ m), Short Channel ( L < 1µ m). Short Channel MOSFETS may further be subdivided as Deep Submicron ( L << 1µ m) like 0.3µ and Nanometer MOSFETS of still smaller channel lengths. The drain is characterized with the saturation values of D S voltage and the channel current as shown in figure below. I Dsat V DSsa FIGURE 4.2: I V Characteristics of the MOSFET under deep submicron. V = V V ( L m). V plays important role in the modeling. For example, Dsat GS TH µ Dsat λ is defined as the slope of the near horizontal part of the drain characteristic of the MOSFET after the onset of saturation. Similarly the transition frequency can be defined as 69

8 f T g 3 V m µ n DS _ sat = (4.2) 2 2πC 4π L gs To get high speed, we need to use minimum L and large V. However: Lowering the channel length L results: 1. decreases r o 2. lowers the gain, and, DS _ sat 3. causes a decrease in µ because of the increase in field, 4. increases the channel length modulation, tending the current to become non quadratic. Increasing the D S saturation voltage V reduces the output swing. Therefore, DS _ sat as a rule for analog design, we can safely compromise 1. 2 X < L < 5X of the minimum of the technology 2. V DS _ sat = 5% of VDD In analog design, a figure of merit, important to consider is the intrinsic gain transition frequency product, µ n GFT = gmro ftα (4.3) L where the RHS is constant, asserting that the intrinsic gain and the transition frequency go reverse of one another and can never be increased simultaneously. Again ftα I D (4.4) g m 1 roα (4.5) I D 70

9 This is an important hint to analog design. Furthermore, the devices behave differently depending upon their L W ratios. Thus if W and device may be considered a L are comparable, the Long Channel Device ( short channel device if ( W L W >> L, say 5/1 in 45nm technology), say 25/1 in 45nm tech.). Both these devices need be modeled separately because a long channel still tends to follow quadratic nature whereas the short channel device tends to deviate away from the standard quadratic relationship between it s voltage and current. 4.4 DESIGN PARAMETER EXTRACTION MOSFET Characteristics in deep submicron regime are quite complicated. This perhaps is due to the proximity influence due to the shrinking geometries of MOSFETS. Therefore design for an analog performance is a tedious job. Design parameters are statistically obtained from a real time process. However for practically obtained MOSFET model cards, analytical methods along with the simulator can also be helpful in extracting the desired set of parameters. In such early stage when the design parameters are not readily available, parameter extraction is highly desirable. Here this task is done using the 45nm CMOS model cards, and adopting analytical methods for design parameter extraction as discussed in [99] and the simulation results for the 45nm model cards. The 45nm CMOS technology is in itself complicated. It is easy to observe that the minimum sized MOSFETS show very high channel length modulation. However this effect can be reduced if wider dimensions than minimum are used. For example, the 71

10 MOS of 1µ/1µ size is almost ideal compared to the sizes 45nm/45nm and 90nm/45nm. FIGURE 4.3: I V Characteristics of a 45nm MOSFET wrt W and L Clearly, geometry wider than the bare minimum, shows better results. In analog applications therefore it is necessary to use wider dimension to keep the things under control. 4.5 SYNOPSYS HSPICE Synopsys provides a series of standard MOSFET models. Each model is like a template that defines various versions of the MOSFET that are compatible to HSPICE-format net list and match the industry standard. The models can be instanced through the net list to define the MOSFET and can be helpful to Create the net list quickly and efficiently, Ease the process of circuit simulation design and debugging, 72

11 Reduce the time required to Create the net list and Reduce the risk of Errors. A MOSFET is usually defined by a recent and widely used MOSFET model, technology dependant model element parameters, and a submodel selected by the CAPOP model parameters. The CAPOP model parameter specifies the model for the MOSFET gate capacitances and the bulk parasitic diodes. In order to accommodate the advancing technology and a real type device, Synopsys has a wide set of device models, BSIM models (LEVEL 13, 28, 39, 47, 49, 53, 54, 57, 59, and 60), which can be selected through the corresponding LEVEL card. The advantage of using BSIM models is that they consider the variation of model parameters as a function of sensitivity of the geometric parameters, and reference a MOS charge conservation model for precise modeling of the MOS capacitances. In this work, the model used is the most advanced and highly accurate model called BSIM4 Model developed by the University of California, Berkeley, and can be referred through the level card as LEVEL = 54 in HSPICE. Real picture of the MOSFET in use is defined by a set of parameters that are generated at the industry standard. Therefore most advanced MOS model (BSIM4) and the industry standard model parameters help to simulate the highly precise and most reliable performance. Among various versions of SPICE Programs, HSPICE is considered as the Gold standard and is thus used in real designs [115] GATE CAPACITANCE MODEL Time dependant simulations need advanced capacitance models to be adopted to corroborate accurate simulation results. Various capacitance model cards are used 73

12 to call a specific capacitance model through a model number. Usually, each card has recommendations, and therefore assigned with specific simulation level card set as default. However, user is free to choose any for his program. For BSIM4 modeling, the highly advanced capacitance model is recommended and is set as default under the CAPMOD = 2 card under simulation LEVEL = 54. BSIM4 considers the effects such as body bias, short and narrow channel and DIBL are explicitly considered in CAPMOD = 2. In deep submicron devices, accurate capacitance modeling is done by considering the charge thickness to avoid any untoward discrepancy in uniformity of the charge layer at V and V [116]. fb TH MODELLING V th MOS conductance is extremely sensitive to the changes in devices, V TH. In deep submicron shows dependence on doping concentration, concentration profile in the channel both in the lateral as well as vertical directions, halo doping, short channel effects, DIBL, narrow channel and temperature variation. BSIM4 models deal with all such effects and HSPICE prepares a consolidated result including these effects. V TH SUBTHRESHOLD MODEL Modeling of the MOSFET under subthreshold region is important for the modern Low Power VLSI. BSIM4 considers unified charge density model for subthreshold region. However, the gate swing is considered dependant on the channel length and the interface state density. 74

13 4.5.4 DIFFUSION DIODE MODEL In a MOSFET the bulk to drain and the bulk to source diodes determine the D/S leakage. The ACM (Area Calculation Method) model parameter controls the geometry of the D/S diffusions, and selects the modeling of these diodes. The diode model includes diffusion resistance ( R ), capacitance ( ), and DC I sub currents to the substrate ( ). diff C diff GATE TUNNELING It is gate current leakage that is gaining prominence with reckless device scaling. Gate current, though zero in conventional devices, exhibits an upward trend with each upcoming technology. HSPICE includes the different effects which lead to the leakages in a MOSFET. A list of various effects and their current components called forth by the card number as given in the Table 4.3 [116]. TABLE 4.3: Various Leakage and other similar Currents in a MOSFET Leakage Card Symbol Description LX38 igso Gate-to-Source Current LX39 igdo Gate-to-Drain Current LX66 igbo Gate-to-Substrate Current (Igb = Igbacc + Igbinv) LX67 igcso Source Partition of Igc LX68 igcdo Drain Partition of Igc LX69 iimi Impact ionization current LX70 igidlo Gate-induced drain leakage current LX71 igdt Gate Dielectric Tunneling Current (Ig = Igs + Igd + Igcs + Igcd + Igb) 75

14 Igcd + Igb) LX72 Igc Gate-to-Channel Current at zero Vds LX73 igbacc Determined by ECB (Electron tunneling from the Conduction Band); significant in the accumulation LX74 igbinv Determined by EVB (Electron tunneling from the Valence Band); significant in the inversion LX110 IGISLO Gate-induced source leakage current 4.6 MOS PARASITES - CAPACITANCE A MOS can have resistance, capacitance and inductance acting as parasites. These parasites come into picture due to the materials involved through which currents flow (Resistance R), different layers maintained potential differences, (Capacitance C) and conducting wires and leads, (Inductance L) etc. Resistance and inductance are all affecting the circuit performances, but capacitance is a major parasite that normally is found responsible for determining the system speed directly. A MOS Model card if generated on practical basis will surely handle these parasites PARASITIC CAPACITANCES AND THE BEHAVIOUR OF HSPICE HSPICE pays special attention to the parasitic capacitance. Below is detailed representation of the model cards used by the simulator to exhaustively deal with the various possibilities of parasitic capacitances in integrated circuits associated with MOSFETs [116]. 76

15 TABLE 4.4: Parasitic capacitance details showing the depth of HSPICE concern. Capacitance Card Symbol Description LX36 COVLGS Gat e-source overlap and fringing capacitances LV38 COVLGB Gate-bulk overlap capacitances LX4 CDO Channel current (IDS) LX5 CBSO DC source-bulk diode current (CBSO) LX6 CBDO DC drain-bulk diode current (CBDO) LX12 LX13 LX14 LX15 QB CQB QG CQG Total bulk (body) charge (QB) Meyer and Charge Conservation Bulk (body) charge current (CQB) Meyer and Charge Conservation Total Gate charge (QG) Meyer and Charge Conservation Gate charge current (CQG) Meyer and Charge Conservation LX16 QD Channel charge (QD) Meyer and Charge Conservation LX17 CQD Channel charge current (CQD) Meyer and Charge Conservation LX18 CGGBO Intrinsic gate capacitance LX19 CGDBO Intrinsic gate-to-drain capacitance LX20 CGSBO Intrinsic gate-to-source capacitance LX21 CBGBO Intrinsic bulk-to-gate capacitance LX22 CBDBO Intrinsic bulk-to-drain capacitance LX23 CBSBO Intrinsic bulk-to-source capacitance LX24 QBD Drain-bulk charge (QBD) LX26 QBS Source-bulk charge (QBS) LX28 CAP_BS Bias dependent bulk-source capacitance LX29 CAP_BD Bias dependent bulk-drain capacitance LX31 CQS Channel-charge current (CQS). LX32 CDGBO Intrinsic drain-to-gate capacitance 77

16 LX33 CDDBO Intrinsic drain capacitance LX34 CDSBO CDSBO = -dqd/dvs, Drain-to-source capacitance - Meyer and Charge Conservation LX80 cap_bsz Zero voltage bias bulk-source capacitance LX81 cap_bdz Zero voltage bias bulk-drain capacitance LX82 LX83 LX84 LX85 LX86 LX87 LX88 LX89 LX90 LX91 CGGBM CGDBM CGSBM CDDBM CDSBM CDGBM CBGBM CBDBM CBSBM CAPFG Total gate capacitance (including intrinsic), and all overlap and fringing components Total gate-to-drain capacitance (including intrinsic), and overlap and fringing components Total gate-to-source capacitance (including intrinsic), and overlap and fringing components Total drain capacitance (including intrinsic), overlap and fringing components, and junction capacitance Total drain-to-source capacitance Total drain-to-gate capacitance (including intrinsic), and overlap and fringing components Total bulk-to-gate (floating body-to-gate) capacitance, including intrinsic and overlap components Total bulk-to-drain capacitance (including intrinsic), and junction capacitance Total bulk-to-source capacitance (including intrinsic), and junction capacitance Fringing capacitance PARASITIC CAPACITANCES RELATED TO CIRCUIT NODES The capacitances that usually are associated with the circuit nodes are represented as follows [116]. TABLE 4.5: Capacitances referred Capacitance cdtot cgtot cstot Value cgd+cdb cgs+cgd+cgb cgs+csb 78

17 cbtot cgs cgd cgb+csb+cdb Cgs cgd Thus the accurate vales of the parasitic capacitances are incorporated in the simulation process and the results are generated using these capacitances. Technology plays important role in defining the characteristics of the system. Advancement of the SC Technology means scaling down the MOS. Scaling has become a necessity to accommodate the rising pressure of the data processing demands. But reckless scaling has pushed the modern day MOS into an arena of problems which are getting more serious than ever with every new step of scaling. In order to apply proper remedial treatment to the problem of power, it is necessary to look into the aspects at various levels, from materials to device to processing to packaging etc. The depth of insight also depends upon the simulation program used. Different parasites determine the performance of the final systems. 79