A methodology for SoC top-level validation

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1 A mehodology for SoC op-level validaion Elecronic Design Process 02 Sylvan Dissoubray Monerey 1 Corporae Profile Founded in Nov M¼UDLVHGLQ and employees in 5 counries 30 consulans 30+ large corporae cusomers 200+ seas deployed Major shareholders Managemen & saff GALILEO Parners CDC Innovaion INNOTECH Advanced Capial Europe Inel Capial THALES Corporae Venures INRIA-Transfer 2 1

2 Sysem Archiecure Specificaions Wireless core plaforms Consumer elecronics core plaforms Microprocessor chipses Top-level Validaion of SoCs Wireless plaforms Se op boxes DVD chipses MPEG decoders Eserel Sudio Applicaions Telecom & Securiy Proocol Developmen (SW / UML) UMTS: RRC, RLC layers Blueooh Secured miliary communicaion Smar-card securiy HiperLAN2 3 SoC op-level validaion challenges SoC s maximized reuse bu design coss did no drop down Because cos moved o SoC s funcional verificaion consumes up o 70% overall design cycle budge (ITRS) Why is i so difficul o verify SoC s? Muli-core, muli-service, muli-raffic SoC s => exreme concurrency More reuse of blocks and IPs => less and less knowledge of componens inernal behavior The SoC inegraor dilemma Funcional coverage requires a lo of es cases, i is difficul o reach corner cases Time wriing es cases is ime consuming, running inegraion level ess is slow 4 2

3 SoC Top Level Validaion: objecives Generae auomaically a Tes Suie o validae IP ineroperabiliy and concurrency High level ransacional approach Obain he bes coverage in he mos effecive manner 5 SoC op-level validaion mehod SoC Archiecure Validaion Plaform RISC DSP BUS Peripheral Glue logic DMA 1 Wrie Transacional Models (TM) 4 Run validaion esbench Peripheral Glue logic DMA 3 Auomaic Generaion Compilaion 6 SoC Top Level Validaion Model Peripheral Glue logic DMA 2 Inegrae all TM in parallel C C Top Top Level Level Validaion Validaion Tesbench Tesbench C C Transacors Transacors Library Library 3

Example: op-level validaion of a MP3 SoC The MP3 sysem The DMA block can ransfer The WRITER can wrie ino RAM The DECODER can: Copy he sream Decode he sream ino anoher forma (wav, pcm, ec.

4 Example: op-level validaion of a MP3 SoC The MP3 sysem The DMA block can ransfer The WRITER can wrie ino RAM The DECODER can: Copy he sream Decode he sream ino anoher forma (wav, pcm, ec.) WRITER and DECODER are concurren and synchronized: he WRITER is responsible o sar he DECODER MP3 DECODER sound1.mp3 SoC Archiecure WRITER1 sound1.mp3 DMA CHANNEL1 Exernal Peripheral sound1.mp3 sound2.mp3 sound2.mp3 WRITER2 CHANNEL2 sound2.mp3 RAM DECODER sound1.wav sound2.wav sound1.wav sound2.wav 7 1 Wrie Transacional Models (TM): he DECODER reques_wai_decode_done reques_decode decode wai_decode_done Inernals of block behavior need no be described in Eserel Sudio no Bus Cycle Accurae level, no Cycle Accurae level 4

5 2 Pu All TM Models in Parallel 9 3 Auomaically Generae TM coverage ess 10 5

6 3 Generaed ess cover 100% saes of he TM TM Inpus sequences Coverage Repor 11 3 Colleced Oupus C Tes Case Scrip o C or oher languages 12 6

7 4 From Transacional Level o Simulaion Plaform C Top Level Validaion Tesbench TRANSACTIONS void run_es() { ransfer(); Transacor Libraries wrie(); wai_ransfer_done(); decode(); wai_wrie_done(); wai_decode_done(); } void ransfer() { *(*in)dma_channel_reg = (in) REG_INIT; inipor(0x ); Simulaion Plaform } void wrie() { } 13 4 Transacion execuion profile on a CPU or simulaion plaform The generaed esbench cover ineroperabiliy and concurren behaviors of SoC inernal blocks ransfer() wrie() void run_es() { ransfer(); wrie(); wai_ransfer_done(); decode(); wai_wrie_done(); wai_decode_done(); } wai_ransfer_done() decode() wai_wrie_done() wai_decode_done() 14 7

8 Refinemen 1: Adding consrains o direc es generaion Fine Tune concurrency Take ino accoun sysem consrain and resricion Mach he es plan Use of exising libraries SarX = ransfer() DMA EndX = wai_ransfer_done() SarY = wrie() WRITER EndY = wai_wrie_done() 15 Schedules Produciviy Gain 2 weeks 3 weeks 2 weeks ~1200 ess Using ES Specificaion undersanding Transacional Model and consrains Tes generaion and inegraion Hand wrien Specificaion undersanding Tess wrien by hand...? weeks Generaed Tes Cases Configuraion Model Generaed Tess Files Configuraion Model Generaed Tess Files pes1 scd1 vld1 pes2 scd2 vld2 aler saes rans cov. ype # of ess pes1 scd1 vld1 pes2 scd2 vld2 aler saes rans cov. ype # of ess dec7_conf1_seqdc_s_ou.esi X X X sae 50 dec7_conf1_seqdc_s_ou.esi X X X sae 50 dec7_conf1_seqdc_t_ou.esi X X X ransiion 364 dec7_conf1_seqdc_t_ou.esi X X X ransiion 364 dec7_conf12_seqdc_s_ou.esi X X X X sae 278 dec7_conf12_seqdc_s_ou.esi X X X X sae 278 dec7_conf12va_seqdc_s_ou.es X X X X X X X sae 1188 dec7_conf12va_seqdc_s_ou.es X X X X X X X sae

9 Generaed es cases are compac and efficien Tes generaion sraegy Eserel Sudio Random or Direced Random Manual coding % Coverage (sae and ransiion) Produciviy Gain: 40 % 100 % Qualiy gain in corner cases? % 60 % 100 % Top Level Validaion Coverage Tes case size Producion effor (available) 17 Eserel Sudio SoC op-level validaion: benefis summary Applicable o acual CPUs as well as any simulaion plaform Requires minimal blocks and IPs documenaion The generaed esbench is exremely efficien o cover concurren behaviors of SoC inernal blocks and ineroperabiliy Applicable o muli-core designs Generaed esbench shows excellen coverage vs. size efficiency and is good a reaching corner cases 18 9

10 Eserel Sudio C++ Eserel syle loop [ awai A awai B ] ; emi O each R DWORD WINAPI Thread_A(LPVOID lpsar){ for (;;) { if (R) { R = 0; ExiThread(1); } if (A) { A = 0; ExiThread(0); } } } DWORD WINAPI Thread_B(LPVOID lpsar){ for (;;) { if (R) { R = 0; ExiThread(1); } if (B) { B = 0; ExiThread(0); } } } in APIENTRY WinMain(HINSTANCE hinsance, HINSTANCE hprevinsance, LPSTR lpszcmdline, in ncmdshow) { DWORD x=0; DWORD ExiCode[2]; HINST = hinsance; hhread[2] = CreaeThread(NULL,0, (LPTHREAD_START_ROUTINE) ConrolPanel, (LPVOID) &x,0,&dwthreadid[2]); for (;;) { hhread[0] = CreaeThread (NULL,0,(LPTHREAD_START_ROUTINE) Thread_A, (LPVOID) &x,0,&dwthreadid[0]); hhread[1] = CreaeThread (NULL,0,(LPTHREAD_START_ROUTINE) Thread_B, (LPVOID) &x,0,&dwthreadid[1]); WaiForMulipleObjecs(2,hhread,TRUE,INFINITE); GeExiCodeThread(hhread[0], &ExiCode[0]); GeExiCodeThread(hhread[1], &ExiCode[1]); if (!ExiCode[0] &&!ExiCode[1]) { O(); for (;;) if (R) break; } } } 19 Sae Noion 20 10

11 A mehodology for SoC op-level validaion Elecronic Design Process 02 Sylvan Dissoubray Monerey 21 11

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