HIGHLY INTEGRATED 4A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

Transcription

1 SupIRBuck TM HIGHLY INTEGRATED 4A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR eature Wide Input Vltage Range 2.5V t 2V Wide Output Vltage Range 0.6V t 2V Cntinuu 4A Lad Capability 600kHz High requency Operatin Prgrammable Over-Current-Prtectin Hiccup Current Limit Tracking capability fr Memry Applicatin Preciin Reference Vltage (0.6V) Prgrammable Sft-Start Pre-Bia Start-up Thermal Prtectin Thermally Enhanced Package Small Size 5mmx6mm QN Pb-ree (RHS Cmpliant) Applicatin Ditributed Pint-f-Lad Server and Wrktatin Embedded Sytem Strage Sytem DDR Applicatin Graphic Card Game Cnle Cmputing Peripheral Vltage Regulatr Decriptin The IR82 SupIRBuck TM i an eay-t-ue, fully integrated and highly efficient DC/DC regulatr. The nbard witching cntrller and MOSET make the IR82 a pace-efficient lutin, prviding accurate pwer delivery fr lw utput vltage applicatin. The IR82 perate frm a ingle 4.5V t 4V input upply and generate an utput vltage adjutable frm 0.6V t 0.75*Vin at lad up t 4A. IR82 can be cnfigured fr tracking applicatin t generate terminatin vltage (VTT) fr memry applicatin. A veratile regulatr ffering prgrammability f tart up time and current limit, the IR82 fixed 600kHz witching frequency allw the ue f mall external cmpnent. IR82 al feature imprtant prtectin functin, uch a Pre-Bia tartup, hiccup current limit and thermal hutdwn t prvide the required ytem level ecurity in the event f fault cnditin. ig.. Typical applicatin diagram

2 ABSOLUTE MAXIMUM RATINGS (Vltage referenced t GND) PACKAGE INORMATION 5mm x 6mm POWER QN V IN Supply Vltage -0.V t 24V Vcc Supply Vltage -0.V t 6V Vc Supply Vltage -0.V t 0V SW -0.V t 0V PGd -0.V t 6V b,comp,ss,vn -0.V t.5v OCSet 0mA AGnd t PGnd -0.V t +0.V Strage Temperature Range -65 C T 50 C Operating Junctin Temperature Range -40 C T 50 C ESD Claificatin JEDEC, JESD22-A4 Miture Senitivity Level JEDEC 260 C Cautin: Stree beynd the lited under Ablute Maximum Rating may caue permanent damage t the device. Thee are tre rating nly and functinal peratin f the device at thee r any ther cnditin beynd the indicated in the peratinal ectin f the pecificatin i nt implied. Expure t Ablute Maximum Rating cnditin fr extended perid may affect device reliability. 2 V IN SW 0 PGnd θ θ JA J-PCB 5 C / W 2 C / W HG 5 AGnd 9 Vref Vc 4 8 V CC Vp B COMP AGnd AGnd SS OCSet ig. 2: Package utline (Tp view) ORDERING INORMATION PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR82MTRPb M IR82MTRPb

3 Blck Diagram ig.. Simplified blck diagram f the IR82.

4 Pin Decriptin Pin Name Decriptin Vp Nn-inverting input f errr amplifier. Thi pin can be ued fr tracking applicatin. 2 b Inverting input t the errr amplifier. Thi pin i cnnected directly t the utput f the regulatr via reitr divider t et the utput vltage and prvide feedback t the errr amplifier. Cmp Output f errr amplifier. An external reitr and capacitr netwrk i typically cnnected frm thi pin t grund t prvide lp cmpenatin. 4 AGnd Signal grund fr internal reference and cntrl circuitry. 5 AGnd Signal grund fr internal reference and cntrl circuitry. 6 SS/SD Sft tart / hutdwn. Thi pin prvide uer prgrammable ft-tart functin. Cnnect an external capacitr frm thi pin t grund t et the tart up time f the utput vltage. The cnverter can be hutdwn by pulling thi pin belw 0.V. 7 OCSet Current limit et pint. A reitr frm thi pin t SW pin will et the current limit threhld. 8 V CC Thi pin pwer the internal IC a well a lw ide driver. A minimum f 0.u high frequency capacitr mut be cnnected frm thi pin t the pwer grund. 9 Vref External reference vltage. Drive capability fr thi pin i 2μA. 0 PGnd Pwer Grund. Thi pin erve a a eparated grund fr the MOSET driver and huld be cnnected t the ytem pwer grund plane. SW Switch nde. Thi pin i cnnected t the utput inductr 2 V IN Input vltage cnnectin pin HG Thi pin i cnnected t the high ide gate driver. Cnnect a mall capacitr frm thi pin t witch nde (SW). 4 V C Thi pin pwer the high ide driver and mut be cnnected t a vltage higher than input vltage. A minimum f 0.u high frequency capacitr mut be cnnected frm thi pin t the pwer grund fr the charge-pump high ide drive cheme. 5 AGnd Signal grund fr internal reference and cntrl circuitry. Pin 4, 5 and 5 need t be cnnected tgether n ytem bard. 4

5 Recmmended Operating Cnditin Symbl Definitin Min Max Unit V in Input Vltage V cc Supply Vltage V c Supply Vltage Vin + 5V 28 V V Output Vltage I Nte Output Current 0 4 A T j Junctin Temperature C Electrical Specificatin Unle therwie pecified, thee pecificatin apply ver VinV cc V c 2V, 0 C<T j (Ic)< 05 C. Typical value are pecified at T a 25 C. Pwer L Parameter Symbl Tet Cnditin Min TYP MAX Unit Pwer L P l VccV in 2V, Vc24V, V.8V, I 4A, L2uH, Nte.5 W MOSET R d(n) Tp Switch R d(n)_tp I D 6A, Tj(MOSET)25 C 8 2 Bttm Switch R d(n)_bt I D 6A, Tj(MOSET)25 C 8 2 mω Reference Vltage eedback Vltage V B 0.6 V Accuracy 0 C<Tj<05 C % -40 C<Tj<05 C, Nte % Supply Current V CC Supply Current (Static) I CC(Static) SS0V, N Switching 0 V C Supply Current (Static) V CC Supply Current (Dynamic) V C Supply Current (Dynamic) Under Vltage Lckut I C(Static) SS0V, N Switching I CC(Dynamic) I C(Dynamic) SSV, V c 24V, V cc V in 2V. V.8V, I0A SSV, V c 24V, V cc V in 2V. V.8V, I0A ma V CC -Start-Threhld V CC _UVLO(R) Supply ramping up V CC -Stp-Threhld V CC _UVLO() Supply ramping dwn.7 4. V CC -Hyterei Supply ramping up and dwn V C -Start-Threhld V C _UVLO(R) Supply ramping up..5 V V C -Stp-Threhld V C _UVLO() Supply ramping dwn V C -Hyterei Supply ramping up and dwn

6 Parameter SYM Tet Cnditin Min TYP MAX Unit Ocillatr requency S khz Ramp Amplitude V ramp Nte.25 V Min Pule Width D min(ctrl) Nte 80 n Max Duty Cycle D max b0v 75 % Errr Amplifier Input Bia Current I B SSV Input Bia Current I Vp SSV Input Bia Current I B2 SS0V μa Surce/Sink Current I(urce/Sink) Trancnductance gm μmh Input Offet Vltage V b t Vp mv Vp( (Cmmn Mde Range) V Sft Start/SD Sft Start Current I SS SS0V μa Shutdwn Output Threhld SD 0.25 V Over Current Prtectin OCSET Current I OCSET Hiccup Current I Hiccup Nte μa Hiccup Duty Cycle Hiccup(duty) I Hiccup / I SS, Nte 5 % Thermal Shutdwn Thermal Shutdwn Threhld 40 Nte Thermal Shutdwn Hyterei Nte 20 C Nte: Cntinuu utput current determined by input and utput vltage etting and the thermal envirnment. Nte2: Cld temperature perfrmance i guaranteed via crrelatin uing tatitical quality cntrl. Nt teted in prductin. Nte: Guaranteed by Deign but nt teted in prductin. 6

7 TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C) Icc(tatic) Ic(tatic) [ma] Temp[C] [ma] Temp[C] Icc(dynamic) Ic(dynamic) [ma] Temp[C] [ma] Temp[C] Vfb ISS [mv] Temp[C] [ua] Temp[C] Trancnductance IOCSET [mmh] Temp[C] [ua] Temp[C] 7

8 Circuit Decriptin THEORY O OPERATION The IR82 i a vltage mde PWM ynchrnu regulatr and perate with a fixed 600kHz witching frequency, allwing the ue f mall external cmpnent. The utput vltage i et by feedback pin (b) and the internal reference vltage (0.6V). Thee are tw input t errr amplifier. The errr ignal between thee tw input i amplified and it i cmpared t a fixed frequency linear awtth ramp. A trailing edge mdulatin i ued fr generating fixed frequency pule (PWM) which drive the internal N-channel MOSET. The internal cillatr circuit ue n-chip circuitry, eliminating the need fr external cmpnent. The IR82 perate with ingle input vltage frm 4.5V t 4V allwing an extended perating input vltage range. The ver-current prtectin i perfrmed by ening current thrugh the R DS(n) f lw ide MOSET. Thi methd enhance the cnverter efficiency and reduce ct by eliminating a current ene reitr. The current limit i prgrammable by uing an external reitr. Under-Vltage Lckut The under-vltage lckut circuit mnitr the tw input upplie (Vcc and Vc) and aure that the MOSET driver utput remain in the ff tate whenever the upply vltage drp belw et threhld. Lckut ccur if Vcc r Vc fall belw 4.V and.v repectively. Nrmal peratin reume nce Vcc and Vc rie abve the et value. Thermal Shutdwn Temperature ening i prvided inide the IR82. The trip threhld i typically et t 40 C. When trip threhld i exceeded, thermal hutdwn turn ff bth MOSET. Thermal hutdwn i nt latched and autmatic retart i initiated when the ened temperature drp within the perating range. There i a 20 C hyterei in the thermal hutdwn threhld. Pre-Bia Startup The IR82 i able t tart up int pre-charged utput, which prevent cillatin and diturbance f the utput vltage. The utput tart in aynchrnu fahin and keep the ynchrnu MOSET ff until the firt gate ignal fr cntrl MOSET i generated. igure 4 hw a typical Pre-Bia cnditin at tart up. Depending n ytem cnfiguratin, a pecific number f utput capacitr may be required t prevent dicharging the utput vltage. V Pre-Bia Vltage ig. 4: Pre-Bia tart up V Time Shutdwn The utput can be hutdwn by pulling the fttart pin belw 0.V. Thi can eaily be dne by uing an external mall ignal tranitr. During hutdwn bth MOSET driver will be turned ff. Nrmal peratin will reume by cycling ft tart pin. External Reference and Tracking IR82 i able t perate a a tand alne regulatr by cnnecting the Vref t Vp. In thi cae the reference vltage i 0.6V. r tracking applicatin Vref pin can be left flating and the Vp pin will be cnnected t mater vltage which IR82 will track. In thi cae the Vp vltage i the IC reference vltage. 8

9 Sft-Start The IR82 ha prgrammable ft-tart t cntrl the utput vltage rie and limit the inruh current during tart-up. T enure crrect tart-up, the ft-tart equence initiate when Vcc and Vc rie abve their threhld and generate the Pwer On Ready (POR) ignal. The ft-tart functin perate by urcing current t charge an external capacitr t abut V. Initially, the ft-tart functin clamp the utput f errr amplifier by injecting a current (40uA) int the b pin and generate a vltage abut 0.96V (40ux24K) acr the negative input f errr amplifier (ee figure 5). The magnitude f the injected current i inverely prprtinal t the vltage at the ft-tart pin. A the ft-tart vltage ramp up, the injected current decreae linearly and de the vltage at negative input f errr amplifier. When the ft-tart capacitr i arund V, the vltage at the pitive input f the errr amplifier i apprximately 0.6V. The utput f errr amplifier will tart increaing and generating the firt PWM ignal. A the fttart capacitr vltage cntinue t rie up, the current flwing int the b pin will keep decreaing. The feedback vltage increae linearly a the ft tart vltage ramp up. When ft-tart vltage i arund 2V, the utput vltage reache the teady tate and the injected current i zer. igure 6 hw the theretical perating wavefrm during ft-tart. The utput vltage tart-up time i the time perid when ft-tart capacitr vltage increae frm V t 2V. The tart-up time will be dependent n the ize f the external ft-tart capacitr and can be etimated by: T 20μA C tart 2V V SS/SD Cmp 0.6V b POR 20uA 24K 24K V 40uA Errr Amp ig. 5: Sft-Start circuit fr IR82 Output f UVLO POR Sft-Start Vltage Current flwing int b pin Vltage at negative input 0.96V f Errr Amp Vltage at b pin 0V 40uA 0V 0uA 0.6V 0.6V V 2V V ig. 6: Theretical peratin wavefrm during ft-tart r a given tart-up time, the ft-tart capacitr can be etimated a: CSS 20μA * Ttart( m) --( ) 9

10 Over-Current Prtectin The ver current prtectin i perfrmed by ening current thrugh the R DS(n) f the lwide MOSET. Thi methd enhance the cnverter efficiency and reduce ct by eliminating a current ene reitr. A hwn in figure 7, an external reitr (R SET ) i cnnected between OCSet pin and the inductr pint which et the current limit et pint. The internal current urce develp a vltage acr R SET. When the lw ide MOSET i turned n, the inductr current flw thrugh the Q2 and reult a vltage which i given by: VOCSet (IOCSet ROCSet ) (RDS(n) IL ) --( 2) ig. 8: ua current urce fr dicharging ft-tart capacitr during hiccup The OCP circuit tart ampling current when the lw gate drive i abut V. The OCSet pin i internally clamped abut.5v during n time f high ide gate t prevent fale trigging, figure 9 hw the OCSet pin during ne witching cycle. A hwn, there i abut 50n delay t mak the dead time. Since thi nde cntain witching nie, thi delay al functin a a filter. Deadtime ig. 7: Cnnectin f ver current ening reitr I OCSet *R OCSet Blanking time Clamp vltage The critical inductr current can be calculated by etting: VOCSet (IOCSet ROCSet) (RDS(n) IL) 0 I SET I L( critical ) R OCSet --( ) An ver current i detected if the OCSet pin ge belw grund. Thi trip the OCP cmparatr and cycle the ft tart functin in hiccup mde. The hiccup i perfrmed by charging and dicharging the ft-tart capacitr in a certain lpe rate. A hwn in figure 8 a ua current urce i ued t dicharge the ft-tart capacitr. The OCP cmparatr reet after every ft tart cycle. The cnverter tay in thi mde until the verlad r hrt circuit i remved. The cnverter will autmatically recver. R I DS ( n ) OCSet ig. 9: OCet pin during nrmal cnditin Ch: Inductr pint, Ch:OCSet The value f R SET huld be checked in an actual circuit t enure that the ver current prtectin circuit activate a expected. The IR82 current limit i deigned primarily a diater preventing, and den't perate a a preciin current regulatr. 0

11 Applicatin Infrmatin Deign Example: The fllwing example i a typical applicatin fr the IR82. The applicatin circuit i hwn in page 7. V V I ΔV in 2V,(.2V, max 0.75V 4 A 0 mv 600 khz Output Vltage Prgramming Output vltage i prgrammed by reference vltage and external vltage divider. The b pin i the inverting input f the errr amplifier, which i internally referenced t 0.6V. The divider i ratied t prvide 0.6V at the b pin when the utput i at it deired value. The utput vltage i defined by uing the fllwing equatin: V V ref R + R 8 9 When an external reitr divider i cnnected t the utput a hwn in figure 0. IR624 IR82 b ) --(4 ) VOUT R8 R9 Sft-Start Prgramming The ft-tart timing can be prgrammed by electing the ft-tart capacitance value. The tart-up time f the cnverter can be calculated by uing: CSS 20μA * T Where T tart i the deired tart-up time (m) r a tart-up time f m, the ft-tart capacitr will be 0.22u. Vc upply fr ingle input vltage T drive the high ide witch, it i neceary t upply a gate vltage at leat 4V greater than the bu vltage. Thi i achieved by uing a charge pump cnfiguratin a hwn in figure. Thi methd i imple and inexpenive. The peratin f the circuit i a fllw: when the lwer MOSET i turned n, the capacitr (C) i pulled dwn t grund and charge, up t V BUS value, thrugh the dide (D). The bu vltage will be added t thi vltage when upper MOSET turn n in next cycle, and prviding upply vltage (Vc) thrugh dide (D2). Vc i apprximately: ( V V ) --(6 ) V 2 V + C bu D D2 --( ) Capacitr in the range f 0.u are generally adequate fr mt applicatin. The dide mut be a fat recvery device t minimize the amunt f charge fed back frm the charge pump capacitr int V BUS. The dide need t be able t blck the full pwer rail vltage, which i een when the high ide MOSET i witched n. r lw vltage applicatin, chttky dide can be ued t minimize frward drp acr the dide at tart up. tart ig. 0: Typical applicatin f the IR82 fr prgramming the utput vltage Equatin (4) can be rewritten a: Vref R9 R8 --(5 ) V V O ref r the calculated value f R 8 and R 9 feedback cmpenatin ectin. ee ig. : Charge pump circuit t generate Vc vltage

12 Input Capacitr Selectin The input filter capacitr huld be elected baed n hw much ripple the upply can tlerate n the DC input line. The ripple current generated during the n time f upper MOSET huld be prvided by the input capacitr. The RMS value f thi ripple i expreed by: V Where: D Vin D i the Duty Cycle I RMS i the RMS value f the input capacitr current. I i the utput current. r I4A and D0.0625, the I RMS 0.97A. Ceramic capacitr are recmmended due t their peak current capabilitie. They al feature lw ESR and ESL at higher frequency which reult in better efficiency, Ue x0u, 6V ceramic capacitr frm Pananic. Inductr Selectin The inductr i elected baed n utput pwer, perating frequency and efficiency requirement. A lw inductr value caue a large ripple current, reulting in the maller ize, fater repne t a lad tranient but pr efficiency and high utput nie. Generally, the electin f the inductr value can be reduced t the deired maximum ripple current in the inductr ( Δi ). The ptimum pint i uually fund between 20% and 50% ripple f the utput current. r the buck cnverter, the inductr value fr the deired perating ripple current can be determined uing the fllwing: Where: V in IRMS I D ( D) Δ i V V L t D in ; Δ Δt L Δt Turn n time V V Δi * --(7) ( V V ) --(8 ) V Output Vltage in Maximum input vltage Δi Inductr ripple current Switching frequency D Duty cycle in If Δi 50%(I,) then the utput inductr will be: L 0.6uH Delta MLP-04 erie prvide a range f inductr in different value, and mall ize uitable fr thi applicatin. Output Capacitr Selectin The vltage ripple and tranient requirement determine the utput capacitr type and value. The criteria i nrmally baed n the value f the Effective Serie Reitance (ESR). Hwever the actual capacitance value and the Equivalent Serie Inductance (ESL) are ther cntributing cmpnent. Thee cmpnent can be decribed a: ΔV ΔV ΔV ΔV ΔV ( ESR) ( ESL) ( C) + ΔV ΔI * ESR Vin * ESL L ΔIL 8 * C * + ΔV - -(9) ΔV Output vltage ripple ΔI Inductr ripple current L ( ESR) L ( ESL) ( C) Since the utput capacitr ha a majr rle in the verall perfrmance f cnverter and determine the reult f tranient repne, electin f the capacitr i critical. The IR82 can perfrm well with all type f capacitr. A a rule the capacitr mut have lw enugh ESR t meet utput ripple and lad tranient requirement, yet have high enugh ESR t atify tability requirement. The gal fr thi deign i t meet the vltage ripple requirement in the mallet pible capacitr ize. Therefre, a ceramic capacitr i elected due t it lw ESR and mall ize. ur f the Pananic ECJ2B0J226M (22u, 6.V, X5R and EIA 0805 cae ize) are a gd chice. In the cae f tantalum r lw ESR electrlytic capacitr, the ESR dminate the utput vltage ripple, equatin (9) can be ued t calculate the required ESR fr the pecific vltage ripple. 2

13 eedback Cmpenatin The IR82 i a vltage mde cntrller; the cntrl lp i a ingle vltage feedback path including errr amplifier and errr cmparatr. T achieve fat tranient repne and accurate utput regulatin, a cmpenatin circuit i neceary. The gal f the cmpenatin netwrk i t prvide a cled lp tranfer functin with the highet 0dB cring frequency and adequate phae margin (greater than 45 ). The utput LC filter intrduce a duble ple, 40dB/decade gain lpe abve it crner renant frequency, and a ttal phae lag f 80 (ee figure ). The renant frequency f the LC filter expreed a fllw: The ESR zer f the utput capacitr expreed a fllw: (2) ESR 2 π * ESR* C VOUT R8 R9 VRE H() db b Gain(dB) E/A Cmp R C4 Ve CPOLE LC 2 π L C () Z requency igure hw gain and phae f the LC filter. Since we already have 80 phae hift frm the utput filter alng, the ytem rik being untable. 0dB Gain The IR82 errr amplifier i a differential-input trancnductance amplifier. The utput i available fr DC gain cntrl r AC phae cmpenatin. The errr amplifier can be cmpenated either in type II r typeiii cmpenatin. When it i ued in type II cmpenatin the trancnductance prpertie f the errr amplifier becme evident and can be ued t cancel ne f the utput filter ple. Thi will be accmplihed with a erie RC circuit frm Cmp pin t grund a hwn in figure 4. Thi methd require that the utput capacitr huld have enugh ESR t atify tability requirement. In general the utput capacitr ESR generate a zer typically at 5kHz t 50kHz which i eential fr an acceptable phae margin. LC -40dB/decade requency Phae 0-80 LC ig. : Gain and Phae f LC filter requency ig. 4: TypeII cmpenatin netwrk and it aympttic gain plt The tranfer functin (Ve/V) i given by: H() R9 gm * R + R 9 + RC 4 * C () The () indicate that the tranfer functin varie a a functin f frequency. Thi cnfiguratin intrduce a gain and zer expreed by: R 9 gm * * R R9 R + 8 z * R * C [ H( ) ] The gain i determined by the vltage divider and errr amplifier trancnductance gain. irt elect the deired zer-crver frequency (): > and /5 ~/0 * ESR Ue the fllwing equatin t calculate R: V R c 8 4 Where: V in Maximum Input Vltage V c Ocillatr Ramp Vltage Crver requency ESR Zer requency f the Output Capacitr LC Renant requency f the Output ilter R 8 and R 9 eedback Reitr Divider g m Errr Amplifier Trancnductance (5) (4) ( ) * * * (R + R ) ESR V * * R * g in LC 9 m (6)

14 T cancel ne f the LC filter ple, place the zer befre the LC filter renant frequency ple: ZIN VOUT C 75% z LC z * L * C (7) C7 R0 R8 R C4 Zf Ue equatin (5) and (6) t calculate C4. One mre capacitr i metime added in parallel with C4 and R. Thi intrduce ne mre ple which i mainly ued t uppre the witching nie. The additinal ple i given by: P C4 * CPOLE * R * C + C POLE The ple et t ne half f witching frequency which reult in the capacitr C POLE : C POLE π * R * r << P 2 r a general lutin fr uncnditinal tability fr any type f utput capacitr, in a wide range f ESR value we huld implement lcal feedback with a cmpenatin netwrk (type III). The typically ued cmpenatin netwrk fr vltage-mde cntrller i hwn in figure 5. In uch a cnfiguratin, the tranfer functin i given by: V g Z e m f V + g Z The errr amplifier gain i independent f the trancnductance under the fllwing cnditin: By replacing Z in and Z f accrding t figure 5, the tranfrmer functin can be expreed a: 4 C gm * Zf >> and gm * Zin >> m 4 π * R * IN (8) [ + C ( R + R )] ( + RC4 ) * 7 8 H( ) * R ( C + C ) 8 4 C * C 4 + R * ( + R C C C ) 7 H() db ig.5: Cmpenatin netwrk with lcal feedback and it aympttic gain plt A knwn, the trancnductance amplifier ha high impedance (current urce) utput, therefre, cnideratin huld be taken when lading the errr amplifier utput. It may exceed it urce/ink utput current capability, that the amplifier will nt be able t wing it utput vltage ver the neceary range. The cmpenatin netwrk ha three ple and tw zer and they are expreed a fllw: P P 2 P z z2 Gain(dB) 0 * R 0 7 R9 * C 4 7 C * C * R 4 * R C C + 4 * R * C * C * ( R + R ) * C * R 8 VRE Cr ver frequency i expreed a: V in R * C * * 7 V * L * C c b 0 E/A Z Z2 P2 P * C 7 8 Cmp requency Ve 4

15 Baed n the frequency f the zer generated by the utput capacitr and it ESR veru crver frequency, the cmpenatin type can be different. The table belw hw the cmpenatin type and lcatin f crver frequency. Cmpenatr type Type II(PI) Type III(PID) Methd A Type III(PID) Methd B ESR v. LC < ESR < < /2 LC < < ESR < /2 LC < < /2 < ESR Output capacitr Electrlytic, Tantalum Tantalum, ceramic Ceramic Table- The cmpenatin type and lcatin f ESR veru The detail f thee cmpenatin type are dicued in applicatin nte AN-04 which can be dwnladed frm IR webite at r thi deign we have: V in 2V V 0.75V V c.25v V ref 0.6V g m 000umh L 0.60uH C 4x22u, ESR0.8mOhm 600kHz The value f the capacitance ued in the cmpenatr deign mut be the mall ignal value. r intance, the mall ignal capacitance f the 22u capacitr ued in thi deign i 2u at.8 VDC bia and 600 khz frequency. It i thi value that mut be ued fr all cmputatin related t the cmpenatin. The mall ignal value may be btained frm the manufacturer dataheet, deign tl r SPICE mdel. Alternatively, they may al be inferred frm meauring the pwer tage tranfer functin f the cnverter and meauring the duble ple frequency LC and uing equatin () t cmpute the mall ignal C. Thee reult t: LC 29.6kHz ESR 4.4MHz /2 600kHz Select crver frequency: < and /5 ~/0 * 80kHz Since: LC<</2<ESR, type III methd B i elected t place the ple and zer. The fllwing deign rule will give a crver frequency apprximately ne-tenth f the witching frequency. The higher the band width, the ptentially fater the lad tranient repne. The DC gain will be large enugh t prvide high DC-regulatin accuracy (typically -5dB t -2dB). The phae margin huld be greater than 45 fr verall tability. Deired Phae Bt: R Z2 Z2 P2 P2 -SinΘ * + SinΘ 4.kHz + SinΘ * -SinΘ 45.70kHz Select: CalculateC C4 * C * CalculateR 0.5* Select: C 80p * * L * C *V R C *V Select: R 8.25KΩ 0 ESR * C * Select: R R8 * C * Vref R9 V -V Z 7 0 ref Z P andc,r : andr ; R.96KΩ and 0.5* ;C4 2.74n, Select: C4 2.7n * R ;C 64.p, Select: C 56p * R 0 7 P2 Z2.95KΩ, checkr - R ; R 60.72KΩ, Select: R 60.4K Ω * R ; R 24.60KΩ, 8 8 in 9 ( ) Z2 0 0 OSC 9 : 8 Θ max 70 P, R 8.KΩ, checkr 0 g 2 g Select: R 24KΩ 9 m 8 m 5

16 Prgramming the Current-Limit The Current-Limit threhld can be et by cnnecting a reitr (R SET ) frm drain f the lw-ide MOSET t the OCSet pin. The reitr can be calculated by uing equatin (). The R DS(n) ha a pitive temperature cefficient and it huld be cnidered fr the wre cae peratin. Thi reitr mut be placed cle t the IC, place a mall ceramic capacitr frm thi pin t pwer grund (PGnd) fr nie rejectin purpe. I I I R Δi R SET I Where : L(critical ) R ROCSet I R Δi ISET (I.5) + 2 where : 9.5KΩ DS(n) : Max Output Current OCSet υ : Temperature Dependency Nte : Ue 24 mω fr lw - ide DS(n) if 5V i ued fr V : Inductr ripple current V Δi (Vin -V ) V L SET (4A*.5) A 6.97A OCSet - -() 8mΩ υ 8mΩ.5 27mΩ 7 in cc MOSET Layut Cnideratin The layut i very imprtant when deigning high frequency witching cnverter. Layut will affect nie pickup and can caue a gd deign t perfrm with le than expected reult. Start t place the pwer cmpnent, making all the cnnectin in the tp layer with wide, cpper filled area. The inductr, utput capacitr and the IR82 huld be a cle t each ther a pible. Thi help t reduce the EMI radiated by the pwer trace due t the high witching current thrugh them. Place the input capacitr directly t the Vin pin f IR82. T reduce the ESR replace the ingle input capacitr with tw parallel unit. The feedback part f the ytem huld be kept away frm the inductr and ther nie urce. The critical bypa cmpnent uch a capacitr fr Vcc and Vc huld be cle t their repective pin. It i imprtant t place the feedback cmpnent including feedback reitr and cmpenatin cmpnent cle t b and Cmp pin. In a multilayer PCB ue ne layer a a pwer grund plane and have a cntrl circuit grund (analg grund), t which all ignal are referenced. The gal i t lcalize the high current path t a eparate lp that de nt interfere with the mre enitive analg cntrl functin. Thee tw grund mut be cnnected tgether n the PC bard layut at a ingle pint. The Pwer QN i a thermally enhanced package. Baed n thermal perfrmance it i recmmended t ue at leat a 4-layer PCB. T effectively remve heat frm the device the exped pad huld be cnnected t the grund plane uing via. 6

17 Typical Applicatin fr IR82 2V t 4A ig.6: Typical Applicatin circuit fr 2V t 0.75V at 4A uing ceramic utput capacitr 7

18 PCB Metal and Cmpnent Placement The lead land (the IC pin) width huld be equal t the nminal part lead width. The minimum lead t lead pacing huld be 0.2mm t minimize hrting. Lead land length huld be equal t the maximum part lead length + 0. mm utbard extenin. The utbard extenin enure a large and inpectable te fillet. The pad land (the 4 big pad ther than the IC pin) length and width huld be equal t maximum part pad length and width. Hwever, the minimum metal-t-metal pacing huld be n le than 0.7mm fr 2 z. Cpper; n le than 0.mm fr z. Cpper and n le than 0.2mm fr z. Cpper. 8

19 Slder Reit It i recmmended that the lead land are Nn Slder Mak Defined (NSMD). The lder reit huld be pulled away frm the metal lead land by a minimum f 0.025mm t enure NSMD pad. The land pad huld be Slder Mak Defined (SMD), with a minimum verlap f the lder reit nt the cpper f 0.05mm t accmmdate lder reit mi-alignment. Enure that the lder reit in between the lead land and the pad land i 0.5mm due t the high apect rati f the lder reit trip eparating the lead land frm the pad land. 9

20 Stencil Deign The Stencil aperture fr the lead land huld be apprximately 80% f the area f the lead lad. Reducing the amunt f lder depited will minimize the ccurrence f lead hrt. If t much lder i depited n the center pad the part will flat and the lead land will be pen. The maximum length and width f the land pad tencil aperture huld be equal t the lder reit pening minu an annular 0.2mm pull back t decreae the incidence f hrting the center land t the lead land when the part i puhed int the lder pate. 20

21 IR WORLD HEADQUARTERS: 2 Kana St., El Segund, Califrnia 90245, USA Tel: (0) TAC ax: (0) Thi prduct ha been deigned and qualified fr the Cnumer market. Viit u at fr ale cntact infrmatin Data and pecificatin ubject t change withut ntice. 0/07 2