Research Article AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic

Transcription

1 Hindawi Publishing Corporaion EURASIP Journal on Embedded Sysems Volume 21, Aricle ID , 8 pages doi:1.1155/21/ Research Aricle AD-PLL for WiMAX wih Digially-Regulaed TDC and Glich Correcion Logic Salvaore Levanino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, and Andrea L. Lacaia Diparimeno di Eleronica e Informazione, Poliecnico di Milano, Piazza L. da Vinci, 32, 2133 Milano, Ialy Correspondence should be addressed o Salvaore Levanino, levanin@ele.polimi.i Received 3 June 29; Acceped 23 Sepember 29 Academic Edior: Sergio Saponara Copyrigh 21 Salvaore Levanino e al. This is an open access aricle disribued under he Creaive Commons Aribuion License, which permis unresriced use, disribuion, and reproducion in any medium, provided he original work is properly cied. This paper describes he design of an All-Digial Phase Locked Loop (AD-PLL) for wireless applicaions in he WiMAX GHz bandwidh. The ime/digial converer (TDC) ses he in-band noise and i may be responsible for he presence of spurious ones a he PLL oupu. The TDC is implemened as a delay-locked loop (DLL) o be insensiive o process spreads and i uses a lead-lag phase deecor and a digial loop filer o furher ake advanage of he digial approach. The mos imporan source of spurs is idenified in he ime skew beween couner and TDC in he PLL. This mechanism gives rise o a glich in he digial feedback signal and spurs in he oupu specrum. A simple glich-correcor logic is described, ha compleely removes his effec, hus allowing o mee he phase noise specificaions. The AD-PLL has been designed in a 9 nm CMOS process. 1. Inroducion In recen years, he mixed-signal approach no only has pervaded many applicaions ha once were exclusively a subjec for he analog design bu also has begun o play an imporan role also in radiofrequency (RF) fron-ends. As a maer of fac, he realizaion of sofware definedradio (SDR) is one of he mos imporan research opic in recen years [1, 2]. In hese soluions, digial (or digiallike) circuis are employed no only o calibrae he circui parameers bu also o realize ransceiver building blocks, ofen adoping a new design approach, such as ransferring he informaion processing from he ampliude o he ime domain. These echniques, besides increasing he circui flexibiliy and funcionaliy, are expeced o beer exploi he scaling of CMOS echnology, o reduce he impac of PVT spreads, o faciliae, a leas o a cerain exen, he porabiliy of a given design, and o allow for he use of auomaic design ools. The all-digial phase-locked loop (AD-PLL) represens he applicaion of his approach o he design of PLL [3 5]. The digiizaion of PLL is an old idea, exploied, for insance, in he clock generaors for digial circuis. In recen implemenaions, however, he AD-PLL is employed as frequency synhesizer for wireless sysems, which implies igh specificaion in erms of specral puriy, ha is, phase noise and spurs. This fac, for insance, sill forces o use an LC-ank oscillaor, o ensure he required phase noise performance. The oher criical block, concerning he specral performance, is he ime-o-digial converer (TDC). This circui is essenially he equivalen of an analog-odigial converer, deecing ime (or phase) delays. Of course, i should no rely on sandard analog design soluions; oherwise some of he above menioned advanages will be los. The TDC is criical in many aspecs: i is known ha is ime resoluion affecs he in-band noise, while he nonlineariy os saic characerisic can give rise o oupu spurs [4]. This work presens he design of an AD-PLL for a GHz WiMAX ransmier. In his loop, he TDC is implemened as a digially-regulaed delay line. This is advanageous because of he simpliciy of he design, bu i requires some care in reducing he generaed limi cycle o negligible values.

2 2 EURASIP Journal on Embedded Sysems FCW + f e 1 R e Digial 1 z 1 filer + 1 z 1 Couner f f 1 z 1 TDC DCO Figure 1: The AD-PLL block schemaic. The unavoidable ime skew beween he TDC and he couner inpus gives rise o gliches in he AD-PLL feedback signal and ulimaely o severe spurious ones in he oupu specrum. This effec is no relaed o our specific implemenaion of he TDC, bu i may affec any common TDC implemenaions. In his paper, we will show how o predic hese skew-induced spurs and we will propose a digial glich correcor, which is able o operae eiher when he loop is locked and when he loop is in he lock ransien. In he nex Secion, he operaing principle of he AD- PLL including a couner and a TDC is recalled. Secion 3 discusses he advanages of he closed-loop TDC, while Secion 4 presens he proposed TDC and explains he presence of he limi cycle in he DLL. Secion 5 discusses he generaion of gliches in he presence of ime skew beween couner and TDC. Secion 6 proposes a simple glich-correcor logic. The schemaic of he complee AD- PLL is presened in Secion 7, ogeher wih he simulaion resuls. Finally, he conclusions are drawn in Secion Combined Operaion of TDC and Couner The basic schemaic of he AD-PLL considered in his work is repored in Figure 1 [4, 6]. I is equivalen o he original srucure proposed in [3], which can be obained by simply shifing he digial inegraor 1/(1 z 1 )backward beween he digial Frequency Conrol Word (FCW) and he adder, and removing he derivaives (1 z 1 ) in he feedback pah. The loop filer feaures a proporionalinegral ransfer funcion; is oupu unes an LC-ank Digial-Conrolled Oscillaor (DCO) by conrolling a bank of swiched capaciors in parallel o he inducor. All he blocks enclosed in he gray box are clocked a he erence frequency f. The error signal a he adder oupu f e is given by he difference beween FCW and he number of DCO periods occurring wihin one erence period T = 1/f.The loop forces his error signal o be zero; heore, if f = 1/T is he DCO frequency, he FCW ses he oupu frequency as f = FCW f. The signal f e is a digial number represening he frequency error. This number is hen inegraed o provide he phase error R e, whose average is forced o be zero by he loop. Wih respec o he original design in [3], he open-loop gain is no alered. The advanage of he srucure in Figure 1 is ha he design of he adder is simpler since is inpu word lenghs are reduced. If he FCW were an ineger number, only a couner would be necessary in he feedback pah. The presence of he TDC is needed because in general FCW may have also a fracional par. For convenience, le us spli FCW ino wo pars: an ineger one (FCW i ) and a fracional one (FCW f ). The couner oupu provides he number oneger DCO periods wihin T, ha is, he ineger par of he ( f / f ) raio. The TDC quanizes he fracional par f f of ( f / f ). The lock condiions are FCW i = and FCW f = f f. I is imporan, for wha follows, o beer underline he concurren operaions of he couner-tdc ensemble. The TDC inpu range has o cover a single erence period. We consider a very simple case in Figure 2, where FCW = 2.25 and he TDC has 8 levels or 3 bis. In a real case, he ineger par of he FCW is much larger and he number of TDC bis is higher, bu his simplificaion does no affec he presen reasoning. Figure 2(a) shows ha he couner oupu afer differeniaion (i.e., he number ) is 2, for hree erence clock periods ou of four, and i is 3 for one clock period ou of four. The TDC oupu afer differeniaion ( f f )provides he fracional par of he FCW, so ha he frequency error f e is always zero. e ha he average value of is 2.25, while he average value of f s zero. When incremens from 2 o 3, he TDC inpu exceeds he limi os dynamic; ha is, i overflows, and is oupu afer differeniaion ( f f ) becomes negaive. Figure 2(b) evidences ha he ensemble TDC/couner operaes as a subranging ADC, which implies ha he TDC characerisics mus be perfecly embedded in a couner bin in he ideal case. A seady sae, a each erence edge, he converer coun will incremen by 2.25 (in our example). Thus, he fracional coun will incremen by.25 and he TDC characerisic will be swep forward. I is easy o see ha, in he case of FCW f higher han.5, he couner would decrease is coun by one uniy when he differeniaed TDC oupu underflows and he TDC characerisic would be swep backward. 3. Closed-Loop TDC As recalled above, he TDC is a key block for he performance of he whole AD-PLL. Figure 3 compares he basic schemes of an open- and a closed-loop TDCs. The ime resoluion of boh of hem is limied o one gae delay (i.e., abou 15 2 ps in a 9 nm CMOS echnology). The circui design of he open-loop delay line is easier; however he closed-loop line, or Delay-Locked Loop (DLL), has some advanages, primarily, he independence of he ime resoluion over process volage emperaure (PVT) variaions, since he DLL always divides he inpu period ino N DLL ime inervals, being he N DLL number of delay elemens. This ensures ha he quanizaion noise is always equal o he expeced one. Conversely, in an open-loop line implemened in scaled CMOS echnology, process corners may spread he delay around he nominal value up o ± 5%, increasing

3 EURASIP Journal on Embedded Sysems 3 TDC + Couner f f = f e (a) (b) Figure 2: AD-PLL behavior for FCW = 2.25: (a) posiive edges of and, feedback signals and f f, and error signal f e = FCW ( + f f ); (b) couner/tdc conversion characerisics. he in-band noise uncerainy. Moreover, exra sages in he line are required o measure he whole oscillaor period in he case of a fas corner. An addiional advanage of he regulaed delay line regards he TDC nonlineariy, which can raise he fracional spur level in ADPLLs [4]. A DLL feaures a beer inegral nonlineariy (INL) han an open-loop delay line [7], since i aligns he inpu and he oupu signal edges. Figure 4 shows he simulaed INL roo mean square (r.m.s.) value a each delay cell oupu for a 16-elemen delay-line boh an open-loop line and a closed-loop. In he simulaions, a random Gaussian delay wih r.m.s. value of 5% of he nominal delay was added o each cell. The resul shows ha he DLL improves he INL by a facor 2 in he middle of he line and by a larger facor in he second half of he line. The AD-PLL presened here is inended o be used as a frequency synhesizer in a WiMAX ransmier in he GHz band. In his applicaion, an inegral phase noise of abou 4 dbc is required o he synhesizer. According o Figure 2, he TDC quanizes he oupu phase shifs wih a leas significan bi (LSB) equal o 2π (τ/t ), where τ is he ime resoluion of he TDC. This LSB is, in urn, relaed o he number B of bis of he TDC. Thus, LSB = 2π 2 B. The expression of he phase specrum can be obained by assuming uniform ampliude disribuion and whie specrum for his quanizaion noise. The resuling quanizaion noise in he AD-PLL specrum is SSCR = (4π 2 2 2B )/ 12 f, wihin he AD-PLL bandwidh. ( SSCR is he Single- Sideband o Carrier Raio.) Seing his bandwidh o few hundreds of khz, and he DCO phase noise o 12 dbc/hz a 1 MHz offse wih 1- MHz corner frequency (beween 1/f 3 and 1/f 2 regions), four TDC bis are sufficien o mee he inegral phase noise requiremens. As a consequence, he delay line needs 16 delay elemens and he delay τ a 3.8 GHz should be abou T /16 17 ps. This corresponds o an in-band noise plaeau in he PLL specrum of abou 95 dbc/hz. In order o mee he noise requiremens, he spurious ones need o be lower han 5 dbc. 4. DLL-Based TDC The key advanage of he AD-PLL is he reduced number of analog block and of exernal componens. Thus, he DLLbased TDC should avoid he use of analog blocks, such as charge pump and loop filer, as much as possible. In he implemened TDC, shown in Figure 5, boh he phase deecor (PD) and he filer are digial circuis. The PD is a se-rese flip-flop, which acs as a one-bi TDC, indicaing which one of he wo signals leads he oher one. These circuis are someimes erred as lead-lag or bang-bang (BB) phase deecors. The digial filer is an inegraor, followed by a 6-bi curren-seering DAC which regulaes he bias curren of he delay cells. The DAC LSB ses he minimum variaion of he cell delay Δτ min (abou 4 fs), which can be considered as he LSB in ime domain of he regulaion loop. Since he delay line feaures 16 sages, he delay line can cover a maximum delay variaion of (4 fs) (16) (2 6 ) 4 ps. e ha his figure in pracice maches he required dynamic of he DLL, which is he difference beween he period of he lowes frequency signal (3.3 GHz) and he period of he fases signal (3.8 GHz). To add some margin for PVT variaions, a coarse uning has been realized by adding hree swiched

4 4 EURASIP Journal on Embedded Sysems DL ou PD PD ou Filer I une DL in τ τ τ τ τ τ τ τ D Q D Q D Q D Q D Q D Q D Q D Q (a) (b) Figure 3: TDC based on (a) open-loop, and (b) closed-loop delay line. INL (LSB) TDC bin Figure 4: Simulaed INL of a TDC based on an open-loop line (circles) and on a closed-loop line (riangles). DL in 8 CK S R Q PD ou 1 Σ PD Filer Tune n DAC I une τ τ τ τ DL ou Regulaor DQ DQ DQ DQ Figure 5: Schemaic of he DLL-based TDC wih bang-bang phase deecor. capaciors of he same value a he oupu of each cell. This coarse conrol is se by he overflow/underflow of he loop inegraor. As shown in Figure 5, he PD operaes a he DCO rae ( GHz). A his frequency, however, he loop filer and he DAC would dissipae an excessive amoun of power and he filer would require a cusom design. This dissipaion can be reduced by noing ha no informaion is los, if he filer clock is obained by frequency-division of he DCO signal. In fac, he cell delay, and in urn he PD oupu, changes only afer a variaion of he filer oupu, ha is, a he same rae of he digial filer clock. The only disadvanage of his choice is an increase of he DLL lock ime. As reasonable rade-off has been found by dividing he inpu frequency by 8 and limiing he maximum clock frequency f ck below (3.8 GHz)/8 = 475 MHz, his value guaranees a he same ime a lock ime for he maximum frequency sep of abou 4 ns, which is less han wo erence cycles of he AD- PLL, and he possibiliy of using sandard cells and auomaic synhesis ools in he filer design [8]. The presence of he BB phase deecor and he quanizaion of he cell delay τ which can be varied wih finie resoluion Δτ min. generaes a limi cycle in he DLL. A simple illusraion of his behavior is skeched in Figure 6. I is necessary o know ha he implemened inegraor inroduces, as usual, one exra clock period of laency. According o Figure 6, in = he cell delay τ is below he arge delay value; so, he phase deecor PD ou changes is sae and becomes one. This new value is read by he filer a he following clock rising edge and he filer oupu sars decreasing one clock period laer a = 1. Consequenly, he cell delay τ sars o increase. When τ exceeds he arge value (a = 2 ), he PD oggles and he dual siuaion akes place. In pracice, he limi cycle period is T lc = 6T ck, where T ck = 1/f ck is he filer clock period. The peak-o-peak ampliude of he cycle a he inegraor oupu is 3τ. This behavior is in accordance wih he general resuls presened in [9]. This limi cycle modulaes periodically each ime bin of he TDC and a spurious one will appear a boh he TDC and he AD-PLL oupu. Since he limi cycle a f ck /6is sampled by he TDC flip-flops a f, he spurious ones a he TDC oupu are expeced o appear a f ck /6 kf, wih ineger k. In pracice, being f ck /6 = f /48, he DCO frequency f in he GHz range, and f = 4 MHz, he spurious one will fall beween abou 8 khz and 11 MHz, depending on he DCO frequency. 5. Time Skew in he Couner-TDC Ensemble The presence of a ime skew beween he couner and he TDC inpus is almos unavoidable. However, i causes an error in he feedback signal. e ha he phenomenon highlighed in his secion is general and i does no depend

5 EURASIP Journal on Embedded Sysems 5 CK Inergraor laency 1 z 1 Couner skew PD ou 1 + τ 2 Figure 6: The limi cycle in he DLL. Targe delay on our paricular TDC implemenaion. We consider a delay skew applied o he couner inpu, as shown in Figure 7. In his siuaion, he couner will be driven by he delayed DCO signal, indicaed as, while he TDC inpu is he original DCO signal, ha is, in Figure 7. w, he insan in which he TDC overflows (or underflows) and ha in which he couner incremens (or reduces) is seady-sae oupu does no coincide. To illusrae his behavior, we consider again he example discussed in Secion 2. The waveforms resuling from he applicaion of skew are skeched in Figure 8(a). Because of he skew, he couner oupu incremens by 3 in he following erence period wih respec o Figure 2. Insead, he TDC oupu is unperurbed. In his figure, he ime skew has been assumed o be equal o.25 T, bu he same and f f graphs would have been obained for < skew.25 T. The ne resul of he ime shif of he sequence is he generaion of a periodic bipolar glich (wih frequency f spur ) in he error signal f e. The average value of f e is zero; heore he loop does no respond; however, his periodic disurbances produces spurious ones a he oupu. The signal R e, which is given by he accumulaion of f e and is proporional o he phase error, will be a periodic squarewave wih duy cycle D = ( f spur /f ). The same impairmen can be visualized by combining again he TDC and he couner conversion characerisics as shown in Figure 8(b). The effec of he posiive ime skew is he generaion of holes in he characerisic. A seady sae, his saircase is swep, going up from one sep o anoher one. Theore, depending on he iniial phase, he converer inpu may periodically fall ino he holes. The resuling phase error is as large as one LSB of he coarse converer, ha is, of he couner. Evaluaing he fundamenal frequency f spur and he ampliude A spur of he spur in he previous example is paricularly simple. Assuming ha he spur fundamenal falls ou of he PLL band, A spur can be calculaed following [1]. Thus, f spur = FCW f f A spur = 2 π sin(π D) H ( fspur ) Δ f 4 f spur (1) wih H( f spur ) being he frequency response magniude of he loop filer and Δ f being he DCO frequency resoluion. f f 1 z 1 TDC Figure 7: Time skew beween he couner and TDC inpu signals. The example presened here is paricularly simple, for he sake of clariy. In paricular, he TDC has enough resoluion o deec he fracional par of FCW, which makes his case similar o wha happens in a sandard PLL wih an ineger division facor. In oher cases, he behavior may be slighly more complex; he main issues o be considered are lised as follows: (i) If skew is larger han.25 T (in our example), he couner sequence will be shifed wih respec o he TDC sequence by more han one erence cycle. So, he f e sequence will include some s beween +1 and 1 and is inegral R e will be a sequence of pulses, whose duy cycle D depends on he number of s in he f e sequence. Thus, maximum spur ampliude in (1) occurs when D =.5. (ii) We have arbirarily assumed a phase relaionship beween and, given he uncerainy of he TDC quanizaion. Theore, in our example, a favorable ime delay beween and exiss which prevens o fall ino he holes of he characerisic in Figure 8(b) and o generae gliches. (iii) When FCW s finer han he TDC resoluion (which is he common siuaion), he phase relaionship beween and changes. Thus, he condiion in (ii) may periodically occur. As a consequence, he f e and R e sequences show some missing gliches, hus slighly alering he resul in (1). 6. Glich-Correcion Logic A possible counermeasure o he glich problem presened in he previous secion has been already proposed in [11]. In ha work, he derivaive of f e is moniored, and is magniude is higher han.5, f e is decreased/increased by 1. In his way, he glich in Figure 8 is removed. However, his soluion has he disadvanage of alering he ransien behavior. If a large variaion in he DCO frequency occurs, which causes a sep of +1 (or more) in he f e value, he loop would no be able o rack he frequency, unless he correcor is disabled. In he case of an unexpeced frequency sep, ha may seriously affec he lock behavior. Insead, he circui proposed in he presen work moniors and f f, separaely. I removes he glich from he feedback signal and ses a flag F, which allows o apply he variaion simulaneously o he f f overflow/underflow.

6 6 EURASIP Journal on Embedded Sysems 1 2 TDC Couner f f f e = (a) (b) Figure 8: AD-PLL behavior for FCW = 2.25 in he presence of a ime skew beween couner and TDC: (a) posiive edges of and,, f f,and f e. (b) Couner/TDC conversion characerisic. Δ i = FCW i Δ i /= Δ i /= 1 Δ i 1 f f < f f > Yes F = 1 f C = 1 F C = 1 Nex edge Yes f C = F C = Yes f e = FCW ( + f f )+ f C F = F + F C Yes f C = F C = Yes F = +1 f C = +1 F C = +1 Figure 9: Flow char describing he operaing principle of he glich correcor when FCW f.5. The circui operaion is shown in he flow char in Figure 9, which is valid for FCW f.5. A he beginning, he flag F is iniialized o. Three main siuaions are aken ino accoun. (a) If he ineger frequency error Δ i = FCW i differs from or 1, hen he loop is considered o be ou of lock and no correcion is applied. Thus, f e is simply given by FCW ( + f f )andf is no varied. (b) In imesamp 1 in he example in Figure 8(a), is no incremened wih respec o FCW i, while he TDC overflows. Theore, Δ i = and f f <. Assuming F =, he value of f e is FCW ( + f f ) 1, hus canceling he glich, and F is decremened by 1. (c) In imesamp 2, is incremened wih respec o FCW i, while he TDC does no overflow. Theore, Δ i = 1and f f >. If his siuaion occurs afer (b), he flag F = 1. Thus, he algorihm ses f e o FCW ( + f f ) + 1, canceling again he glich, and F is incremened by 1, reurning o zero. I is easy o check ha if a sudden change in he DCO frequency causes a sep of +1 in Δ i, hanks o he adopion of he flag F, his circui removes only he firs sample +1 of. Then, i leaves he loop operaing normally. Thecaseinwhich.5 < FCW f < 1 is no repored here, for he sake of breviy. In ha case, he algorihm applies a correcion when Δ i = and he TDC underflows and when Δ i = 1 and he TDC does no underflow. The signs of he correcions of f e and F are swapped wih respec o he case in Figure Simulaions Resuls The schemaic of he whole AD-PLL is skeched in Figure 1, where also he deails of he loop filer are evidenced. The circui has been designed in 9 nm CMOS echnology.

7 EURASIP Journal on Embedded Sysems 7 FCW Glich correcor f e 1 1 z 1 R e β 1 1 z 1 α + z 1 DCO f f 1 z 1 1 z 1 Couner TDC Regulaor Tune τ τ τ τ D n D n 1 Regiser D 2 D 1 Figure 1: Full block schemaic of he designed AD-PLL. Skew-induced glich 2 2 DLL limi cycle SSB phase noise (dbc) SSB phase noise (dbc) RBW = 1.8 KHz Frequency offse (Hz) RBW = 1.8 KHz Frequency offse (Hz) Figure 11: Oupu specrum of he AD-PLL when he glich correcor is disabled. The dominan spur is induced by he ime skew beween couner and TDC. Figure 12: Oupu specrum of he AD-PLL when he glich correcor is enabled. The dominan spur is induced by he DLL limi cycle and i is below 5 dbc. The digial PI loop filers feaures α = 1andβ = 16. The DCO uning range covers he 3-4 GHz bandwidh, wih 64 coarse characerisics. Each characerisic sweeps abou 2 MHz wih a fine uning resoluion Δ f = 15 khz. The closed-loop bandwidh is abou 37 khz. The AD-PLL is simulaed by adding a 1/f 2 phase noise o he DCO signal of 12 dbc/hz a 1 MHz offse from he carrier. The fracional FCW word is se o (95 + 1/ /2 14 ) and he erence frequency is 4 MHz. Theore, he oupu frequency is GHz. The ime skew beween couner and TDC is assumed o be abou skew = 15 ps, which is slighly less han one TDC LSB. In he absence of he glich correcor, we expec from (1) he spur fundamenal o be locaed a f spur = (1/16+351/2 14 ) 4 MHz = MHz and o have ampliude A spur beween 1 and 24 dbc, depending on he duy cycle D of he R e signal. The oupu specrum, simulaed when he glich correcor is disabled, is shown in Figure 11. The dominan spur is a MHz wih power of 13 dbc, as prediced from heory. When he glich correcor is enabled, he skew-induced spurs disappear compleely, as shown in Figure 12. The remaining dominan spur is below 5 dbc, which allows o mee he phase noise requiremens. This spur is caused by

8 8 EURASIP Journal on Embedded Sysems f (GHz) f (GHz) MHz Time (μs) (a) Time (μs) (b) Figure 13: AD-PLL oupu frequency for a 1 MHz inpu sep, when he glich correcor is disabled (a) and enabled (b). he DLL limi cycle, as discussed in Secion 4. Asexpeced, i falls a ( f /48 8 f ) 8 khz. The level of he in-band noise of abou 95 dbc/hz is consisen wih he quanizaion noise of he 4-bi TDC, discussed in Secion 2. In order o highligh he neuraliy of he proposed glich correcor during he lock ransien, a 1 MHz frequency sep has been applied when he glich correcor is eiher enabled and disabled. The oupu frequency (evaluaed as he inverse of he oupu period) is shown for he wo cases in Figure 13. The oupu frequency spikes in he absence of he correcor are caused by he +1 spikes in he R e sequence. Theore, hey are as large as β Δ f = 2.4 MHz. Enabling he correcor allows o cancel ou hose spikes, wihou alering he lock behavior. 8. Conclusions The design of an AD-PLL for he WiMAX bandwidh has been presened. The main focus of his work is he design of he TDC, which ses he in-band noise performance of he synhesizer and, above all, i may be an imporan source of spurious one. To fully exploi he digial-inensive approach, he TDC is implemened as a bang-bang DLL and i designed o guaranee he required ime resoluion. However, he unavoidable ime skew beween he couner and he TDC inpus in he AD-PLL is demonsraed o be responsible of generaing gliches a he PLL comparison node and in urn large spurs in he PLL oupu specrum. A digial glich correcor has been presened which solves his impairmen and i is able o work correcly even during a lock ransien. Acknowledgmen This work was parially suppored by he Communicaion Inegraion Research Lab of Inel Corp., Hillsboro OR. References [1] R. B. Saszewski, K. Muhammad, D. Leipold, e al., Alldigial TX frequency synhesizer and discree-ime receiver for Blueooh radio in 13-nm CMOS, IEEE Journal of Solid-Sae Circuis, vol. 39, no. 12, pp , 24. [2] A. A. Abidi, The pah o he sofware-defined radio receiver, IEEE Journal of Solid-Sae Circuis, vol. 42, no. 5, pp , 27. [3] R. B. Saszewski, J. L. Wallberg, S. Rezeq, e al., All-digial PLL and ransmier for mobile phones, IEEE Journal of Solid-Sae Circuis, vol. 4, no. 12, pp , 25. [4] E. Temporii, C. Welin-Wu, D. Baldi, R. Tonieo, and F. Svelo, A 3GHz fracional all-digial pll wih a 1.8 MHz bandwidh implemening spur reducion echniques, IEEE Journal of Solid-Sae Circuis, vol. 44, no. 3, Aricle ID , pp , 29. [5] C.-M. Hsu, M. Z. Sraayer, M. H. Perro, e al., A lownoise wide-bw 3.6-GHz digial ΔΣ fracional-n frequency synhesizer wih a noise-shaping ime-o-digial converer and quanizaion noise cancellaion, IEEE Journal of Solid-Sae Circuis, vol. 43, no. 12, Aricle ID , pp , 28. [6] E. Aalla, I. Bashir, P. Balsara, K. Kiasaleh, and R. B. Saszewski, A pracical sep forward oward sofware-defined radio ransmiers, in Proceedings of he 6h IEEE Dallas Circuis and Sysems Workshop on Sysem-on-Chip (DCAS 7), pp , Dallas, Tex, USA, vember 27. [7] S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmi-Landsiedel, A local passive ime inerpolaion concep for variaion-oleran high-resoluion ime-o-digial conversion, IEEE Journal of Solid-Sae Circuis, vol. 43, no. 7, pp , 28. [8] M. Zanuso, P. Madoglio, S. Levanino, C. Samori, and A. Lacaia, Time-o-digial converer for frequency synhesis based on a digial bang-bang, o appear in IEEE Transacions on Circuis and Sysems I. [9] N. Da Dal, A design-oriened sudy of he nonlinear dynamics of digial bang-bang PLLs, IEEE Transacions on Circuis and Sysems I, vol. 52, no. 1, pp , 25. [1] A. Lacaia, S. Levanino, and C. Samori, Inegraed Frequency Synhesizers for Wireless Sysems, Cambridge Universiy Press, Cambridge, UK, 27. [11] M. Lee, M. E. Heidari, and A. A. Abidi, A low noise, wideband digial phase-locked loop based on a new ime-o-digial converer wih subpicosecond resoluion, in Proceedings of IEEE Symposium on VLSI Circuis, pp , Honolulu, Hawaii, USA, June 28.