DEFECT-TOLERANT FPGA SWITCH BLOCK AND CONNECTION BLOCK WITH FINE-GRAIN REDUNDANCY FOR YIELD ENHANCEMENT

Transcription

1 DEFECT-TOLERANT FPGA SWITCH BLOCK AND CONNECTION BLOCK WITH FINE-GRAIN REDUNDANCY FOR YIELD ENHANCEMENT Anhony J. Yu Guy G. F. Lemieux Deparmen of Elecrical and Compuer Engineering Universiy of Briish Columbia, Vancouver, BC, Canada { anhonyy lemieux ece.ubc.ca ABSTRACT Fuure process nodes have such small feaure sizes ha here will be an increase in he number of manufacuring defecs per die. For large FPGAs, i will be criical o olerae muliple defecs [6]. We propose a number of changes o he deailed rouing archiecure of island-syle FPGAs o olerae muliple random, disribued inerconnec defecs wihou re-rouing and wih minimal impac on signal iming. Our scheme is a user opion prebuil ino an archiecure, requiring +% area for addiional muliplexers. Unused (spare) wiring racks are also needed, bringing oal overhead o 4% o olerae suck-a or open fauls, or 34% o include bridging. User circuis ha do no fully sress he rouing nework already have hese racks freely available. The delay penaly is programmable: 5 % if defec raes are expeced o be sufficienly low, bu can be as high as 5% if defec raes are high. Our schemes can olerae more han inerconnec defecs for large array sizes of 8 8. Unlike row/column redundancy schemes, our schemes are scalable: hey naurally olerae more defecs as he FPGA array size increases. This work is he firs deailed analysis of fine-grained defec-oleran schemes in FPGAs.. INTRODUCTION Field programmable gae arrays (FPGAs) are large inegraed circuis comprised of programmable logic blocks and programmable rouing. Their size, densiy and regular layou makes hem aracive for aggressive uning in he laes echnology processes. As such, hey are also prone o manufacuring defecs [6]. Since FPGAs are rouing dominaed, defecs are more likely found in he inerconnec han in he logic blocks. This makes he abiliy o olerae defecs in he inerconnecion nework exremely imporan. In his paper, he inerconnecion nework encompasses he physical wiring, he swich elemens, and he configuraion bis found in boh he swich block and he connecion block. Tradiional defec-oleran schemes involve he use of enire spare rows and/or columns in he array of logic blocks. This mehod is capable of oleraing clusers of defecs, however he consolidaion of spare resources severely resrics is abiliy o olerae muliple disribued defecs. Our approach addresses his problem by embodying a fine-grain approach o redundancy: spare resources are disribued in every rouing channel. This paper presens a new swich and connecion block archiecure ha is capable of oleraing muliple disribued defecs wihin he inerconnecion nework. Our approach is based on defec avoidance by shifing. As shown in Figure, shifing allows signals o roue around a defec. We show ha his can be done in a conrolled, localized fashion wihou re-rouing. spare defec a) original rouing soluion b) avoiding a defec Fig.. Shifing signals o avoid defecs. To successfully correc a defec, we need o know where he defecs are. One such way o provide his informaion is hrough he use of a lis of defecive resources, called a defec map. This map can be sored on-chip in non-volaile sorage, or in an off-chip daabase indexed using a unique on-chip ID. When an FPGA is being programmed, he defec map specific o ha FPGA is called up and he correcion is applied. Our archiecure is designed so ha correcion can be applied hrough bisream manipulaion alone. The correcion can be applied during programming or bisream generaion. I can even be applied by means of an embedded processor wihin he FPGA. Wih his laer mehod, defec correcion can be compleely hidden from he user. Our archiecure has some disadvanages. Firs, like any sparebased redundancy scheme, i requires some amoun of overhead which canno be avoided. We evaluae a number of deailed variaions o our scheme and precisely quanify he impac on area, delay and yield. Nex, our archiecure does no olerae ransien fauls (single even upses), clusers of defecs, or defecs in he logic blocks. To address hese laer wo issues, our archiecure can be complemened wih spare row/column echniques, alhough here are oher possibiliies as well. Despie hese disadvanages, here are also noable advanages: Toleraes muliple disribued random defecs, Scalable: more defecs are oleraed in larger FPGA arrays, Defec correcions do no change signal iming, Defec correcions can be applied very quickly, and Crossalk defecs [9] can be repaired by separaing nes.. PREVIOUS WORK Faul redundancy can be loosely classified ino hree groups: sofware redundancy, hardware redundancy and run-ime redundancy.

2 Each of hese approaches have heir advanages, and ypically rade off beween ime (criical pah delay and processing/applicaion ime) and resources (silicon area, exernal sorage, ec). Our approach is a combinaion of sofware and hardware redundancy... Sofware-based Redundancy In a sofware redundancy approach, CAD ools are used o map around fauly resources. This mehod ypically has no hardware overhead. The effeciveness and efficiency of correcion is dependen on he abiliies of he CAD ools. Furhermore, his mehod is impracical in a producion environmen because: ) generaing a unique placemen and rouing soluion for each FPGA is imeconsuming, and ) verifying iming of each soluion is impossible. Xilinx solves hese problems wih heir EasyPah [] echnology. Raher han forcing he configuraion bisream o avoid he defecs, Xilinx forces he defecs o avoid he bisream. They do his by obaining he cusomer s final bisream and selecing chips which conain defecs only in he unused porions of he chip. Two oher approaches have been proposed o solve hese problems. The firs mehod is o precompue a number of placemen and rouing soluions for a paricular design. Each precompued soluion differs by is resource usage. When programming a defecive chip, defec correcion simply involves selecing he appropriae soluion (one ha does no use he defecive resource(s)) [, 3]. The second mehod requires he reservaion of spare resources. By carefully avoiding he use of cerain resources, i is possible o avoid defecs by shifing he enire design [9] by one row or column in he array. Design shifing can be applied in a relaively shor amoun of ime. Wihou special hardware suppor, however, shifing resuls in a sligh variance in IO iming. I can also be complicaed by heerogeneous (memory or DSP) blocks in he array. Furhermore, o suppor muliple defecs, hey mus be perfecly aligned o he spare locaions... Hardware-based Redundancy Hardware redundancy involves he addiion of exra or spare resources. The spare resources allow defecive pars o be swapped wih empy spare ones. This exchange reduces correcion ime since he ime required o swap is ypically less han he ime needed o generae a new placemen and rouing soluion. The spare row and column echnique is one of he firs hardware redundancy approaches [] and has been successfully applied in indusry [3]. This mehod adds one spare row and one spare column o he layou. I also requires he rouing nework o be modified. In he even of a defec, he row or column conaining he defec is bypassed, and he spare row or column is uilized. The abiliy o bypass enire rows and columns gives his approach he abiliy o olerae defec clusers. Unforunaely, published research does no presen he delicae circui deails needed o perform he bypass. Alera paens provide some insigh [4] and indicae ha addiional circuiry is required for bypassing. Redundancy can be implemened a a finer level. For example, addiional connecions can be added inside he swich block o olerae one ransisor defec per swich block [8]. Unforunaely, his approach is impracical because i significanly alers delay..3. Run-ime Faul Tolerance Faul olerance can also be addressed during run-ime. As ransisor sizes shrink, FPGAs become suscepible o ransien fauls such as single even upses [5, ]. To alleviae his problem, echniques have been developed o deec and correc ransien errors hrough reprogramming or bi scrubbing [, 7]. However, i is no clear wheher hese echniques can be exended o correc permanen manufacuring defecs; simply reprogramming is insufficien..4. New Approach The proposed approach is a combinaion of sofware and hardware redundancy. Addiional rouing resources are added o faciliae and simplify defec correcion. A new swich block design allows defecs o be bypassed by compuing a new configuraion for a small, localized par of he FPGA. This ensures ha areas ouside of he neighbourhood of he firs defec can sill olerae oher defecs. The affeced neighbourhood is so small ha defec correcion can be achieved by modifying he configuraion bisream alone. The defec correcion also inroduces minimal iming disurbances. 3. ARCHITECTURE AND IMPLEMENTATION DETAILS This secion describes he archiecure and implemenaion deails of our approach, he ype of defecs we consider, how defec correcion is applied, and he limiaions of our design. 3.. Swich Block Changes for Defec Tolerance The proposed defec redundan swich block builds upon he direcional swich block described in [6], which is no defec oleran. Figure shows boh a deailed and high-level represenaion of he direcional swich for lengh wires. In he high-level represenaion, individual wires and buffers are replaced by arrows. To make his swich block defec oleran, we wrapped wo layers of muliplexers around he direcional swich. This is shown as he wo ouer layers in Figure 3. The ouer-mos layer represens he shif-avoid layer of muliplexers (omux), and he middle layer represens he shif-resore layer of muliplexers (imux). Clearly, his exra muliplexing coss in area (%+) and delay (5%+). The omux allows signals o seer away from a downsream defec. By means of hese muliplexers, signals roued on rack can be shifed up o racks + or +. When here is a defec on rack, he defec is avoided by shifing up all signals roued on racks. Signals on racks < remain in place. Clearly, he shifing requires ha here be spare rouing racks. These spares incur abou % area overhead for each spare se, bu his amoun diminishes as device channel widhs increase. The imux is used o reverse or resore he shif-avoid acion in an upsream swich block. These muliplexers allow a signal on rack + or + o shif down o rack, hereby nullifying any upsream shifing acion. To keep he effecs of rack shifing localized, we have designed he swich block such ha any signal leaving a perurbed neighbourhood can be resored o he original rack number. This localizaion allows our archiecure o olerae muliple disribued defecs. To reduce he delay of long nes, a bypass pah similar o [7] is inroduced ino he swich block. This bypass pah connecs a sraigh-hrough wire endpoin direcly wih he corresponding omux on he opposie side of he swich block. Bypassing he imux and he direcional swich creaes an alernae, reduced delay pah for signals ravelling across a channel.

3 , +/-,+/ , +/-, +/-, +/-, +/ A) Deailed Represenaion B) High Level Represenaion IMUX Fig.. Direcional swich block., +/-,+/- 3.. Swich Block Changes for Area Reducion In an aemp o reduce area and delay overhead, we considered reducing he flexibiliy of he direcional swich, F s. F s is he number of oher wires conneced o a given swich block wire [8]. By decreasing F s, we can shrink he size of he muliplexers in he swich, hence improving boh area and delay. Wih long wires, he flexibiliy a he end swich blocks or endpoins is differen han a he middle swich blocks or midpoins. We considered he following swich flexibiliies:. The E3M swich is he direcional swich described in [6]. I has F s = 3 for endpoins and F s = for midpoins.. The E3M swich also uses F s = 3 a endpoins. However, midpoins are reduced o F s =, meaning hey can only urn eiher lef or righ (no boh). The urn direcion alernaes along he lengh of a wire. 3. The EM swich has F s = for endpoins and F s = for midpoins. Endpoins include only sraigh-hrough connecions. Turns are handled in he same manner as E3M Connecion Block Changes As a consequence of rack shifing, signals ha were once roued on rack can now reside on racks + or +. To accommodae for his variabiliy, he connecion block mus also be modified. In our archiecure, he CLB oupus do no need o be modified because hey are already fully conneced o all of he racks. However, he CLB inpu conneciviy is increased by adding he addiional required connecions o he shifed racks. This modificaion is shown in Figure 4ab. Iniially, he CLB inpus are conneced o half of he rouing racks. To adjus for he rack shifing, for every rack ha is conneced o a CLB inpu, we ensure ha racks + and + are also conneced o he inpu. Thus, if a signal ges shifed up by or, he CLB can sill exrac he correc signal. Clearly, we can reduce his overhead by maximizing he number of consecuive racks ha are conneced o a paricular CLB inpu, as shown in Figure 4c. However, his opimizaion is lef for fuure work. Fig. 3. High-level view of defec-oleran swich block. a) Orginal C Block 3.4. Suppored Defecs b) Faul Redundan C Block Fig. 4. Connecion block modificaions. vs. c) C Block Opimizaion Wih our schemes, inerconnec defecs can be caegorized ino hree disjoin classes: single-lengh, double-lengh and inolerable defecs. Examples of he firs wo classes are shown in Figure 5. For example, if an open or suck-a faul occurs on he wire, or here is a suck-a faul in he wire driver or he oupu of he omux, he defec is a single-lengh defec. In his case, one swich block avoids he defec and all adjacen downsream swich blocks do he resore. This kind of defec is isolaed o one wire lengh. Figure 5a demonsraes how a single-lengh defec is correced using wo parallel sraigh-hrough signals. Wih single-lengh defecs, he change is purely localized in he channel o a group of wires wih common sar and ending poins in he array. Such a group of wires is called a rackgroup. If a defec is found in any of he muliplexers (aside from he oupu of he omux), he defec is caegorized as a double-lengh defec. Due o heir locaion, hese defecs acually impair he defec-correcing abiliy of he curren swich block. To fix his, he swich block of he adjacen upsream rackgroup is used o avoid he defec, and he downsream swich blocks do he resore. Hence, his kind of defec requires wo wire lenghs o correc. Figure 5b indicaes how a double-lengh defec spans wo adjacen rackgroups: he upsream rackgroup on he lef, and he defecive one on he righ. In fac, for his example here are addi-

4 Enhanced Swich Block Enhanced Swich Block (Porion of) Regular Swich Block IMUX Conenion 3 3, -, +, -, + a) Iniial imux Design wih Conenion (Porion of) Enhanced Swich Block Embedded IMUX No Conenion Wire Driver Equivalen Defecs 3 3 a) Single-lengh Defecs Enhanced Swich Block Enhanced Swich Block, +, + b) Embedded imux Design Avoids Conenion Fig. 6. Embedding imux o avoid conenion. Equivalen Defecs b) Double-lengh Defecs Fig. 5. Two classes of olerable defecs. If his mus be implemened by wo +/- shifs, he surrounding neighbourhood ha mus be defec-free is considerably larger han he double-lengh defec siuaion and his also harms yield. There exiss a class of inolerable defecs ha is no shown in Figure 5. This includes power/ground shors and clusers of defecs. The firs ype of defec canno be oleraed. However, i is possible o olerae he laer by complemening our archiecure wih a spare row/column echnique, e.g. [] Modes of Operaion and True Overhead ional upsream swich blocks (above and below) ha reside in he verical channel. As shown in Figure 6a, conenion arises when a sraigh-hrough signal is shifed up ono a rack ha is expeced o be available for urning signals. To avoid conenion, signals on racks in he verical channel mus be shifed before arriving. All of he swich blocks in he verical channel wihin a disance of one wire lengh mus paricipae in correcing a doublelengh defec. Hence, hey mus all be defec-free (or conain a defec in exacly he same rack). This resuls in a fairly large (bu sill localized) neighbourhood which mus be defec-free. The upsream pre-shifing jus described is one way o solve he conflic problem wih double-lengh defecs. A more robus soluion is shown in Figure 6b. Here, he imux is embedded wihin he swich block and he inernal swich block muliplexers are duplicaed. This shrinks he requisie defec-free area o jus he wo adjacen rackgroups. We find his increases oal area by abou 4%, bu due o mux sizes his also improves delay by a similar amoun. Muliplexer embedding also produces beer yield resuls. Wire bridges and cerain source-drain shors in he muliplexer are usually caegorized as double-lengh defecs. These defecs have he poenial o render wo adjacen racks as unusable. To avoid such a defec, he upsream swich block(s) mus shif racks up by and he downsream swich blocks mus shif down by. Our archiecure makes defec redundancy an opion o he user. This means we expec FPGA devices o operae in wo modes: normal defec-oleran mode and recovery mode. The normal mode assumes he cusomer will buy imperfec, low-cos devices by applying defec correcion. In his mode, he rouing sofware reserves a spare rouing rack in each rackgroup. This reduces he number of rouing racks available o he applicaion, bu he spares are needed for defec correcion. For many applicaions which do no sress he rouing nework, his is an easy way o lower device cos. The recovery mode assumes he cusomer will buy perfec devices a a price premium. In his mode, he rouing sofware uses he addiional imux and omux rouing muliplexers o increase he flexibiliy of he inerconnec. In essence, he rouer is using he redundan resources o recover some area/delay efficiency ha was sacrificed when hey were added. This mode is used for hose few applicaions ha have high inerconnec demands where he resuling increase in inerconnec flexibiliy is even more helpful. However, in his mode, here is no naural abiliy o olerae defecs. When recovery mode is used, our resuls show an increase of % in area and 6% in delay. Recovery mode is he rue over- Two spares are needed for devices wih bridging defecs, which may be sold a even lower cos.

5 ... 6: MUX... 3: MUX 4: MUX Arch. imux implemenaion imux - shif omux + shif EM embedded Y Y EM embedded N Y EM embedded N N fla Y Y encoded Y Y EN encoded N Y EN encoded N N IMUX Table. Defec-oleran swich implemenaions. Fig. 7. HSPICE model for delay characerizaion. head cos of our redundancy scheme. I is he addiional cos imposed on aggressive applicaions wih high inerconnec demands. When normal mode is used, he overhead appears o be higher because spare racks are also couned as overhead. This is misleading! Applicaions wih low inerconnec demands already have an abundance of unused rouing racks, so his exra capaciy is already buil-in. The cusomer has already paid for hese unused rouing racks, so here is no real end-user cos o supplying hem. Our redundancy scheme merely finds a use for hese free racks by calling hem spare racks Deailed Transisor-level Design The ransisor circui model used for HSPICE simulaions is shown in Figure 7. The componens in he circui (from lef-o-righ) are: inpu buffer, direcional muliplexer, srenghening buffer, shifresore muliplexer (imux), shif-avoid muliplexer (omux), apered driver and he wire model wih loads. For area consideraions, he direcional muliplexer is implemened using a ree of minimum-sized ransisors. This allows us o use encoded conrol lines and reduce SRAM usage. We also assumed boh rue and complemened oupus are available from a 6-ransisor SRAM cell. The omux is implemened using a decoded one-level muliplexer of minimum-widh pass ransisors. Each pass ransisor is conrolled by an independen SRAM cell. The moivaion for his is o reduce delay. We explored 3 differen implemenaions of he imux: decoded, encoded and embedded. The decoded muliplexer is idenical in implemenaion as he omux. This kind of muliplexer rades area for delay. The encoded imux is buil like he direcional muliplexer. I rades delay for area. As menioned earlier, i is also possible o embed he imux ino he direcional muliplexer. This enhanced muliplexer is buil by duplicaing he inpus of he direcional muliplexer for rack + and +, and connecing hem o he direcional muliplexer for rack. An embedded imux allows signals o urn and shif a he same ime. This improves yield wih double-lengh defecs a he expense of some area. By varying he implemenaion of he imux and shifing abiliy of he muliplexers, we obained 7 differen defec-oleran implemenaions. The +/- shifs use addiional area o improve yield of bridging defecs. The aribues and differences beween he swich implemenaions are summarized in Table. The area and delay performance of he implemenaions are also sensiive o he precise ransisor-level circui design of he muliplexers and buffers. We used he procedures described in [5, 6] o deermine he bes ransisor sizes for lowes area-delay produc. Delay resuls are compued from HSPICE simulaions of TSMC s 8nm echnology Limiaions In order o implemen our redundancy scheme, we assume ha FPGA and VLSI esing sraegies can idenify he defec locaions o produce a defec map. This map may be provided by he vendor or even generaed by he user. Furhermore, he defec map does no need o be overly deailed. For each defec, i mus idenify he wire segmen locaion in he array (x, y and rack numbers) and ype (single- or double-lengh). Bridges are adjacen defec pairs. Our mehod of dealing wih bridging defecs assumes ha rouing racks wihin he same channel are laid ou beside one anoher. This may no be a realisic assumpion since here are many facors ha influence he layou of an FPGA. Our soluion should only be viewed as a general approach. To fully proec an FPGA from bridging defecs, he final FPGA layou mus be considered. As described earlier, defecs mus be surrounded by some defecfree resources for successful repair. As a resul, our approach canno olerae clusers or closely-spaced defecs. To reconcile his shorcoming, i is possible o complemen our archiecure wih a spare row/column echnique []. Finally, defecs in he logic block have been ignored in his paper. This issue has been addressed in he pas [, 3, 4]. We feel hese echniques, or a spare row/column echnique, can be used o complemen our inerconnec-based schemes Trade-offs In our archiecure, area and delay rade-offs can be made in wo places. Firs, he implemenaion of muliplexers can be varied: reducing muliplexer levels by flaening increases area bu improves delay. Second, he addiion of a bypass pah also increases area bu improves delay. Nex, here are rade-offs beween he amoun of defec olerance (yield) and area or delay. Firs, we can eliminae he abiliy o shif by wo. This reduces he size of he shifing muliplexers. To coninue o olerae bridging and source-drain shors, we require wo + shifs followed by wo - shifs. In fac, any combinaion of shifs, a + shif followed by wo -, wo + followed by a - is accepable. However, changing he shifing naure of he archiecure increases he number of defec classes and he repair lengh. An increase in repair lengh negaively affecs he number of defecs we can olerae. Second, usage of he bypass pah improves delay, bu his increases he repair lengh and consequenly lowers yield.

6 .5.5 Normalized Area (E3M w/ no redundancy) Normalized Delay (E3M w/ no redundancy) EM EM EM EN EN EM-NB EN-NB EM EM EM EN EN EM-NB EN-NB E3M-NRST E3M-Normal E3M-Recovery Implemenaion + Archiecure E3M-NRST E3M-Normal E3M-Recovery EM-NRST EM-Normal EM-Recovery Implemenaion + Archiecure Fig. 9. Delay of defec-oleran implemenaions. Fig. 8. Area of defec-oleran implemenaions. 4. RESULTS The new archiecural feaures were incorporaed ino an enhanced version of he VPR place and roue ool, VPRx [6], which now suppors direcional wires [5]. VPRx was hen used o map he larges MCNC benchmark circuis [] ino an island-syle FPGA consising of direcional lengh 4 wires and CLBs conaining eigh 4-inpu LUTs. The area and criical pah delay resuls we presen are he geomeric averages of all benchmarks as repored by VPRx. The yield resuls were obained from Mone Carlo simulaions. 4.. Area Rouing experimens wih non-defec oleran swich blocks indicaed ha he direcional swich E3M uses.5% less area han E3M and E3M. The average criical pah delay for E3M was also 4.5% lower han he oher wo archiecures. In comparison, he average channel widh increased by 3.% and 8.9% for E3M and EM, respecively. Hence, we seleced he non-defec oleran E3M o be he basis for all area and delay normalizaion (=.). Figure 8 presens he average area overhead for he defecoleran swich blocks. The resuls have been normalized o he non-defec oleran E3M, he bes alernaive wihou defec olerance. When rouing he design in normal mode, wo spare ses of wires were added in he channel for he 7 archiecures ha olerae bridging defecs. Only one spare se of wires is insered for he archiecures ha do no olerae bridging defecs ( archiecures wih -NB). These spare wires were no used during rouing. The EN-E3M archiecure was he mos area-efficien, having an area overhead of 4% for non-bridging defecs and 34% for bridging defecs. The difference in area cos (%) is one se of spare wires. Noice ha he second-bes area archiecure, EM-E3M, needs +4% o embed he imux bu i oleraes more defecs. We should noe ha we do no compare our area resuls o he radiional spare row/column approach. Alhough he area overhead of spare rows/columns is very clear, he addiional circuiry required wihin each CLB o bypass a fauly row/column is nonrivial and is no repored in previous work. Normalized Delay x Normalized Area Delay EM EM EM EN EN Implemenaion + Archiecure Fig.. Area-delay produc comparison. The average criical pah delay for each archiecure is shown in Figure 9. These numbers were obained by rerouing he benchmark circuis using a channel widh equal o he minimum channel widh obained from he defec-oleran area invesigaion plus one addiional se of wires. Unlike he spare wires ha are held in reserve, he rouer was allowed o use his new se of wires o relieve delay increases caused by congesion. Our experimen indicaed ha he EM-E3M archiecure gave he lowes average criical pah delay overhead of 5%. Overhead for he non-embedded version, EN-E3M was 4%. Figure 9 also shows he imporance of he bypass pah. Resuls wihou he bypass are labelled -NRST (no roue on sraigh hrough) and experience higher delay. However, secion 4.4 below explains why using he bypass negaively impacs yield Area and Delay Recovery Nex, we explored he rue area and delay overhead by using he rouing ool in recovery mode. In general, we observed ha he EM-NB EN-NB

7 .8 EM*, SLD (M = 33), EN*, SLD (M = 33) EM, BD (M = 33) Spare R+C (M = 34) EN, BD (M = 33).8 EM, BD (M = 33),, BD (M = 33) EM, BD (M = 33) EM, BD (M = 33) EN, BD (M = 33) Spare R+C (M = 34) EN, BD (M = 33) Yield.6 Yield Number of Defecs (log scale) Number of Defecs (log scale) Fig.. Yield comparison of faul classes. Fig.. Yield comparison of defec-oleran implemenaions. rouer needs lower channel widhs for defec-oleran archiecures in recovery mode han non-defec-oleran archiecures. Hence, he addiional muliplexers do help improve inerconnec flexibiliy. Figure 8 shows he rue area overhead for our defec-oleran implemenaions in recovery mode. The EN-E3M archiecure demonsraed he lowes area overhead of %. The criical pah delay overhead in recovery mode is shown in Figure 9. The EM-E3M archiecure demonsraed he lowes rue delay overhead of 5%. Using he delay and area resuls obained from he previous wo experimens, we compued he area-delay produc for each archiecure in recovery mode. Figure shows ha he EM- E3M archiecure produced he lowes area-delay produc Failure Analysis In addiion o comparing he defec olerance of he differen implemenaions of our archiecure, we also compared he expeced yield of our approach o an archiecure conaining boh one spare row and one spare column. The abiliy o swap a row and a column allows he laer archiecure o olerae muliple defecs wihin he same channel. However, as he array size grows, i becomes increasingly unlikely ha a second defec lies in he same row/column. Hence, his archiecure fails when here are defecs in wo (or more) differen rows or columns. Yield esimaes were obained hrough Mone Carlo simulaions. For a given number of defecs, random fauls were injeced ino he inerconnecs for, differen FPGA dies. When a defec is injeced ino he FPGA, is rackgroup was marked. Neighbouring rackgroups ha mus also be perfec o ensure successful defec correcion were also marked. The firs defec was always olerable, bu yield failure occurs when a new defec lands in a locaion ha was previously marked. To simplify our resuls, we fixed he swich block flexibiliy a E3M since his generally produced he bes area, delay and areadelay produc resuls. We also fixed he channel widh a 8 racks, and iniially fixed he FPGA array size M M o M = 33. Figure shows he resul of our yield analysis for singlelengh defecs (SLD, bes case) and double-lengh bridging defecs (BD, wors case). BD are wors-case because implemenaions wihou +/- shifing abiliy need larger regions o be defec-free. Yield M = 4 M = 5 M = 56 M = 8 M = 64 M = 3 Number of Defecs (EN-E3M, BD) Fig. 3. Yield as die size scales. In pracice, he acual yield will lie somewhere beween he SLD and BD curves. This could be deermined using real manufacuring daa. Figure shows a yield comparison beween our 7 swich implemenaions for double-lengh bridging defecs. Figure 3 shows ha our leas-favourable archiecure can olerae an increasing number of he wors-case defecs as he array size scales (M is increased). The spare row/column approach does no scale beyond defecs a all. This is imporan because i is anicipaed ha devices manufacured in fuure process generaions will have muliple inerconnec fauls [6]. In hese yield esimaes, we are overly opimisic in wo ways. Firs, our resuls assume all implemenaions use he same area. We anicipae ha oleraing muliple defecs significanly offses he area overhead and ulimaely leads o an increase in good die per wafer. Second, our yield resuls assume he delay bypass pah of he omux is no being uilized. If i is uilized, hen we mus eiher: (a) perurb iming when correcing a defec, or (b) limi device defecs o one-per-channel (insead of per-rackgroup) and use he embedded imux.

8 Normalized Area or Delay (E3M w/ no redundancy) EN EM EM EN EN EN EM EM normal mode area overhead normal mode delay overhead EM EM Tolerable Defecs wih Yield >5% (M = 33, BD) Fig. 4. Summary of area/delay overhead vs defec olerance. Arch Area Delay Area Recovery Delay Recovery Yield EM EM EM 5 EN EN Table. Summary ranking of defec-oleran schemes w/ E3M. 5. CONCLUSIONS This paper is he firs deailed sudy of he rue area and delay overheads required for a hardware-based fine-grained defec-oleran inerconnec scheme in FPGAs. We presened a new defec-oleran swich block and connecion block archiecure ha can olerae an increasing number of permanen manufacuring defecs as he FPGA array size scales up. Our proposed scheme handles ens of disribued random defecs. Previous approaches do no scale beyond disribued defecs. However, previous approaches are much beer for clusered defecs. Our approach has a rue area overhead of approximaely % and delay overhead of 4% on aggressive applicaions ha do no wish o be defec-oleran. When defec-olerance is desired, i is emping o include he cos of reserving a spare rack. This increases area overhead o 5 4% and delay overhead o 5 5%. However, we noe ha less aggressive applicaions will already have hese spare (unused) rouing racks available for free, so he acual cos is much closer o he rue area overhead. We have presened a range of implemenaion opions ha have a range of area and delay coss. Of hese opions, EN-E3M has he lowes area, EM-E3M has he lowes delay, and EM- E3M has he highes yield. Table ranks he defec-oleran swich implemenaions in erms of area, delay, area recovery, delay recovery, and yield. Figure 4 gives anoher view of he area/delay overhead and yield performance of he implemenaions. 6. REFERENCES [] Lgsynh93 benchmark se: Version 4.. Technical repor, Collaboraive Benchmarking Laboraory, 993. [] M. Abramovici, J. M. Emmer, and C. E. Sroud. Roving sars: An inegraed approach o on-line esing, diagnosis, and faul olerance for FPGAs. In NASA/DoD Workshop on Evolvable Hardware,. [3] Alera Corp. Alera s paened redundancy echnology dramaically increases yields on high-densiy APEX KE devices. In Press Release, Nov. 7. [4] Alera Corp. In Unied Saes paens 6,34,536, 6,66,559, 6,337,578, 6,344,755, 6,6,337 and 6,759,87, 4. [5] G. Asadi and M. B. Tahoori. Sof error rae esimaion and miigaion for SRAM-based FPGAs. In FPGA, pages ACM Press, 5. [6] N. Campregher e al. Analysis of yield loss due o random phoolihographic defecs in he inerconnec srucure of FP- GAs. In FPGA, pages 38 48, February 5. [7] C. Carmichael, M. Caffrey, and A. Salazar. Correcing singleeven upses hrough Virex parial configuraion. In Xilinx Applicaion Noes, XAPP6 (v.),. [8] A. Doumar and H. Io. Design of swiching blocks oleraing defecs/fauls in FPGA inerconnecion resources. In IEEE Symp. on Defec and Faul-Tolerance, pages 34 4,. [9] A. Doumar, S. Kaneko, and H. Io. Defec and faul olerance FPGAs by shifing he configuraion daa. In IEEE Symp. on Defec and Faul-Tolerance, pages , 999. [] S. Hareland e al. Impac of CMOS process scaling and SOI on he sof error raes of logic processes. In IEEE Nuclear and Space Radiaion Effecs Conference, pages 73 74,. [] F. Haori, T. Sakurai, e al. Inroducing redundancy in FP- GAs. In Cusom Inegraed Circuis Conference, 993. [] W.-J. Huang and E. McCluskey. Column-based precompiled configuraion echnique for FPGA faul olerance. In Field Programmable Cusom Compuing Machines,. [3] J. Lach, W. H. Mangione-Smih, and M. Pokonjak. Efficienly supporing faul-olerance in FPGAs. In FPGA, pages 5 5. ACM Press, 998. [4] V. Lakamraju and R. Tessier. Toleraing operaional fauls in cluser-based FPGAs. In FPGA, pages 87 94,. [5] G. Lemieux, E. Lee, M. Tom, and A. Yu. Direcional and single-driver wires in FPGA inerconnec. In Field- Programmable Technology, 4. [6] G. Lemieux and D. Lewis. Design of Inerconnecion Neworks for Programmable Logic. Kluwer, 4. [7] D. Lewis, E. Ahmed, e al. The Sraix II logic and rouing archiecure. In FPGA, pages 4, February 5. [8] J. Rose and S. Brown. Flexibiliy of inerconnecion srucures in FPGAs. J. of Solid Sae Circuis. [9] S. J. E. Wilon. A crossalk-aware iming-driven rouer for FPGAs. In FPGA, pages 8. ACM Press,. [] Xilinx, San Jose, CA. EasyPah Soluions, 5. hp://